1 //===-- TargetInstrInfo.cpp - Target Instruction Information --------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/Target/TargetInstrInfo.h"
15 #include "llvm/MC/MCAsmInfo.h"
16 #include "llvm/Target/TargetInstrItineraries.h"
17 #include "llvm/Target/TargetRegisterInfo.h"
18 #include "llvm/Support/ErrorHandling.h"
21 //===----------------------------------------------------------------------===//
23 //===----------------------------------------------------------------------===//
25 /// getRegClass - Get the register class for the operand, handling resolution
26 /// of "symbolic" pointer register classes etc. If this is not a register
27 /// operand, this returns null.
28 const TargetRegisterClass *
29 TargetOperandInfo::getRegClass(const TargetRegisterInfo *TRI) const {
30 if (isLookupPtrRegClass())
31 return TRI->getPointerRegClass(RegClass);
32 // Instructions like INSERT_SUBREG do not have fixed register classes.
35 // Otherwise just look it up normally.
36 return TRI->getRegClass(RegClass);
39 //===----------------------------------------------------------------------===//
41 //===----------------------------------------------------------------------===//
43 TargetInstrInfo::TargetInstrInfo(const TargetInstrDesc* Desc,
45 : Descriptors(Desc), NumOpcodes(numOpcodes) {
48 TargetInstrInfo::~TargetInstrInfo() {
52 TargetInstrInfo::getNumMicroOps(const MachineInstr *MI,
53 const InstrItineraryData *ItinData) const {
54 if (!ItinData || ItinData->isEmpty())
57 unsigned Class = MI->getDesc().getSchedClass();
58 unsigned UOps = ItinData->Itineraries[Class].NumMicroOps;
62 // The # of u-ops is dynamically determined. The specific target should
63 // override this function to return the right number.
67 /// insertNoop - Insert a noop into the instruction stream at the specified
69 void TargetInstrInfo::insertNoop(MachineBasicBlock &MBB,
70 MachineBasicBlock::iterator MI) const {
71 llvm_unreachable("Target didn't implement insertNoop!");
75 bool TargetInstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const {
76 const TargetInstrDesc &TID = MI->getDesc();
77 if (!TID.isTerminator()) return false;
79 // Conditional branch is a special case.
80 if (TID.isBranch() && !TID.isBarrier())
82 if (!TID.isPredicable())
84 return !isPredicated(MI);
88 /// Measure the specified inline asm to determine an approximation of its
90 /// Comments (which run till the next SeparatorChar or newline) do not
91 /// count as an instruction.
92 /// Any other non-whitespace text is considered an instruction, with
93 /// multiple instructions separated by SeparatorChar or newlines.
94 /// Variable-length instructions are not handled here; this function
95 /// may be overloaded in the target code to do that.
96 unsigned TargetInstrInfo::getInlineAsmLength(const char *Str,
97 const MCAsmInfo &MAI) const {
100 // Count the number of instructions in the asm.
101 bool atInsnStart = true;
103 for (; *Str; ++Str) {
104 if (*Str == '\n' || *Str == MAI.getSeparatorChar())
106 if (atInsnStart && !isspace(*Str)) {
107 Length += MAI.getMaxInstLength();
110 if (atInsnStart && strncmp(Str, MAI.getCommentString(),
111 strlen(MAI.getCommentString())) == 0)