1 //===-- TargetInstrInfo.cpp - Target Instruction Information --------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/Target/TargetInstrInfo.h"
15 #include "llvm/Target/TargetRegisterInfo.h"
16 #include "llvm/CodeGen/SelectionDAGNodes.h"
17 #include "llvm/MC/MCAsmInfo.h"
18 #include "llvm/MC/MCInstrItineraries.h"
19 #include "llvm/Support/ErrorHandling.h"
23 //===----------------------------------------------------------------------===//
25 //===----------------------------------------------------------------------===//
27 TargetInstrInfo::TargetInstrInfo(const MCInstrDesc* Desc, unsigned numOpcodes,
28 int CFSetupOpcode, int CFDestroyOpcode)
29 : CallFrameSetupOpcode(CFSetupOpcode),
30 CallFrameDestroyOpcode(CFDestroyOpcode) {
31 InitMCInstrInfo(Desc, numOpcodes);
34 TargetInstrInfo::~TargetInstrInfo() {
37 const TargetRegisterClass*
38 TargetInstrInfo::getRegClass(const MCInstrDesc &MCID, unsigned OpNum,
39 const TargetRegisterInfo *TRI) const {
40 if (OpNum >= MCID.getNumOperands())
43 short RegClass = MCID.OpInfo[OpNum].RegClass;
44 if (MCID.OpInfo[OpNum].isLookupPtrRegClass())
45 return TRI->getPointerRegClass(RegClass);
47 // Instructions like INSERT_SUBREG do not have fixed register classes.
51 // Otherwise just look it up normally.
52 return TRI->getRegClass(RegClass);
56 TargetInstrInfo::getNumMicroOps(const InstrItineraryData *ItinData,
57 const MachineInstr *MI) const {
58 if (!ItinData || ItinData->isEmpty())
61 unsigned Class = MI->getDesc().getSchedClass();
62 unsigned UOps = ItinData->Itineraries[Class].NumMicroOps;
66 // The # of u-ops is dynamically determined. The specific target should
67 // override this function to return the right number.
72 TargetInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
73 const MachineInstr *DefMI, unsigned DefIdx,
74 const MachineInstr *UseMI, unsigned UseIdx) const {
75 if (!ItinData || ItinData->isEmpty())
78 unsigned DefClass = DefMI->getDesc().getSchedClass();
79 unsigned UseClass = UseMI->getDesc().getSchedClass();
80 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx);
84 TargetInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
85 SDNode *DefNode, unsigned DefIdx,
86 SDNode *UseNode, unsigned UseIdx) const {
87 if (!ItinData || ItinData->isEmpty())
90 if (!DefNode->isMachineOpcode())
93 unsigned DefClass = get(DefNode->getMachineOpcode()).getSchedClass();
94 if (!UseNode->isMachineOpcode())
95 return ItinData->getOperandCycle(DefClass, DefIdx);
96 unsigned UseClass = get(UseNode->getMachineOpcode()).getSchedClass();
97 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx);
100 int TargetInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
101 const MachineInstr *MI,
102 unsigned *PredCost) const {
103 if (!ItinData || ItinData->isEmpty())
106 return ItinData->getStageLatency(MI->getDesc().getSchedClass());
109 int TargetInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
111 if (!ItinData || ItinData->isEmpty())
114 if (!N->isMachineOpcode())
117 return ItinData->getStageLatency(get(N->getMachineOpcode()).getSchedClass());
120 bool TargetInstrInfo::hasLowDefLatency(const InstrItineraryData *ItinData,
121 const MachineInstr *DefMI,
122 unsigned DefIdx) const {
123 if (!ItinData || ItinData->isEmpty())
126 unsigned DefClass = DefMI->getDesc().getSchedClass();
127 int DefCycle = ItinData->getOperandCycle(DefClass, DefIdx);
128 return (DefCycle != -1 && DefCycle <= 1);
131 /// insertNoop - Insert a noop into the instruction stream at the specified
133 void TargetInstrInfo::insertNoop(MachineBasicBlock &MBB,
134 MachineBasicBlock::iterator MI) const {
135 llvm_unreachable("Target didn't implement insertNoop!");
139 bool TargetInstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const {
140 const MCInstrDesc &MCID = MI->getDesc();
141 if (!MCID.isTerminator()) return false;
143 // Conditional branch is a special case.
144 if (MCID.isBranch() && !MCID.isBarrier())
146 if (!MCID.isPredicable())
148 return !isPredicated(MI);
152 /// Measure the specified inline asm to determine an approximation of its
154 /// Comments (which run till the next SeparatorString or newline) do not
155 /// count as an instruction.
156 /// Any other non-whitespace text is considered an instruction, with
157 /// multiple instructions separated by SeparatorString or newlines.
158 /// Variable-length instructions are not handled here; this function
159 /// may be overloaded in the target code to do that.
160 unsigned TargetInstrInfo::getInlineAsmLength(const char *Str,
161 const MCAsmInfo &MAI) const {
164 // Count the number of instructions in the asm.
165 bool atInsnStart = true;
167 for (; *Str; ++Str) {
168 if (*Str == '\n' || strncmp(Str, MAI.getSeparatorString(),
169 strlen(MAI.getSeparatorString())) == 0)
171 if (atInsnStart && !std::isspace(*Str)) {
172 Length += MAI.getMaxInstLength();
175 if (atInsnStart && strncmp(Str, MAI.getCommentString(),
176 strlen(MAI.getCommentString())) == 0)