1 //===- TargetRegisterInfo.cpp - Target Register Information Implementation ===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the TargetRegisterInfo interface.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/Target/TargetMachine.h"
15 #include "llvm/Target/TargetRegisterInfo.h"
16 #include "llvm/ADT/BitVector.h"
17 #include "llvm/Support/raw_ostream.h"
21 TargetRegisterInfo::TargetRegisterInfo(const TargetRegisterInfoDesc *ID,
22 regclass_iterator RCB, regclass_iterator RCE,
23 const char *const *subregindexnames)
24 : InfoDesc(ID), SubRegIndexNames(subregindexnames),
25 RegClassBegin(RCB), RegClassEnd(RCE) {
28 TargetRegisterInfo::~TargetRegisterInfo() {}
30 void PrintReg::print(raw_ostream &OS) const {
33 else if (TargetRegisterInfo::isStackSlot(Reg))
34 OS << "SS#" << TargetRegisterInfo::stackSlot2Index(Reg);
35 else if (TargetRegisterInfo::isVirtualRegister(Reg))
36 OS << "%vreg" << TargetRegisterInfo::virtReg2Index(Reg);
37 else if (TRI && Reg < TRI->getNumRegs())
38 OS << '%' << TRI->getName(Reg);
40 OS << "%physreg" << Reg;
43 OS << ':' << TRI->getSubRegIndexName(SubIdx);
45 OS << ":sub(" << SubIdx << ')';
49 /// getMinimalPhysRegClass - Returns the Register Class of a physical
50 /// register of the given type, picking the most sub register class of
51 /// the right type that contains this physreg.
52 const TargetRegisterClass *
53 TargetRegisterInfo::getMinimalPhysRegClass(unsigned reg, EVT VT) const {
54 assert(isPhysicalRegister(reg) && "reg must be a physical register");
56 // Pick the most sub register class of the right type that contains
58 const TargetRegisterClass* BestRC = 0;
59 for (regclass_iterator I = regclass_begin(), E = regclass_end(); I != E; ++I){
60 const TargetRegisterClass* RC = *I;
61 if ((VT == MVT::Other || RC->hasType(VT)) && RC->contains(reg) &&
62 (!BestRC || BestRC->hasSubClass(RC)))
66 assert(BestRC && "Couldn't find the register class");
70 /// getAllocatableSetForRC - Toggle the bits that represent allocatable
71 /// registers for the specific register class.
72 static void getAllocatableSetForRC(const MachineFunction &MF,
73 const TargetRegisterClass *RC, BitVector &R){
74 ArrayRef<uint16_t> Order = RC->getRawAllocationOrder(MF);
75 for (unsigned i = 0; i != Order.size(); ++i)
79 BitVector TargetRegisterInfo::getAllocatableSet(const MachineFunction &MF,
80 const TargetRegisterClass *RC) const {
81 BitVector Allocatable(getNumRegs());
83 getAllocatableSetForRC(MF, RC, Allocatable);
85 for (TargetRegisterInfo::regclass_iterator I = regclass_begin(),
86 E = regclass_end(); I != E; ++I)
87 if ((*I)->isAllocatable())
88 getAllocatableSetForRC(MF, *I, Allocatable);
91 // Mask out the reserved registers
92 BitVector Reserved = getReservedRegs(MF);
93 Allocatable &= Reserved.flip();
98 const TargetRegisterClass *
99 TargetRegisterInfo::getCommonSubClass(const TargetRegisterClass *A,
100 const TargetRegisterClass *B) const {
101 // First take care of the trivial cases.
107 // Register classes are ordered topologically, so the largest common
108 // sub-class it the common sub-class with the smallest ID.
109 const unsigned *SubA = A->getSubClassMask();
110 const unsigned *SubB = B->getSubClassMask();
112 // We could start the search from max(A.ID, B.ID), but we are only going to
113 // execute 2-3 iterations anyway.
114 for (unsigned Base = 0, BaseE = getNumRegClasses(); Base < BaseE; Base += 32)
115 if (unsigned Common = *SubA++ & *SubB++)
116 return getRegClass(Base + CountTrailingZeros_32(Common));
118 // No common sub-class exists.