1 //===- TargetRegisterInfo.cpp - Target Register Information Implementation ===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the TargetRegisterInfo interface.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/Target/TargetMachine.h"
15 #include "llvm/Target/TargetRegisterInfo.h"
16 #include "llvm/ADT/BitVector.h"
17 #include "llvm/Support/raw_ostream.h"
21 TargetRegisterInfo::TargetRegisterInfo(const TargetRegisterInfoDesc *ID,
22 regclass_iterator RCB, regclass_iterator RCE,
23 const char *const *subregindexnames)
24 : InfoDesc(ID), SubRegIndexNames(subregindexnames),
25 RegClassBegin(RCB), RegClassEnd(RCE) {
28 TargetRegisterInfo::~TargetRegisterInfo() {}
30 void PrintReg::print(raw_ostream &OS) const {
33 else if (TargetRegisterInfo::isStackSlot(Reg))
34 OS << "SS#" << TargetRegisterInfo::stackSlot2Index(Reg);
35 else if (TargetRegisterInfo::isVirtualRegister(Reg))
36 OS << "%vreg" << TargetRegisterInfo::virtReg2Index(Reg);
37 else if (TRI && Reg < TRI->getNumRegs())
38 OS << '%' << TRI->getName(Reg);
40 OS << "%physreg" << Reg;
43 OS << ':' << TRI->getSubRegIndexName(SubIdx);
45 OS << ":sub(" << SubIdx << ')';
49 void PrintRegUnit::print(raw_ostream &OS) const {
50 // Generic printout when TRI is missing.
52 OS << "Unit~" << Unit;
56 // Check for invalid register units.
57 if (Unit >= TRI->getNumRegUnits()) {
58 OS << "BadUnit~" << Unit;
62 // Normal units have at least one root.
63 MCRegUnitRootIterator Roots(Unit, TRI);
64 assert(Roots.isValid() && "Unit has no roots.");
65 OS << TRI->getName(*Roots);
66 for (++Roots; Roots.isValid(); ++Roots)
67 OS << '~' << TRI->getName(*Roots);
70 /// getAllocatableClass - Return the maximal subclass of the given register
71 /// class that is alloctable, or NULL.
72 const TargetRegisterClass *
73 TargetRegisterInfo::getAllocatableClass(const TargetRegisterClass *RC) const {
74 if (!RC || RC->isAllocatable())
77 const unsigned *SubClass = RC->getSubClassMask();
78 for (unsigned Base = 0, BaseE = getNumRegClasses();
79 Base < BaseE; Base += 32) {
81 for (unsigned Mask = *SubClass++; Mask; Mask >>= 1) {
82 unsigned Offset = CountTrailingZeros_32(Mask);
83 const TargetRegisterClass *SubRC = getRegClass(Idx + Offset);
84 if (SubRC->isAllocatable())
93 /// getMinimalPhysRegClass - Returns the Register Class of a physical
94 /// register of the given type, picking the most sub register class of
95 /// the right type that contains this physreg.
96 const TargetRegisterClass *
97 TargetRegisterInfo::getMinimalPhysRegClass(unsigned reg, EVT VT) const {
98 assert(isPhysicalRegister(reg) && "reg must be a physical register");
100 // Pick the most sub register class of the right type that contains
102 const TargetRegisterClass* BestRC = 0;
103 for (regclass_iterator I = regclass_begin(), E = regclass_end(); I != E; ++I){
104 const TargetRegisterClass* RC = *I;
105 if ((VT == MVT::Other || RC->hasType(VT)) && RC->contains(reg) &&
106 (!BestRC || BestRC->hasSubClass(RC)))
110 assert(BestRC && "Couldn't find the register class");
114 /// getAllocatableSetForRC - Toggle the bits that represent allocatable
115 /// registers for the specific register class.
116 static void getAllocatableSetForRC(const MachineFunction &MF,
117 const TargetRegisterClass *RC, BitVector &R){
118 assert(RC->isAllocatable() && "invalid for nonallocatable sets");
119 ArrayRef<uint16_t> Order = RC->getRawAllocationOrder(MF);
120 for (unsigned i = 0; i != Order.size(); ++i)
124 BitVector TargetRegisterInfo::getAllocatableSet(const MachineFunction &MF,
125 const TargetRegisterClass *RC) const {
126 BitVector Allocatable(getNumRegs());
128 // A register class with no allocatable subclass returns an empty set.
129 const TargetRegisterClass *SubClass = getAllocatableClass(RC);
131 getAllocatableSetForRC(MF, SubClass, Allocatable);
133 for (TargetRegisterInfo::regclass_iterator I = regclass_begin(),
134 E = regclass_end(); I != E; ++I)
135 if ((*I)->isAllocatable())
136 getAllocatableSetForRC(MF, *I, Allocatable);
139 // Mask out the reserved registers
140 BitVector Reserved = getReservedRegs(MF);
141 Allocatable &= Reserved.flip();
147 const TargetRegisterClass *firstCommonClass(const uint32_t *A,
149 const TargetRegisterInfo *TRI) {
150 for (unsigned I = 0, E = TRI->getNumRegClasses(); I < E; I += 32)
151 if (unsigned Common = *A++ & *B++)
152 return TRI->getRegClass(I + CountTrailingZeros_32(Common));
156 const TargetRegisterClass *
157 TargetRegisterInfo::getCommonSubClass(const TargetRegisterClass *A,
158 const TargetRegisterClass *B) const {
159 // First take care of the trivial cases.
165 // Register classes are ordered topologically, so the largest common
166 // sub-class it the common sub-class with the smallest ID.
167 return firstCommonClass(A->getSubClassMask(), B->getSubClassMask(), this);
170 const TargetRegisterClass *
171 TargetRegisterInfo::getMatchingSuperRegClass(const TargetRegisterClass *A,
172 const TargetRegisterClass *B,
173 unsigned Idx) const {
174 assert(A && B && "Missing register class");
175 assert(Idx && "Bad sub-register index");
177 // Find Idx in the list of super-register indices.
178 for (SuperRegClassIterator RCI(B, this); RCI.isValid(); ++RCI)
179 if (RCI.getSubReg() == Idx)
180 // The bit mask contains all register classes that are projected into B
181 // by Idx. Find a class that is also a sub-class of A.
182 return firstCommonClass(RCI.getMask(), A->getSubClassMask(), this);
186 const TargetRegisterClass *TargetRegisterInfo::
187 getCommonSuperRegClass(const TargetRegisterClass *RCA, unsigned SubA,
188 const TargetRegisterClass *RCB, unsigned SubB,
189 unsigned &PreA, unsigned &PreB) const {
190 assert(RCA && SubA && RCB && SubB && "Invalid arguments");
192 // Search all pairs of sub-register indices that project into RCA and RCB
193 // respectively. This is quadratic, but usually the sets are very small. On
194 // most targets like X86, there will only be a single sub-register index
195 // (e.g., sub_16bit projecting into GR16).
197 // The worst case is a register class like DPR on ARM.
198 // We have indices dsub_0..dsub_7 projecting into that class.
200 // It is very common that one register class is a sub-register of the other.
201 // Arrange for RCA to be the larger register so the answer will be found in
202 // the first iteration. This makes the search linear for the most common
204 const TargetRegisterClass *BestRC = 0;
205 unsigned *BestPreA = &PreA;
206 unsigned *BestPreB = &PreB;
207 if (RCA->getSize() < RCB->getSize()) {
209 std::swap(SubA, SubB);
210 std::swap(BestPreA, BestPreB);
213 // Also terminate the search one we have found a register class as small as
215 unsigned MinSize = RCA->getSize();
217 for (SuperRegClassIterator IA(RCA, this, true); IA.isValid(); ++IA) {
218 unsigned FinalA = composeSubRegIndices(IA.getSubReg(), SubA);
219 for (SuperRegClassIterator IB(RCB, this, true); IB.isValid(); ++IB) {
220 // Check if a common super-register class exists for this index pair.
221 const TargetRegisterClass *RC =
222 firstCommonClass(IA.getMask(), IB.getMask(), this);
223 if (!RC || RC->getSize() < MinSize)
226 // The indexes must compose identically: PreA+SubA == PreB+SubB.
227 unsigned FinalB = composeSubRegIndices(IB.getSubReg(), SubB);
228 if (FinalA != FinalB)
231 // Is RC a better candidate than BestRC?
232 if (BestRC && RC->getSize() >= BestRC->getSize())
235 // Yes, RC is the smallest super-register seen so far.
237 *BestPreA = IA.getSubReg();
238 *BestPreB = IB.getSubReg();
240 // Bail early if we reached MinSize. We won't find a better candidate.
241 if (BestRC->getSize() == MinSize)