1 //===- TargetRegisterInfo.cpp - Target Register Information Implementation ===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the TargetRegisterInfo interface.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/Target/TargetMachine.h"
15 #include "llvm/Target/TargetRegisterInfo.h"
16 #include "llvm/Target/TargetFrameInfo.h"
17 #include "llvm/CodeGen/MachineFunction.h"
18 #include "llvm/CodeGen/MachineFrameInfo.h"
19 #include "llvm/ADT/BitVector.h"
23 TargetRegisterInfo::TargetRegisterInfo(const TargetRegisterDesc *D, unsigned NR,
24 regclass_iterator RCB, regclass_iterator RCE,
25 const char *const *subregindexnames,
27 const unsigned* subregs, const unsigned subregsize,
28 const unsigned* aliases, const unsigned aliasessize)
29 : SubregHash(subregs), SubregHashSize(subregsize),
30 AliasesHash(aliases), AliasesHashSize(aliasessize),
31 Desc(D), SubRegIndexNames(subregindexnames), NumRegs(NR),
32 RegClassBegin(RCB), RegClassEnd(RCE) {
33 assert(NumRegs < FirstVirtualRegister &&
34 "Target has too many physical registers!");
36 CallFrameSetupOpcode = CFSO;
37 CallFrameDestroyOpcode = CFDO;
40 TargetRegisterInfo::~TargetRegisterInfo() {}
42 /// getPhysicalRegisterRegClass - Returns the Register Class of a physical
43 /// register of the given type. If type is EVT::Other, then just return any
44 /// register class the register belongs to.
45 const TargetRegisterClass *
46 TargetRegisterInfo::getPhysicalRegisterRegClass(unsigned reg, EVT VT) const {
47 assert(isPhysicalRegister(reg) && "reg must be a physical register");
49 // Pick the most super register class of the right type that contains
51 const TargetRegisterClass* BestRC = 0;
52 for (regclass_iterator I = regclass_begin(), E = regclass_end(); I != E; ++I){
53 const TargetRegisterClass* RC = *I;
54 if ((VT == MVT::Other || RC->hasType(VT)) && RC->contains(reg) &&
55 (!BestRC || BestRC->hasSuperClass(RC)))
59 assert(BestRC && "Couldn't find the register class");
63 /// getMinimalPhysRegClass - Returns the Register Class of a physical
64 /// register of the given type.
65 const TargetRegisterClass *
66 TargetRegisterInfo::getMinimalPhysRegClass(unsigned reg) const {
67 assert(isPhysicalRegister(reg) && "reg must be a physical register");
69 // Pick the most sub register class of the right type that contains
71 const TargetRegisterClass* BestRC = 0;
72 for (regclass_iterator I = regclass_begin(), E = regclass_end(); I != E; ++I){
73 const TargetRegisterClass* RC = *I;
74 if (RC->contains(reg) && (!BestRC || BestRC->hasSubClass(RC)))
78 assert(BestRC && "Couldn't find the register class");
82 /// getAllocatableSetForRC - Toggle the bits that represent allocatable
83 /// registers for the specific register class.
84 static void getAllocatableSetForRC(const MachineFunction &MF,
85 const TargetRegisterClass *RC, BitVector &R){
86 for (TargetRegisterClass::iterator I = RC->allocation_order_begin(MF),
87 E = RC->allocation_order_end(MF); I != E; ++I)
91 BitVector TargetRegisterInfo::getAllocatableSet(const MachineFunction &MF,
92 const TargetRegisterClass *RC) const {
93 BitVector Allocatable(NumRegs);
95 getAllocatableSetForRC(MF, RC, Allocatable);
99 for (TargetRegisterInfo::regclass_iterator I = regclass_begin(),
100 E = regclass_end(); I != E; ++I)
101 getAllocatableSetForRC(MF, *I, Allocatable);
105 /// getFrameIndexOffset - Returns the displacement from the frame register to
106 /// the stack frame of the specified index. This is the default implementation
107 /// which is overridden for some targets.
108 int TargetRegisterInfo::getFrameIndexOffset(const MachineFunction &MF,
110 const TargetFrameInfo &TFI = *MF.getTarget().getFrameInfo();
111 const MachineFrameInfo *MFI = MF.getFrameInfo();
112 return MFI->getObjectOffset(FI) + MFI->getStackSize() -
113 TFI.getOffsetOfLocalArea() + MFI->getOffsetAdjustment();
116 /// getInitialFrameState - Returns a list of machine moves that are assumed
117 /// on entry to a function.
119 TargetRegisterInfo::getInitialFrameState(std::vector<MachineMove> &Moves) const{
120 // Default is to do nothing.
123 const TargetRegisterClass *
124 llvm::getCommonSubClass(const TargetRegisterClass *A,
125 const TargetRegisterClass *B) {
126 // First take care of the trivial cases
132 // If B is a subclass of A, it will be handled in the loop below
133 if (B->hasSubClass(A))
136 const TargetRegisterClass *Best = 0;
137 for (TargetRegisterClass::sc_iterator I = A->subclasses_begin();
138 const TargetRegisterClass *X = *I; ++I) {
140 return B; // B is a subclass of A
142 // X must be a common subclass of A and B
143 if (!B->hasSubClass(X))
146 // A superclass is definitely better.
147 if (!Best || Best->hasSuperClass(X)) {
152 // A subclass is definitely worse
153 if (Best->hasSubClass(X))
156 // Best and *I have no super/sub class relation - pick the larger class, or
157 // the smaller spill size.
158 int nb = std::distance(Best->begin(), Best->end());
159 int ni = std::distance(X->begin(), X->end());
160 if (ni>nb || (ni==nb && X->getSize() < Best->getSize()))