1 //===- TargetRegisterInfo.cpp - Target Register Information Implementation ===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the TargetRegisterInfo interface.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/Target/TargetMachine.h"
15 #include "llvm/Target/TargetRegisterInfo.h"
16 #include "llvm/Target/TargetFrameInfo.h"
17 #include "llvm/CodeGen/MachineFunction.h"
18 #include "llvm/CodeGen/MachineFrameInfo.h"
19 #include "llvm/ADT/BitVector.h"
23 TargetRegisterInfo::TargetRegisterInfo(const TargetRegisterDesc *D, unsigned NR,
24 regclass_iterator RCB, regclass_iterator RCE,
26 const unsigned* subregs, const unsigned subregsize)
27 : Desc(D), NumRegs(NR), RegClassBegin(RCB), RegClassEnd(RCE),
28 SubregHash(subregs), SubregHashSize(subregsize) {
29 assert(NumRegs < FirstVirtualRegister &&
30 "Target has too many physical registers!");
32 CallFrameSetupOpcode = CFSO;
33 CallFrameDestroyOpcode = CFDO;
36 TargetRegisterInfo::~TargetRegisterInfo() {}
39 // Sort according to super- / sub- class relations.
40 // i.e. super- register class < sub- register class.
42 bool operator()(const TargetRegisterClass* const &LHS,
43 const TargetRegisterClass* const &RHS) {
44 return RHS->hasSuperClass(LHS);
49 /// getPhysicalRegisterRegClass - Returns the Register Class of a physical
50 /// register of the given type. If type is MVT::Other, then just return any
51 /// register class the register belongs to.
52 const TargetRegisterClass *
53 TargetRegisterInfo::getPhysicalRegisterRegClass(unsigned reg, MVT VT) const {
54 assert(isPhysicalRegister(reg) && "reg must be a physical register");
56 // Pick the register class of the right type that contains this physreg.
57 SmallVector<const TargetRegisterClass*, 4> RCs;
58 for (regclass_iterator I = regclass_begin(), E = regclass_end(); I != E; ++I){
59 if ((VT == MVT::Other || (*I)->hasType(VT)) && (*I)->contains(reg))
67 // Multiple compatible register classes. Get the super- class.
68 std::stable_sort(RCs.begin(), RCs.end(), RCCompare());
72 assert(false && "Couldn't find the register class");
76 /// getAllocatableSetForRC - Toggle the bits that represent allocatable
77 /// registers for the specific register class.
78 static void getAllocatableSetForRC(MachineFunction &MF,
79 const TargetRegisterClass *RC, BitVector &R){
80 for (TargetRegisterClass::iterator I = RC->allocation_order_begin(MF),
81 E = RC->allocation_order_end(MF); I != E; ++I)
85 BitVector TargetRegisterInfo::getAllocatableSet(MachineFunction &MF,
86 const TargetRegisterClass *RC) const {
87 BitVector Allocatable(NumRegs);
89 getAllocatableSetForRC(MF, RC, Allocatable);
93 for (TargetRegisterInfo::regclass_iterator I = regclass_begin(),
94 E = regclass_end(); I != E; ++I)
95 getAllocatableSetForRC(MF, *I, Allocatable);
99 /// getFrameIndexOffset - Returns the displacement from the frame register to
100 /// the stack frame of the specified index. This is the default implementation
101 /// which is likely incorrect for the target.
102 int TargetRegisterInfo::getFrameIndexOffset(MachineFunction &MF, int FI) const {
103 const TargetFrameInfo &TFI = *MF.getTarget().getFrameInfo();
104 MachineFrameInfo *MFI = MF.getFrameInfo();
105 return MFI->getObjectOffset(FI) + MFI->getStackSize() -
106 TFI.getOffsetOfLocalArea() + MFI->getOffsetAdjustment();
109 /// getInitialFrameState - Returns a list of machine moves that are assumed
110 /// on entry to a function.
112 TargetRegisterInfo::getInitialFrameState(std::vector<MachineMove> &Moves) const {
113 // Default is to do nothing.