1 //===- TargetRegisterInfo.cpp - Target Register Information Implementation ===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the TargetRegisterInfo interface.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/Target/TargetMachine.h"
15 #include "llvm/Target/TargetRegisterInfo.h"
16 #include "llvm/ADT/BitVector.h"
17 #include "llvm/Support/raw_ostream.h"
21 TargetRegisterInfo::TargetRegisterInfo(const TargetRegisterInfoDesc *ID,
22 regclass_iterator RCB, regclass_iterator RCE,
23 const char *const *subregindexnames)
24 : InfoDesc(ID), SubRegIndexNames(subregindexnames),
25 RegClassBegin(RCB), RegClassEnd(RCE) {
28 TargetRegisterInfo::~TargetRegisterInfo() {}
30 void PrintReg::print(raw_ostream &OS) const {
33 else if (TargetRegisterInfo::isStackSlot(Reg))
34 OS << "SS#" << TargetRegisterInfo::stackSlot2Index(Reg);
35 else if (TargetRegisterInfo::isVirtualRegister(Reg))
36 OS << "%vreg" << TargetRegisterInfo::virtReg2Index(Reg);
37 else if (TRI && Reg < TRI->getNumRegs())
38 OS << '%' << TRI->getName(Reg);
40 OS << "%physreg" << Reg;
43 OS << ':' << TRI->getSubRegIndexName(SubIdx);
45 OS << ":sub(" << SubIdx << ')';
49 /// getAllocatableClass - Return the maximal subclass of the given register
50 /// class that is alloctable, or NULL.
51 const TargetRegisterClass *
52 TargetRegisterInfo::getAllocatableClass(const TargetRegisterClass *RC) const {
53 if (!RC || RC->isAllocatable())
56 const unsigned *SubClass = RC->getSubClassMask();
57 for (unsigned Base = 0, BaseE = getNumRegClasses();
58 Base < BaseE; Base += 32) {
60 for (unsigned Mask = *SubClass++; Mask; Mask >>= 1) {
61 unsigned Offset = CountTrailingZeros_32(Mask);
62 const TargetRegisterClass *SubRC = getRegClass(Idx + Offset);
63 if (SubRC->isAllocatable())
72 /// getMinimalPhysRegClass - Returns the Register Class of a physical
73 /// register of the given type, picking the most sub register class of
74 /// the right type that contains this physreg.
75 const TargetRegisterClass *
76 TargetRegisterInfo::getMinimalPhysRegClass(unsigned reg, EVT VT) const {
77 assert(isPhysicalRegister(reg) && "reg must be a physical register");
79 // Pick the most sub register class of the right type that contains
81 const TargetRegisterClass* BestRC = 0;
82 for (regclass_iterator I = regclass_begin(), E = regclass_end(); I != E; ++I){
83 const TargetRegisterClass* RC = *I;
84 if ((VT == MVT::Other || RC->hasType(VT)) && RC->contains(reg) &&
85 (!BestRC || BestRC->hasSubClass(RC)))
89 assert(BestRC && "Couldn't find the register class");
93 /// getAllocatableSetForRC - Toggle the bits that represent allocatable
94 /// registers for the specific register class.
95 static void getAllocatableSetForRC(const MachineFunction &MF,
96 const TargetRegisterClass *RC, BitVector &R){
97 assert(RC->isAllocatable() && "invalid for nonallocatable sets");
98 ArrayRef<uint16_t> Order = RC->getRawAllocationOrder(MF);
99 for (unsigned i = 0; i != Order.size(); ++i)
103 BitVector TargetRegisterInfo::getAllocatableSet(const MachineFunction &MF,
104 const TargetRegisterClass *RC) const {
105 BitVector Allocatable(getNumRegs());
107 // A register class with no allocatable subclass returns an empty set.
108 const TargetRegisterClass *SubClass = getAllocatableClass(RC);
110 getAllocatableSetForRC(MF, SubClass, Allocatable);
112 for (TargetRegisterInfo::regclass_iterator I = regclass_begin(),
113 E = regclass_end(); I != E; ++I)
114 if ((*I)->isAllocatable())
115 getAllocatableSetForRC(MF, *I, Allocatable);
118 // Mask out the reserved registers
119 BitVector Reserved = getReservedRegs(MF);
120 Allocatable &= Reserved.flip();
125 const TargetRegisterClass *
126 TargetRegisterInfo::getCommonSubClass(const TargetRegisterClass *A,
127 const TargetRegisterClass *B) const {
128 // First take care of the trivial cases.
134 // Register classes are ordered topologically, so the largest common
135 // sub-class it the common sub-class with the smallest ID.
136 const unsigned *SubA = A->getSubClassMask();
137 const unsigned *SubB = B->getSubClassMask();
139 // We could start the search from max(A.ID, B.ID), but we are only going to
140 // execute 2-3 iterations anyway.
141 for (unsigned Base = 0, BaseE = getNumRegClasses(); Base < BaseE; Base += 32)
142 if (unsigned Common = *SubA++ & *SubB++)
143 return getRegClass(Base + CountTrailingZeros_32(Common));
145 // No common sub-class exists.
149 const TargetRegisterClass *
150 TargetRegisterInfo::getMatchingSuperRegClass(const TargetRegisterClass *A,
151 const TargetRegisterClass *B,
152 unsigned Idx) const {
153 assert(A && B && "Missing register class");
154 assert(Idx && "Bad sub-register index");
156 // Find Idx in the list of super-register indices.
157 const uint16_t *SRI = B->getSuperRegIndices();
159 while (SRI[Offset] != Idx) {
165 // The register class bit mask corresponding to SRI[Offset]. The bit mask
166 // contains all register classes that are projected into B by Idx. Find a
167 // class that is also a sub-class of A.
168 const unsigned RCMaskWords = (getNumRegClasses()+31)/32;
169 const uint32_t *TV = B->getSubClassMask() + (Offset + 1) * RCMaskWords;
170 const uint32_t *SC = A->getSubClassMask();
172 // Find the first common register class in TV and SC.
173 for (unsigned i = 0; i != RCMaskWords ; ++i)
174 if (unsigned Common = TV[i] & SC[i])
175 return getRegClass(32*i + CountTrailingZeros_32(Common));