1 //===- TargetRegisterInfo.cpp - Target Register Information Implementation ===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the TargetRegisterInfo interface.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/Target/TargetMachine.h"
15 #include "llvm/Target/TargetRegisterInfo.h"
16 #include "llvm/Target/TargetFrameInfo.h"
17 #include "llvm/CodeGen/MachineFunction.h"
18 #include "llvm/CodeGen/MachineFrameInfo.h"
19 #include "llvm/ADT/BitVector.h"
23 TargetRegisterInfo::TargetRegisterInfo(const TargetRegisterDesc *D, unsigned NR,
24 regclass_iterator RCB, regclass_iterator RCE,
25 const char *const *subregindexnames,
27 const unsigned* subregs, const unsigned subregsize,
28 const unsigned* aliases, const unsigned aliasessize)
29 : SubregHash(subregs), SubregHashSize(subregsize),
30 AliasesHash(aliases), AliasesHashSize(aliasessize),
31 Desc(D), SubRegIndexNames(subregindexnames), NumRegs(NR),
32 RegClassBegin(RCB), RegClassEnd(RCE) {
33 assert(NumRegs < FirstVirtualRegister &&
34 "Target has too many physical registers!");
36 CallFrameSetupOpcode = CFSO;
37 CallFrameDestroyOpcode = CFDO;
40 TargetRegisterInfo::~TargetRegisterInfo() {}
42 /// getPhysicalRegisterRegClass - Returns the Register Class of a physical
43 /// register of the given type. If type is EVT::Other, then just return any
44 /// register class the register belongs to.
45 const TargetRegisterClass *
46 TargetRegisterInfo::getPhysicalRegisterRegClass(unsigned reg, EVT VT) const {
47 assert(isPhysicalRegister(reg) && "reg must be a physical register");
49 // Pick the most super register class of the right type that contains
51 const TargetRegisterClass* BestRC = 0;
52 for (regclass_iterator I = regclass_begin(), E = regclass_end(); I != E; ++I){
53 const TargetRegisterClass* RC = *I;
54 if ((VT == MVT::Other || RC->hasType(VT)) && RC->contains(reg) &&
55 (!BestRC || BestRC->hasSuperClass(RC)))
59 assert(BestRC && "Couldn't find the register class");
63 /// getMinimalPhysRegClass - Returns the Register Class of a physical
64 /// register of the given type, picking the most sub register class of
65 /// the right type that contains this physreg.
66 const TargetRegisterClass *
67 TargetRegisterInfo::getMinimalPhysRegClass(unsigned reg, EVT VT) const {
68 assert(isPhysicalRegister(reg) && "reg must be a physical register");
70 // Pick the most sub register class of the right type that contains
72 const TargetRegisterClass* BestRC = 0;
73 for (regclass_iterator I = regclass_begin(), E = regclass_end(); I != E; ++I){
74 const TargetRegisterClass* RC = *I;
75 if ((VT == MVT::Other || RC->hasType(VT)) && RC->contains(reg) &&
76 (!BestRC || BestRC->hasSubClass(RC)))
80 assert(BestRC && "Couldn't find the register class");
84 /// getAllocatableSetForRC - Toggle the bits that represent allocatable
85 /// registers for the specific register class.
86 static void getAllocatableSetForRC(const MachineFunction &MF,
87 const TargetRegisterClass *RC, BitVector &R){
88 for (TargetRegisterClass::iterator I = RC->allocation_order_begin(MF),
89 E = RC->allocation_order_end(MF); I != E; ++I)
93 BitVector TargetRegisterInfo::getAllocatableSet(const MachineFunction &MF,
94 const TargetRegisterClass *RC) const {
95 BitVector Allocatable(NumRegs);
97 getAllocatableSetForRC(MF, RC, Allocatable);
101 for (TargetRegisterInfo::regclass_iterator I = regclass_begin(),
102 E = regclass_end(); I != E; ++I)
103 getAllocatableSetForRC(MF, *I, Allocatable);
107 /// getFrameIndexOffset - Returns the displacement from the frame register to
108 /// the stack frame of the specified index. This is the default implementation
109 /// which is overridden for some targets.
110 int TargetRegisterInfo::getFrameIndexOffset(const MachineFunction &MF,
112 const TargetFrameInfo &TFI = *MF.getTarget().getFrameInfo();
113 const MachineFrameInfo *MFI = MF.getFrameInfo();
114 return MFI->getObjectOffset(FI) + MFI->getStackSize() -
115 TFI.getOffsetOfLocalArea() + MFI->getOffsetAdjustment();
118 /// getInitialFrameState - Returns a list of machine moves that are assumed
119 /// on entry to a function.
121 TargetRegisterInfo::getInitialFrameState(std::vector<MachineMove> &Moves) const{
122 // Default is to do nothing.
125 const TargetRegisterClass *
126 llvm::getCommonSubClass(const TargetRegisterClass *A,
127 const TargetRegisterClass *B) {
128 // First take care of the trivial cases
134 // If B is a subclass of A, it will be handled in the loop below
135 if (B->hasSubClass(A))
138 const TargetRegisterClass *Best = 0;
139 for (TargetRegisterClass::sc_iterator I = A->subclasses_begin();
140 const TargetRegisterClass *X = *I; ++I) {
142 return B; // B is a subclass of A
144 // X must be a common subclass of A and B
145 if (!B->hasSubClass(X))
148 // A superclass is definitely better.
149 if (!Best || Best->hasSuperClass(X)) {
154 // A subclass is definitely worse
155 if (Best->hasSubClass(X))
158 // Best and *I have no super/sub class relation - pick the larger class, or
159 // the smaller spill size.
160 int nb = std::distance(Best->begin(), Best->end());
161 int ni = std::distance(X->begin(), X->end());
162 if (ni>nb || (ni==nb && X->getSize() < Best->getSize()))