1 //===- TargetRegisterInfo.cpp - Target Register Information Implementation ===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the TargetRegisterInfo interface.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/Target/TargetMachine.h"
15 #include "llvm/Target/TargetRegisterInfo.h"
16 #include "llvm/Target/TargetFrameInfo.h"
17 #include "llvm/CodeGen/MachineFunction.h"
18 #include "llvm/CodeGen/MachineFrameInfo.h"
19 #include "llvm/ADT/BitVector.h"
23 TargetRegisterInfo::TargetRegisterInfo(const TargetRegisterDesc *D, unsigned NR,
24 regclass_iterator RCB, regclass_iterator RCE,
26 : Desc(D), NumRegs(NR), RegClassBegin(RCB), RegClassEnd(RCE) {
27 assert(NumRegs < FirstVirtualRegister &&
28 "Target has too many physical registers!");
30 CallFrameSetupOpcode = CFSO;
31 CallFrameDestroyOpcode = CFDO;
34 TargetRegisterInfo::~TargetRegisterInfo() {}
37 // Sort according to super- / sub- class relations.
38 // i.e. super- register class < sub- register class.
40 bool operator()(const TargetRegisterClass* const &LHS,
41 const TargetRegisterClass* const &RHS) {
42 return RHS->hasSuperClass(LHS);
47 /// getPhysicalRegisterRegClass - Returns the Register Class of a physical
48 /// register of the given type. If type is MVT::Other, then just return any
49 /// register class the register belongs to.
50 const TargetRegisterClass *
51 TargetRegisterInfo::getPhysicalRegisterRegClass(unsigned reg,
52 MVT::ValueType VT) const {
53 assert(isPhysicalRegister(reg) && "reg must be a physical register");
55 // Pick the register class of the right type that contains this physreg.
56 SmallVector<const TargetRegisterClass*, 4> RCs;
57 for (regclass_iterator I = regclass_begin(), E = regclass_end(); I != E; ++I){
58 if ((VT == MVT::Other || (*I)->hasType(VT)) && (*I)->contains(reg))
66 // Multiple compatible register classes. Get the super- class.
67 std::stable_sort(RCs.begin(), RCs.end(), RCCompare());
71 assert(false && "Couldn't find the register class");
75 /// getAllocatableSetForRC - Toggle the bits that represent allocatable
76 /// registers for the specific register class.
77 static void getAllocatableSetForRC(MachineFunction &MF,
78 const TargetRegisterClass *RC, BitVector &R){
79 for (TargetRegisterClass::iterator I = RC->allocation_order_begin(MF),
80 E = RC->allocation_order_end(MF); I != E; ++I)
84 BitVector TargetRegisterInfo::getAllocatableSet(MachineFunction &MF,
85 const TargetRegisterClass *RC) const {
86 BitVector Allocatable(NumRegs);
88 getAllocatableSetForRC(MF, RC, Allocatable);
92 for (TargetRegisterInfo::regclass_iterator I = regclass_begin(),
93 E = regclass_end(); I != E; ++I)
94 getAllocatableSetForRC(MF, *I, Allocatable);
98 /// getFrameIndexOffset - Returns the displacement from the frame register to
99 /// the stack frame of the specified index. This is the default implementation
100 /// which is likely incorrect for the target.
101 int TargetRegisterInfo::getFrameIndexOffset(MachineFunction &MF, int FI) const {
102 const TargetFrameInfo &TFI = *MF.getTarget().getFrameInfo();
103 MachineFrameInfo *MFI = MF.getFrameInfo();
104 return MFI->getObjectOffset(FI) + MFI->getStackSize() -
105 TFI.getOffsetOfLocalArea() + MFI->getOffsetAdjustment();
108 /// getInitialFrameState - Returns a list of machine moves that are assumed
109 /// on entry to a function.
111 TargetRegisterInfo::getInitialFrameState(std::vector<MachineMove> &Moves) const {
112 // Default is to do nothing.