1 //===- TargetRegisterInfo.cpp - Target Register Information Implementation ===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the TargetRegisterInfo interface.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/Target/TargetMachine.h"
15 #include "llvm/Target/TargetRegisterInfo.h"
16 #include "llvm/CodeGen/MachineFunction.h"
17 #include "llvm/CodeGen/MachineFrameInfo.h"
18 #include "llvm/ADT/BitVector.h"
19 #include "llvm/Support/raw_ostream.h"
23 TargetRegisterInfo::TargetRegisterInfo(const TargetRegisterInfoDesc *ID,
24 regclass_iterator RCB, regclass_iterator RCE,
25 const char *const *subregindexnames,
27 : InfoDesc(ID), SubRegIndexNames(subregindexnames),
28 RegClassBegin(RCB), RegClassEnd(RCE) {
29 CallFrameSetupOpcode = CFSO;
30 CallFrameDestroyOpcode = CFDO;
33 TargetRegisterInfo::~TargetRegisterInfo() {}
35 void PrintReg::print(raw_ostream &OS) const {
38 else if (TargetRegisterInfo::isStackSlot(Reg))
39 OS << "SS#" << TargetRegisterInfo::stackSlot2Index(Reg);
40 else if (TargetRegisterInfo::isVirtualRegister(Reg))
41 OS << "%vreg" << TargetRegisterInfo::virtReg2Index(Reg);
42 else if (TRI && Reg < TRI->getNumRegs())
43 OS << '%' << TRI->getName(Reg);
45 OS << "%physreg" << Reg;
48 OS << ':' << TRI->getSubRegIndexName(SubIdx);
50 OS << ":sub(" << SubIdx << ')';
54 /// getMinimalPhysRegClass - Returns the Register Class of a physical
55 /// register of the given type, picking the most sub register class of
56 /// the right type that contains this physreg.
57 const TargetRegisterClass *
58 TargetRegisterInfo::getMinimalPhysRegClass(unsigned reg, EVT VT) const {
59 assert(isPhysicalRegister(reg) && "reg must be a physical register");
61 // Pick the most sub register class of the right type that contains
63 const TargetRegisterClass* BestRC = 0;
64 for (regclass_iterator I = regclass_begin(), E = regclass_end(); I != E; ++I){
65 const TargetRegisterClass* RC = *I;
66 if ((VT == MVT::Other || RC->hasType(VT)) && RC->contains(reg) &&
67 (!BestRC || BestRC->hasSubClass(RC)))
71 assert(BestRC && "Couldn't find the register class");
75 /// getAllocatableSetForRC - Toggle the bits that represent allocatable
76 /// registers for the specific register class.
77 static void getAllocatableSetForRC(const MachineFunction &MF,
78 const TargetRegisterClass *RC, BitVector &R){
79 ArrayRef<unsigned> Order = RC->getRawAllocationOrder(MF);
80 for (unsigned i = 0; i != Order.size(); ++i)
84 BitVector TargetRegisterInfo::getAllocatableSet(const MachineFunction &MF,
85 const TargetRegisterClass *RC) const {
86 BitVector Allocatable(getNumRegs());
88 getAllocatableSetForRC(MF, RC, Allocatable);
90 for (TargetRegisterInfo::regclass_iterator I = regclass_begin(),
91 E = regclass_end(); I != E; ++I)
92 if ((*I)->isAllocatable())
93 getAllocatableSetForRC(MF, *I, Allocatable);
96 // Mask out the reserved registers
97 BitVector Reserved = getReservedRegs(MF);
98 Allocatable &= Reserved.flip();
103 const TargetRegisterClass *
104 llvm::getCommonSubClass(const TargetRegisterClass *A,
105 const TargetRegisterClass *B) {
106 // First take care of the trivial cases
112 // If B is a subclass of A, it will be handled in the loop below
113 if (B->hasSubClass(A))
116 const TargetRegisterClass *Best = 0;
117 for (TargetRegisterClass::sc_iterator I = A->subclasses_begin();
118 const TargetRegisterClass *X = *I; ++I) {
120 return B; // B is a subclass of A
122 // X must be a common subclass of A and B
123 if (!B->hasSubClass(X))
126 // A superclass is definitely better.
127 if (!Best || Best->hasSuperClass(X)) {
132 // A subclass is definitely worse
133 if (Best->hasSubClass(X))
136 // Best and *I have no super/sub class relation - pick the larger class, or
137 // the smaller spill size.
138 int nb = std::distance(Best->begin(), Best->end());
139 int ni = std::distance(X->begin(), X->end());
140 if (ni>nb || (ni==nb && X->getSize() < Best->getSize()))