1 //===- TargetRegisterInfo.cpp - Target Register Information Implementation ===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the TargetRegisterInfo interface.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/Target/TargetMachine.h"
15 #include "llvm/Target/TargetRegisterInfo.h"
16 #include "llvm/Target/TargetFrameInfo.h"
17 #include "llvm/CodeGen/MachineFunction.h"
18 #include "llvm/CodeGen/MachineFrameInfo.h"
19 #include "llvm/ADT/BitVector.h"
23 TargetRegisterInfo::TargetRegisterInfo(const TargetRegisterDesc *D, unsigned NR,
24 regclass_iterator RCB, regclass_iterator RCE,
26 const unsigned* subregs, const unsigned subregsize)
27 : SubregHash(subregs), SubregHashSize(subregsize), Desc(D), NumRegs(NR),
28 RegClassBegin(RCB), RegClassEnd(RCE) {
29 assert(NumRegs < FirstVirtualRegister &&
30 "Target has too many physical registers!");
32 CallFrameSetupOpcode = CFSO;
33 CallFrameDestroyOpcode = CFDO;
36 TargetRegisterInfo::~TargetRegisterInfo() {}
38 /// getPhysicalRegisterRegClass - Returns the Register Class of a physical
39 /// register of the given type. If type is MVT::Other, then just return any
40 /// register class the register belongs to.
41 const TargetRegisterClass *
42 TargetRegisterInfo::getPhysicalRegisterRegClass(unsigned reg, MVT VT) const {
43 assert(isPhysicalRegister(reg) && "reg must be a physical register");
45 // Pick the most super register class of the right type that contains
47 const TargetRegisterClass* BestRC = 0;
48 for (regclass_iterator I = regclass_begin(), E = regclass_end(); I != E; ++I){
49 const TargetRegisterClass* RC = *I;
50 if ((VT == MVT::Other || RC->hasType(VT)) && RC->contains(reg) &&
51 (!BestRC || BestRC->hasSuperClass(RC)))
55 assert(BestRC && "Couldn't find the register class");
59 /// getAllocatableSetForRC - Toggle the bits that represent allocatable
60 /// registers for the specific register class.
61 static void getAllocatableSetForRC(MachineFunction &MF,
62 const TargetRegisterClass *RC, BitVector &R){
63 for (TargetRegisterClass::iterator I = RC->allocation_order_begin(MF),
64 E = RC->allocation_order_end(MF); I != E; ++I)
68 BitVector TargetRegisterInfo::getAllocatableSet(MachineFunction &MF,
69 const TargetRegisterClass *RC) const {
70 BitVector Allocatable(NumRegs);
72 getAllocatableSetForRC(MF, RC, Allocatable);
76 for (TargetRegisterInfo::regclass_iterator I = regclass_begin(),
77 E = regclass_end(); I != E; ++I)
78 getAllocatableSetForRC(MF, *I, Allocatable);
82 /// getFrameIndexOffset - Returns the displacement from the frame register to
83 /// the stack frame of the specified index. This is the default implementation
84 /// which is likely incorrect for the target.
85 int TargetRegisterInfo::getFrameIndexOffset(MachineFunction &MF, int FI) const {
86 const TargetFrameInfo &TFI = *MF.getTarget().getFrameInfo();
87 MachineFrameInfo *MFI = MF.getFrameInfo();
88 return MFI->getObjectOffset(FI) + MFI->getStackSize() -
89 TFI.getOffsetOfLocalArea() + MFI->getOffsetAdjustment();
92 /// getInitialFrameState - Returns a list of machine moves that are assumed
93 /// on entry to a function.
95 TargetRegisterInfo::getInitialFrameState(std::vector<MachineMove> &Moves) const {
96 // Default is to do nothing.