1 //===- TargetRegisterInfo.cpp - Target Register Information Implementation ===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the TargetRegisterInfo interface.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/Target/TargetMachine.h"
15 #include "llvm/Target/TargetRegisterInfo.h"
16 #include "llvm/Target/TargetFrameInfo.h"
17 #include "llvm/CodeGen/MachineFunction.h"
18 #include "llvm/CodeGen/MachineFrameInfo.h"
19 #include "llvm/ADT/BitVector.h"
23 TargetRegisterInfo::TargetRegisterInfo(const TargetRegisterDesc *D, unsigned NR,
24 regclass_iterator RCB, regclass_iterator RCE,
26 const unsigned* subregs, const unsigned subregsize,
27 const unsigned* superregs, const unsigned superregsize)
28 : SubregHash(subregs), SubregHashSize(subregsize),
29 SuperregHash(superregs), SuperregHashSize(superregsize),
30 Desc(D), NumRegs(NR), RegClassBegin(RCB), RegClassEnd(RCE) {
31 assert(NumRegs < FirstVirtualRegister &&
32 "Target has too many physical registers!");
34 CallFrameSetupOpcode = CFSO;
35 CallFrameDestroyOpcode = CFDO;
38 TargetRegisterInfo::~TargetRegisterInfo() {}
40 /// getPhysicalRegisterRegClass - Returns the Register Class of a physical
41 /// register of the given type. If type is MVT::Other, then just return any
42 /// register class the register belongs to.
43 const TargetRegisterClass *
44 TargetRegisterInfo::getPhysicalRegisterRegClass(unsigned reg, MVT VT) const {
45 assert(isPhysicalRegister(reg) && "reg must be a physical register");
47 // Pick the most super register class of the right type that contains
49 const TargetRegisterClass* BestRC = 0;
50 for (regclass_iterator I = regclass_begin(), E = regclass_end(); I != E; ++I){
51 const TargetRegisterClass* RC = *I;
52 if ((VT == MVT::Other || RC->hasType(VT)) && RC->contains(reg) &&
53 (!BestRC || BestRC->hasSuperClass(RC)))
57 assert(BestRC && "Couldn't find the register class");
61 /// getAllocatableSetForRC - Toggle the bits that represent allocatable
62 /// registers for the specific register class.
63 static void getAllocatableSetForRC(MachineFunction &MF,
64 const TargetRegisterClass *RC, BitVector &R){
65 for (TargetRegisterClass::iterator I = RC->allocation_order_begin(MF),
66 E = RC->allocation_order_end(MF); I != E; ++I)
70 BitVector TargetRegisterInfo::getAllocatableSet(MachineFunction &MF,
71 const TargetRegisterClass *RC) const {
72 BitVector Allocatable(NumRegs);
74 getAllocatableSetForRC(MF, RC, Allocatable);
78 for (TargetRegisterInfo::regclass_iterator I = regclass_begin(),
79 E = regclass_end(); I != E; ++I)
80 getAllocatableSetForRC(MF, *I, Allocatable);
84 /// getFrameIndexOffset - Returns the displacement from the frame register to
85 /// the stack frame of the specified index. This is the default implementation
86 /// which is likely incorrect for the target.
87 int TargetRegisterInfo::getFrameIndexOffset(MachineFunction &MF, int FI) const {
88 const TargetFrameInfo &TFI = *MF.getTarget().getFrameInfo();
89 MachineFrameInfo *MFI = MF.getFrameInfo();
90 return MFI->getObjectOffset(FI) + MFI->getStackSize() -
91 TFI.getOffsetOfLocalArea() + MFI->getOffsetAdjustment();
94 /// getInitialFrameState - Returns a list of machine moves that are assumed
95 /// on entry to a function.
97 TargetRegisterInfo::getInitialFrameState(std::vector<MachineMove> &Moves) const {
98 // Default is to do nothing.