1 //===-- SchedInfo.cpp - Generic code to support target schedulers ----------==//
3 // This file implements the generic part of a Scheduler description for a
4 // target. This functionality is defined in the llvm/Target/SchedInfo.h file.
6 //===----------------------------------------------------------------------===//
8 #include "llvm/Target/MachineSchedInfo.h"
10 // External object describing the machine instructions
11 // Initialized only when the TargetMachine class is created
12 // and reset when that class is destroyed.
14 const MachineInstrDescriptor* TargetInstrDescriptors = 0;
16 resourceId_t MachineResource::nextId = 0;
18 // Check if fromRVec and toRVec have *any* common entries.
19 // Assume the vectors are sorted in increasing order.
20 // Algorithm copied from function set_intersection() for sorted ranges
24 RUConflict(const vector<resourceId_t>& fromRVec,
25 const vector<resourceId_t>& toRVec)
28 unsigned fN = fromRVec.size(), tN = toRVec.size();
29 unsigned fi = 0, ti = 0;
31 while (fi < fN && ti < tN)
33 if (fromRVec[fi] < toRVec[ti])
35 else if (toRVec[ti] < fromRVec[fi])
45 ComputeMinGap(const InstrRUsage &fromRU,
46 const InstrRUsage &toRU)
50 if (fromRU.numBubbles > 0)
51 minGap = fromRU.numBubbles;
53 if (minGap < fromRU.numCycles)
55 // only need to check from cycle `minGap' onwards
56 for (cycles_t gap=minGap; gap <= fromRU.numCycles-1; gap++)
58 // check if instr. #2 can start executing `gap' cycles after #1
59 // by checking for resource conflicts in each overlapping cycle
60 cycles_t numOverlap = min(fromRU.numCycles - gap, toRU.numCycles);
61 for (cycles_t c = 0; c <= numOverlap-1; c++)
62 if (RUConflict(fromRU.resourcesByCycle[gap + c],
63 toRU.resourcesByCycle[c]))
65 // conflict found so minGap must be more than `gap'
76 //---------------------------------------------------------------------------
77 // class MachineSchedInfo
78 // Interface to machine description for instruction scheduling
79 //---------------------------------------------------------------------------
81 MachineSchedInfo::MachineSchedInfo(const TargetMachine& tgt,
83 const InstrClassRUsage* ClassRUsages,
84 const InstrRUsageDelta* UsageDeltas,
85 const InstrIssueDelta* IssueDeltas,
86 unsigned int NumUsageDeltas,
87 unsigned int NumIssueDeltas)
89 numSchedClasses(NumSchedClasses), mii(& tgt.getInstrInfo()),
90 classRUsages(ClassRUsages), usageDeltas(UsageDeltas),
91 issueDeltas(IssueDeltas), numUsageDeltas(NumUsageDeltas),
92 numIssueDeltas(NumIssueDeltas)
96 MachineSchedInfo::initializeResources()
98 assert(MAX_NUM_SLOTS >= (int)getMaxNumIssueTotal()
99 && "Insufficient slots for static data! Increase MAX_NUM_SLOTS");
101 // First, compute common resource usage info for each class because
102 // most instructions will probably behave the same as their class.
103 // Cannot allocate a vector of InstrRUsage so new each one.
105 vector<InstrRUsage> instrRUForClasses;
106 instrRUForClasses.resize(numSchedClasses);
107 for (InstrSchedClass sc = 0; sc < numSchedClasses; sc++) {
108 // instrRUForClasses.push_back(new InstrRUsage);
109 instrRUForClasses[sc].setMaxSlots(getMaxNumIssueTotal());
110 instrRUForClasses[sc] = classRUsages[sc];
113 computeInstrResources(instrRUForClasses);
114 computeIssueGaps(instrRUForClasses);
119 MachineSchedInfo::computeInstrResources(const vector<InstrRUsage>&
122 int numOpCodes = mii->getNumRealOpCodes();
123 instrRUsages.resize(numOpCodes);
125 // First get the resource usage information from the class resource usages.
126 for (MachineOpCode op = 0; op < numOpCodes; ++op) {
127 InstrSchedClass sc = getSchedClass(op);
128 assert(sc >= 0 && sc < numSchedClasses);
129 instrRUsages[op] = instrRUForClasses[sc];
132 // Now, modify the resource usages as specified in the deltas.
133 for (unsigned i = 0; i < numUsageDeltas; ++i) {
134 MachineOpCode op = usageDeltas[i].opCode;
135 assert(op < numOpCodes);
136 instrRUsages[op].addUsageDelta(usageDeltas[i]);
139 // Then modify the issue restrictions as specified in the deltas.
140 for (unsigned i = 0; i < numIssueDeltas; ++i) {
141 MachineOpCode op = issueDeltas[i].opCode;
142 assert(op < numOpCodes);
143 instrRUsages[issueDeltas[i].opCode].addIssueDelta(issueDeltas[i]);
149 MachineSchedInfo::computeIssueGaps(const vector<InstrRUsage>&
152 int numOpCodes = mii->getNumRealOpCodes();
153 instrRUsages.resize(numOpCodes);
155 assert(numOpCodes < (1 << MAX_OPCODE_SIZE) - 1
156 && "numOpCodes invalid for implementation of class OpCodePair!");
158 // First, compute issue gaps between pairs of classes based on common
159 // resources usages for each class, because most instruction pairs will
160 // usually behave the same as their class.
162 int classPairGaps[numSchedClasses][numSchedClasses];
163 for (InstrSchedClass fromSC=0; fromSC < numSchedClasses; fromSC++)
164 for (InstrSchedClass toSC=0; toSC < numSchedClasses; toSC++)
166 int classPairGap = ComputeMinGap(instrRUForClasses[fromSC],
167 instrRUForClasses[toSC]);
168 classPairGaps[fromSC][toSC] = classPairGap;
171 // Now, for each pair of instructions, use the class pair gap if both
172 // instructions have identical resource usage as their respective classes.
173 // If not, recompute the gap for the pair from scratch.
175 longestIssueConflict = 0;
177 for (MachineOpCode fromOp=0; fromOp < numOpCodes; fromOp++)
178 for (MachineOpCode toOp=0; toOp < numOpCodes; toOp++)
181 (instrRUsages[fromOp].sameAsClass && instrRUsages[toOp].sameAsClass)
182 ? classPairGaps[getSchedClass(fromOp)][getSchedClass(toOp)]
183 : ComputeMinGap(instrRUsages[fromOp], instrRUsages[toOp]);
185 if (instrPairGap > 0)
187 issueGaps[OpCodePair(fromOp,toOp)] = instrPairGap;
188 conflictLists[fromOp].push_back(toOp);
189 longestIssueConflict = max(longestIssueConflict, instrPairGap);