1 //===- TargetSchedule.td - Target Independent Scheduling ---*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by James M. Laskey and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the target-independent scheduling interfaces which should
11 // be implemented by each target which is using TableGen based scheduling.
13 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
16 // Processor chip sets - These values represent each of the chip sets supported
17 // by the scheduler. Each Processor definition requires corresponding
18 // instruction itineraries.
22 //===----------------------------------------------------------------------===//
23 // Processor functional unit - These values represent the function units
24 // available across all chip sets for the target. Eg., IntUnit, FPUnit, ...
25 // These may be independent values for each chip set or may be shared across
26 // all chip sets of the target. Each functional unit is treated as a resource
27 // during scheduling and has an affect instruction order based on availability
28 // during a time interval.
32 //===----------------------------------------------------------------------===//
33 // Instruction stage - These values represent a step in the execution of an
34 // instruction. The latency represents the number of discrete time slots used
35 // need to complete the stage. Units represent the choice of functional units
36 // that can be used to complete the stage. Eg. IntUnit1, IntUnit2.
38 class InstrStage<int latency, list<FuncUnit> units> {
39 int Latency = latency; // length of stage in machine cycles
40 list<FuncUnit> Units = units; // choice of functional units
43 //===----------------------------------------------------------------------===//
44 // Instruction itinerary - An itinerary represents a sequential series of steps
45 // required to complete an instruction. Itineraries are represented as lists of
46 // instruction stages.
49 //===----------------------------------------------------------------------===//
50 // Instruction itinerary classes - These values represent 'named' instruction
51 // itinerary. Using named itineraries simplifies managing groups of
52 // instructions across chip sets. An instruction uses the same itinerary class
53 // across all chip sets. Thus a new chip set can be added without modifying
54 // instruction information.
58 //===----------------------------------------------------------------------===//
59 // Instruction itinerary data - These values provide a runtime map of an
60 // instruction itinerary class (name) to it's itinerary data.
62 class InstrItinData<InstrItinClass Class, list<InstrStage> stages> {
63 InstrItinClass TheClass = Class;
64 list<InstrStage> Stages = stages;
67 //===----------------------------------------------------------------------===//
68 // Processor itineraries - These values represent the set of all itinerary
69 // classes for a given chip set.
71 class ProcessorItineraries<Processor proc, list<InstrItinData> iid> {
72 Processor Proc = proc;
73 list<InstrItinData> IID = iid;