1 //===- TargetSelectionDAG.td - Common code for DAG isels ---*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the target-independent interfaces used by SelectionDAG
11 // instruction selection generators.
13 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
16 // Selection DAG Type Constraint definitions.
18 // Note that the semantics of these constraints are hard coded into tblgen. To
19 // modify or add constraints, you have to hack tblgen.
22 class SDTypeConstraint<int opnum> {
23 int OperandNum = opnum;
26 // SDTCisVT - The specified operand has exactly this VT.
27 class SDTCisVT<int OpNum, ValueType vt> : SDTypeConstraint<OpNum> {
31 class SDTCisPtrTy<int OpNum> : SDTypeConstraint<OpNum>;
33 // SDTCisInt - The specified operand is has integer type.
34 class SDTCisInt<int OpNum> : SDTypeConstraint<OpNum>;
36 // SDTCisFP - The specified operand is has floating point type.
37 class SDTCisFP<int OpNum> : SDTypeConstraint<OpNum>;
39 // SDTCisSameAs - The two specified operands have identical types.
40 class SDTCisSameAs<int OpNum, int OtherOp> : SDTypeConstraint<OpNum> {
41 int OtherOperandNum = OtherOp;
44 // SDTCisVTSmallerThanOp - The specified operand is a VT SDNode, and its type is
45 // smaller than the 'Other' operand.
46 class SDTCisVTSmallerThanOp<int OpNum, int OtherOp> : SDTypeConstraint<OpNum> {
47 int OtherOperandNum = OtherOp;
50 class SDTCisOpSmallerThanOp<int SmallOp, int BigOp> : SDTypeConstraint<SmallOp>{
51 int BigOperandNum = BigOp;
54 /// SDTCisIntVectorOfSameSize - This indicates that ThisOp and OtherOp are
55 /// vector types, and that ThisOp is the result of
56 /// MVT::getIntVectorWithNumElements with the number of elements that ThisOp
58 class SDTCisIntVectorOfSameSize<int ThisOp, int OtherOp>
59 : SDTypeConstraint<ThisOp> {
60 int OtherOpNum = OtherOp;
63 //===----------------------------------------------------------------------===//
64 // Selection DAG Type Profile definitions.
66 // These use the constraints defined above to describe the type requirements of
67 // the various nodes. These are not hard coded into tblgen, allowing targets to
68 // add their own if needed.
71 // SDTypeProfile - This profile describes the type requirements of a Selection
73 class SDTypeProfile<int numresults, int numoperands,
74 list<SDTypeConstraint> constraints> {
75 int NumResults = numresults;
76 int NumOperands = numoperands;
77 list<SDTypeConstraint> Constraints = constraints;
81 def SDTIntLeaf: SDTypeProfile<1, 0, [SDTCisInt<0>]>; // for 'imm'.
82 def SDTFPLeaf : SDTypeProfile<1, 0, [SDTCisFP<0>]>; // for 'fpimm'.
83 def SDTPtrLeaf: SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>; // for '&g'.
84 def SDTOther : SDTypeProfile<1, 0, [SDTCisVT<0, OtherVT>]>; // for 'vt'.
85 def SDTUNDEF : SDTypeProfile<1, 0, []>; // for 'undef'.
86 def SDTUnaryOp : SDTypeProfile<1, 1, []>; // bitconvert
88 def SDTIntBinOp : SDTypeProfile<1, 2, [ // add, and, or, xor, udiv, etc.
89 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<0>
91 def SDTIntShiftOp : SDTypeProfile<1, 2, [ // shl, sra, srl
92 SDTCisSameAs<0, 1>, SDTCisInt<0>, SDTCisInt<2>
94 def SDTFPBinOp : SDTypeProfile<1, 2, [ // fadd, fmul, etc.
95 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisFP<0>
97 def SDTFPSignOp : SDTypeProfile<1, 2, [ // fcopysign.
98 SDTCisSameAs<0, 1>, SDTCisFP<0>, SDTCisFP<2>
100 def SDTFPTernaryOp : SDTypeProfile<1, 3, [ // fmadd, fnmsub, etc.
101 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>, SDTCisFP<0>
103 def SDTIntUnaryOp : SDTypeProfile<1, 1, [ // ctlz
104 SDTCisSameAs<0, 1>, SDTCisInt<0>
106 def SDTIntExtendOp : SDTypeProfile<1, 1, [ // sext, zext, anyext
107 SDTCisInt<0>, SDTCisInt<1>, SDTCisOpSmallerThanOp<1, 0>
109 def SDTIntTruncOp : SDTypeProfile<1, 1, [ // trunc
110 SDTCisInt<0>, SDTCisInt<1>, SDTCisOpSmallerThanOp<0, 1>
112 def SDTFPUnaryOp : SDTypeProfile<1, 1, [ // fneg, fsqrt, etc
113 SDTCisSameAs<0, 1>, SDTCisFP<0>
115 def SDTFPRoundOp : SDTypeProfile<1, 1, [ // fround
116 SDTCisFP<0>, SDTCisFP<1>, SDTCisOpSmallerThanOp<0, 1>
118 def SDTFPExtendOp : SDTypeProfile<1, 1, [ // fextend
119 SDTCisFP<0>, SDTCisFP<1>, SDTCisOpSmallerThanOp<1, 0>
121 def SDTIntToFPOp : SDTypeProfile<1, 1, [ // [su]int_to_fp
122 SDTCisFP<0>, SDTCisInt<1>
124 def SDTFPToIntOp : SDTypeProfile<1, 1, [ // fp_to_[su]int
125 SDTCisInt<0>, SDTCisFP<1>
127 def SDTExtInreg : SDTypeProfile<1, 2, [ // sext_inreg
128 SDTCisSameAs<0, 1>, SDTCisInt<0>, SDTCisVT<2, OtherVT>,
129 SDTCisVTSmallerThanOp<2, 1>
132 def SDTSetCC : SDTypeProfile<1, 3, [ // setcc
133 SDTCisInt<0>, SDTCisSameAs<1, 2>, SDTCisVT<3, OtherVT>
136 def SDTSelect : SDTypeProfile<1, 3, [ // select
137 SDTCisInt<1>, SDTCisSameAs<0, 2>, SDTCisSameAs<2, 3>
140 def SDTSelectCC : SDTypeProfile<1, 5, [ // select_cc
141 SDTCisSameAs<1, 2>, SDTCisSameAs<3, 4>, SDTCisSameAs<0, 3>,
145 def SDTBr : SDTypeProfile<0, 1, [ // br
149 def SDTBrcond : SDTypeProfile<0, 2, [ // brcond
150 SDTCisInt<0>, SDTCisVT<1, OtherVT>
153 def SDTBrind : SDTypeProfile<0, 1, [ // brind
157 def SDTRet : SDTypeProfile<0, 0, []>; // ret
159 def SDTLoad : SDTypeProfile<1, 1, [ // load
163 def SDTStore : SDTypeProfile<0, 2, [ // store
167 def SDTIStore : SDTypeProfile<1, 3, [ // indexed store
168 SDTCisSameAs<0, 2>, SDTCisPtrTy<0>, SDTCisPtrTy<3>
171 def SDTVecShuffle : SDTypeProfile<1, 3, [
172 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisIntVectorOfSameSize<3, 0>
175 class SDCallSeqStart<list<SDTypeConstraint> constraints> :
176 SDTypeProfile<0, 1, constraints>;
177 class SDCallSeqEnd<list<SDTypeConstraint> constraints> :
178 SDTypeProfile<0, 2, constraints>;
180 //===----------------------------------------------------------------------===//
181 // Selection DAG Node Properties.
183 // Note: These are hard coded into tblgen.
185 class SDNodeProperty;
186 def SDNPCommutative : SDNodeProperty; // X op Y == Y op X
187 def SDNPAssociative : SDNodeProperty; // (X op Y) op Z == X op (Y op Z)
188 def SDNPHasChain : SDNodeProperty; // R/W chain operand and result
189 def SDNPOutFlag : SDNodeProperty; // Write a flag result
190 def SDNPInFlag : SDNodeProperty; // Read a flag operand
191 def SDNPOptInFlag : SDNodeProperty; // Optionally read a flag operand
192 def SDNPMayStore : SDNodeProperty; // May write to memory, sets 'mayStore'.
193 def SDNPMayLoad : SDNodeProperty; // May read memory, sets 'mayLoad'.
194 def SDNPSideEffect : SDNodeProperty; // Sets 'HasUnmodelledSideEffects'.
196 //===----------------------------------------------------------------------===//
197 // Selection DAG Node definitions.
199 class SDNode<string opcode, SDTypeProfile typeprof,
200 list<SDNodeProperty> props = [], string sdclass = "SDNode"> {
201 string Opcode = opcode;
202 string SDClass = sdclass;
203 list<SDNodeProperty> Properties = props;
204 SDTypeProfile TypeProfile = typeprof;
213 def imm : SDNode<"ISD::Constant" , SDTIntLeaf , [], "ConstantSDNode">;
214 def fpimm : SDNode<"ISD::TargetConstantFP",
215 SDTFPLeaf, [], "ConstantFPSDNode">;
216 def vt : SDNode<"ISD::VALUETYPE" , SDTOther , [], "VTSDNode">;
217 def bb : SDNode<"ISD::BasicBlock", SDTOther , [], "BasicBlockSDNode">;
218 def cond : SDNode<"ISD::CONDCODE" , SDTOther , [], "CondCodeSDNode">;
219 def undef : SDNode<"ISD::UNDEF" , SDTUNDEF , []>;
220 def globaladdr : SDNode<"ISD::GlobalAddress", SDTPtrLeaf, [],
221 "GlobalAddressSDNode">;
222 def tglobaladdr : SDNode<"ISD::TargetGlobalAddress", SDTPtrLeaf, [],
223 "GlobalAddressSDNode">;
224 def globaltlsaddr : SDNode<"ISD::GlobalTLSAddress", SDTPtrLeaf, [],
225 "GlobalAddressSDNode">;
226 def tglobaltlsaddr : SDNode<"ISD::TargetGlobalTLSAddress", SDTPtrLeaf, [],
227 "GlobalAddressSDNode">;
228 def constpool : SDNode<"ISD::ConstantPool", SDTPtrLeaf, [],
229 "ConstantPoolSDNode">;
230 def tconstpool : SDNode<"ISD::TargetConstantPool", SDTPtrLeaf, [],
231 "ConstantPoolSDNode">;
232 def jumptable : SDNode<"ISD::JumpTable", SDTPtrLeaf, [],
234 def tjumptable : SDNode<"ISD::TargetJumpTable", SDTPtrLeaf, [],
236 def frameindex : SDNode<"ISD::FrameIndex", SDTPtrLeaf, [],
238 def tframeindex : SDNode<"ISD::TargetFrameIndex", SDTPtrLeaf, [],
240 def externalsym : SDNode<"ISD::ExternalSymbol", SDTPtrLeaf, [],
241 "ExternalSymbolSDNode">;
242 def texternalsym: SDNode<"ISD::TargetExternalSymbol", SDTPtrLeaf, [],
243 "ExternalSymbolSDNode">;
245 def add : SDNode<"ISD::ADD" , SDTIntBinOp ,
246 [SDNPCommutative, SDNPAssociative]>;
247 def sub : SDNode<"ISD::SUB" , SDTIntBinOp>;
248 def mul : SDNode<"ISD::MUL" , SDTIntBinOp,
249 [SDNPCommutative, SDNPAssociative]>;
250 def mulhs : SDNode<"ISD::MULHS" , SDTIntBinOp, [SDNPCommutative]>;
251 def mulhu : SDNode<"ISD::MULHU" , SDTIntBinOp, [SDNPCommutative]>;
252 def sdiv : SDNode<"ISD::SDIV" , SDTIntBinOp>;
253 def udiv : SDNode<"ISD::UDIV" , SDTIntBinOp>;
254 def srem : SDNode<"ISD::SREM" , SDTIntBinOp>;
255 def urem : SDNode<"ISD::UREM" , SDTIntBinOp>;
256 def srl : SDNode<"ISD::SRL" , SDTIntShiftOp>;
257 def sra : SDNode<"ISD::SRA" , SDTIntShiftOp>;
258 def shl : SDNode<"ISD::SHL" , SDTIntShiftOp>;
259 def rotl : SDNode<"ISD::ROTL" , SDTIntShiftOp>;
260 def rotr : SDNode<"ISD::ROTR" , SDTIntShiftOp>;
261 def and : SDNode<"ISD::AND" , SDTIntBinOp,
262 [SDNPCommutative, SDNPAssociative]>;
263 def or : SDNode<"ISD::OR" , SDTIntBinOp,
264 [SDNPCommutative, SDNPAssociative]>;
265 def xor : SDNode<"ISD::XOR" , SDTIntBinOp,
266 [SDNPCommutative, SDNPAssociative]>;
267 def addc : SDNode<"ISD::ADDC" , SDTIntBinOp,
268 [SDNPCommutative, SDNPOutFlag]>;
269 def adde : SDNode<"ISD::ADDE" , SDTIntBinOp,
270 [SDNPCommutative, SDNPOutFlag, SDNPInFlag]>;
271 def subc : SDNode<"ISD::SUBC" , SDTIntBinOp,
273 def sube : SDNode<"ISD::SUBE" , SDTIntBinOp,
274 [SDNPOutFlag, SDNPInFlag]>;
276 def sext_inreg : SDNode<"ISD::SIGN_EXTEND_INREG", SDTExtInreg>;
277 def bswap : SDNode<"ISD::BSWAP" , SDTIntUnaryOp>;
278 def ctlz : SDNode<"ISD::CTLZ" , SDTIntUnaryOp>;
279 def cttz : SDNode<"ISD::CTTZ" , SDTIntUnaryOp>;
280 def ctpop : SDNode<"ISD::CTPOP" , SDTIntUnaryOp>;
281 def sext : SDNode<"ISD::SIGN_EXTEND", SDTIntExtendOp>;
282 def zext : SDNode<"ISD::ZERO_EXTEND", SDTIntExtendOp>;
283 def anyext : SDNode<"ISD::ANY_EXTEND" , SDTIntExtendOp>;
284 def trunc : SDNode<"ISD::TRUNCATE" , SDTIntTruncOp>;
285 def bitconvert : SDNode<"ISD::BIT_CONVERT", SDTUnaryOp>;
287 def fadd : SDNode<"ISD::FADD" , SDTFPBinOp, [SDNPCommutative]>;
288 def fsub : SDNode<"ISD::FSUB" , SDTFPBinOp>;
289 def fmul : SDNode<"ISD::FMUL" , SDTFPBinOp, [SDNPCommutative]>;
290 def fdiv : SDNode<"ISD::FDIV" , SDTFPBinOp>;
291 def frem : SDNode<"ISD::FREM" , SDTFPBinOp>;
292 def fabs : SDNode<"ISD::FABS" , SDTFPUnaryOp>;
293 def fneg : SDNode<"ISD::FNEG" , SDTFPUnaryOp>;
294 def fsqrt : SDNode<"ISD::FSQRT" , SDTFPUnaryOp>;
295 def fsin : SDNode<"ISD::FSIN" , SDTFPUnaryOp>;
296 def fcos : SDNode<"ISD::FCOS" , SDTFPUnaryOp>;
298 def fround : SDNode<"ISD::FP_ROUND" , SDTFPRoundOp>;
299 def fextend : SDNode<"ISD::FP_EXTEND" , SDTFPExtendOp>;
300 def fcopysign : SDNode<"ISD::FCOPYSIGN" , SDTFPSignOp>;
302 def sint_to_fp : SDNode<"ISD::SINT_TO_FP" , SDTIntToFPOp>;
303 def uint_to_fp : SDNode<"ISD::UINT_TO_FP" , SDTIntToFPOp>;
304 def fp_to_sint : SDNode<"ISD::FP_TO_SINT" , SDTFPToIntOp>;
305 def fp_to_uint : SDNode<"ISD::FP_TO_UINT" , SDTFPToIntOp>;
307 def setcc : SDNode<"ISD::SETCC" , SDTSetCC>;
308 def select : SDNode<"ISD::SELECT" , SDTSelect>;
309 def selectcc : SDNode<"ISD::SELECT_CC" , SDTSelectCC>;
311 def brcond : SDNode<"ISD::BRCOND" , SDTBrcond, [SDNPHasChain]>;
312 def brind : SDNode<"ISD::BRIND" , SDTBrind, [SDNPHasChain]>;
313 def br : SDNode<"ISD::BR" , SDTBr, [SDNPHasChain]>;
314 def ret : SDNode<"ISD::RET" , SDTRet, [SDNPHasChain]>;
316 // Do not use ld, st directly. Use load, extload, sextload, zextload, store,
317 // and truncst (see below).
318 def ld : SDNode<"ISD::LOAD" , SDTLoad,
319 [SDNPHasChain, SDNPMayLoad]>;
320 def st : SDNode<"ISD::STORE" , SDTStore,
321 [SDNPHasChain, SDNPMayStore]>;
322 def ist : SDNode<"ISD::STORE" , SDTIStore,
323 [SDNPHasChain, SDNPMayStore]>;
325 def vector_shuffle : SDNode<"ISD::VECTOR_SHUFFLE", SDTVecShuffle, []>;
326 def build_vector : SDNode<"ISD::BUILD_VECTOR", SDTypeProfile<1, 0, []>, []>;
327 def scalar_to_vector : SDNode<"ISD::SCALAR_TO_VECTOR", SDTypeProfile<1, 1, []>,
329 def vector_extract : SDNode<"ISD::EXTRACT_VECTOR_ELT",
330 SDTypeProfile<1, 2, [SDTCisPtrTy<2>]>, []>;
331 def vector_insert : SDNode<"ISD::INSERT_VECTOR_ELT",
332 SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisPtrTy<3>]>, []>;
334 def extract_subreg : SDNode<"ISD::EXTRACT_SUBREG",
335 SDTypeProfile<1, 2, []>>;
336 def insert_subreg : SDNode<"ISD::INSERT_SUBREG",
337 SDTypeProfile<1, 3, []>>;
339 // Nodes for intrinsics, you should use the intrinsic itself and let tblgen use
340 // these internally. Don't reference these directly.
341 def intrinsic_void : SDNode<"ISD::INTRINSIC_VOID",
342 SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>,
344 def intrinsic_w_chain : SDNode<"ISD::INTRINSIC_W_CHAIN",
345 SDTypeProfile<1, -1, [SDTCisPtrTy<1>]>,
347 def intrinsic_wo_chain : SDNode<"ISD::INTRINSIC_WO_CHAIN",
348 SDTypeProfile<1, -1, [SDTCisPtrTy<1>]>, []>;
351 //===----------------------------------------------------------------------===//
352 // Selection DAG Condition Codes
354 class CondCode; // ISD::CondCode enums
355 def SETOEQ : CondCode; def SETOGT : CondCode;
356 def SETOGE : CondCode; def SETOLT : CondCode; def SETOLE : CondCode;
357 def SETONE : CondCode; def SETO : CondCode; def SETUO : CondCode;
358 def SETUEQ : CondCode; def SETUGT : CondCode; def SETUGE : CondCode;
359 def SETULT : CondCode; def SETULE : CondCode; def SETUNE : CondCode;
361 def SETEQ : CondCode; def SETGT : CondCode; def SETGE : CondCode;
362 def SETLT : CondCode; def SETLE : CondCode; def SETNE : CondCode;
365 //===----------------------------------------------------------------------===//
366 // Selection DAG Node Transformation Functions.
368 // This mechanism allows targets to manipulate nodes in the output DAG once a
369 // match has been formed. This is typically used to manipulate immediate
372 class SDNodeXForm<SDNode opc, code xformFunction> {
374 code XFormFunction = xformFunction;
377 def NOOP_SDNodeXForm : SDNodeXForm<imm, [{}]>;
380 //===----------------------------------------------------------------------===//
381 // Selection DAG Pattern Fragments.
383 // Pattern fragments are reusable chunks of dags that match specific things.
384 // They can take arguments and have C++ predicates that control whether they
385 // match. They are intended to make the patterns for common instructions more
386 // compact and readable.
389 /// PatFrag - Represents a pattern fragment. This can match something on the
390 /// DAG, frame a single node to multiply nested other fragments.
392 class PatFrag<dag ops, dag frag, code pred = [{}],
393 SDNodeXForm xform = NOOP_SDNodeXForm> {
396 code Predicate = pred;
397 SDNodeXForm OperandTransform = xform;
400 // PatLeaf's are pattern fragments that have no operands. This is just a helper
401 // to define immediates and other common things concisely.
402 class PatLeaf<dag frag, code pred = [{}], SDNodeXForm xform = NOOP_SDNodeXForm>
403 : PatFrag<(ops), frag, pred, xform>;
407 def vtInt : PatLeaf<(vt), [{ return MVT::isInteger(N->getVT()); }]>;
408 def vtFP : PatLeaf<(vt), [{ return MVT::isFloatingPoint(N->getVT()); }]>;
410 def immAllOnes : PatLeaf<(imm), [{ return N->isAllOnesValue(); }]>;
411 def immAllOnesV: PatLeaf<(build_vector), [{
412 return ISD::isBuildVectorAllOnes(N);
414 def immAllOnesV_bc: PatLeaf<(bitconvert), [{
415 return ISD::isBuildVectorAllOnes(N);
417 def immAllZerosV: PatLeaf<(build_vector), [{
418 return ISD::isBuildVectorAllZeros(N);
420 def immAllZerosV_bc: PatLeaf<(bitconvert), [{
421 return ISD::isBuildVectorAllZeros(N);
426 // Other helper fragments.
427 def not : PatFrag<(ops node:$in), (xor node:$in, immAllOnes)>;
428 def vnot : PatFrag<(ops node:$in), (xor node:$in, immAllOnesV)>;
429 def vnot_conv : PatFrag<(ops node:$in), (xor node:$in, immAllOnesV_bc)>;
430 def ineg : PatFrag<(ops node:$in), (sub 0, node:$in)>;
433 def load : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
434 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
435 return LD->getExtensionType() == ISD::NON_EXTLOAD &&
436 LD->getAddressingMode() == ISD::UNINDEXED;
440 // extending load fragments.
441 def extloadi1 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
442 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
443 return LD->getExtensionType() == ISD::EXTLOAD &&
444 LD->getAddressingMode() == ISD::UNINDEXED &&
445 LD->getLoadedVT() == MVT::i1;
448 def extloadi8 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
449 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
450 return LD->getExtensionType() == ISD::EXTLOAD &&
451 LD->getAddressingMode() == ISD::UNINDEXED &&
452 LD->getLoadedVT() == MVT::i8;
455 def extloadi16 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
456 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
457 return LD->getExtensionType() == ISD::EXTLOAD &&
458 LD->getAddressingMode() == ISD::UNINDEXED &&
459 LD->getLoadedVT() == MVT::i16;
462 def extloadi32 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
463 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
464 return LD->getExtensionType() == ISD::EXTLOAD &&
465 LD->getAddressingMode() == ISD::UNINDEXED &&
466 LD->getLoadedVT() == MVT::i32;
469 def extloadf32 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
470 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
471 return LD->getExtensionType() == ISD::EXTLOAD &&
472 LD->getAddressingMode() == ISD::UNINDEXED &&
473 LD->getLoadedVT() == MVT::f32;
476 def extloadf64 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
477 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
478 return LD->getExtensionType() == ISD::EXTLOAD &&
479 LD->getAddressingMode() == ISD::UNINDEXED &&
480 LD->getLoadedVT() == MVT::f64;
484 def sextloadi1 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
485 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
486 return LD->getExtensionType() == ISD::SEXTLOAD &&
487 LD->getAddressingMode() == ISD::UNINDEXED &&
488 LD->getLoadedVT() == MVT::i1;
491 def sextloadi8 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
492 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
493 return LD->getExtensionType() == ISD::SEXTLOAD &&
494 LD->getAddressingMode() == ISD::UNINDEXED &&
495 LD->getLoadedVT() == MVT::i8;
498 def sextloadi16 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
499 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
500 return LD->getExtensionType() == ISD::SEXTLOAD &&
501 LD->getAddressingMode() == ISD::UNINDEXED &&
502 LD->getLoadedVT() == MVT::i16;
505 def sextloadi32 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
506 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
507 return LD->getExtensionType() == ISD::SEXTLOAD &&
508 LD->getAddressingMode() == ISD::UNINDEXED &&
509 LD->getLoadedVT() == MVT::i32;
513 def zextloadi1 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
514 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
515 return LD->getExtensionType() == ISD::ZEXTLOAD &&
516 LD->getAddressingMode() == ISD::UNINDEXED &&
517 LD->getLoadedVT() == MVT::i1;
520 def zextloadi8 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
521 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
522 return LD->getExtensionType() == ISD::ZEXTLOAD &&
523 LD->getAddressingMode() == ISD::UNINDEXED &&
524 LD->getLoadedVT() == MVT::i8;
527 def zextloadi16 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
528 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
529 return LD->getExtensionType() == ISD::ZEXTLOAD &&
530 LD->getAddressingMode() == ISD::UNINDEXED &&
531 LD->getLoadedVT() == MVT::i16;
534 def zextloadi32 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
535 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
536 return LD->getExtensionType() == ISD::ZEXTLOAD &&
537 LD->getAddressingMode() == ISD::UNINDEXED &&
538 LD->getLoadedVT() == MVT::i32;
543 def store : PatFrag<(ops node:$val, node:$ptr),
544 (st node:$val, node:$ptr), [{
545 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
546 return !ST->isTruncatingStore() &&
547 ST->getAddressingMode() == ISD::UNINDEXED;
551 // truncstore fragments.
552 def truncstorei1 : PatFrag<(ops node:$val, node:$ptr),
553 (st node:$val, node:$ptr), [{
554 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
555 return ST->isTruncatingStore() && ST->getStoredVT() == MVT::i1 &&
556 ST->getAddressingMode() == ISD::UNINDEXED;
559 def truncstorei8 : PatFrag<(ops node:$val, node:$ptr),
560 (st node:$val, node:$ptr), [{
561 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
562 return ST->isTruncatingStore() && ST->getStoredVT() == MVT::i8 &&
563 ST->getAddressingMode() == ISD::UNINDEXED;
566 def truncstorei16 : PatFrag<(ops node:$val, node:$ptr),
567 (st node:$val, node:$ptr), [{
568 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
569 return ST->isTruncatingStore() && ST->getStoredVT() == MVT::i16 &&
570 ST->getAddressingMode() == ISD::UNINDEXED;
573 def truncstorei32 : PatFrag<(ops node:$val, node:$ptr),
574 (st node:$val, node:$ptr), [{
575 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
576 return ST->isTruncatingStore() && ST->getStoredVT() == MVT::i32 &&
577 ST->getAddressingMode() == ISD::UNINDEXED;
580 def truncstoref32 : PatFrag<(ops node:$val, node:$ptr),
581 (st node:$val, node:$ptr), [{
582 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
583 return ST->isTruncatingStore() && ST->getStoredVT() == MVT::f32 &&
584 ST->getAddressingMode() == ISD::UNINDEXED;
587 def truncstoref64 : PatFrag<(ops node:$val, node:$ptr),
588 (st node:$val, node:$ptr), [{
589 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
590 return ST->isTruncatingStore() && ST->getStoredVT() == MVT::f64 &&
591 ST->getAddressingMode() == ISD::UNINDEXED;
595 // indexed store fragments.
596 def pre_store : PatFrag<(ops node:$val, node:$base, node:$offset),
597 (ist node:$val, node:$base, node:$offset), [{
598 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
599 ISD::MemIndexedMode AM = ST->getAddressingMode();
600 return (AM == ISD::PRE_INC || AM == ISD::PRE_DEC) &&
601 !ST->isTruncatingStore();
606 def pre_truncsti1 : PatFrag<(ops node:$val, node:$base, node:$offset),
607 (ist node:$val, node:$base, node:$offset), [{
608 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
609 ISD::MemIndexedMode AM = ST->getAddressingMode();
610 return (AM == ISD::PRE_INC || AM == ISD::PRE_DEC) &&
611 ST->isTruncatingStore() && ST->getStoredVT() == MVT::i1;
615 def pre_truncsti8 : PatFrag<(ops node:$val, node:$base, node:$offset),
616 (ist node:$val, node:$base, node:$offset), [{
617 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
618 ISD::MemIndexedMode AM = ST->getAddressingMode();
619 return (AM == ISD::PRE_INC || AM == ISD::PRE_DEC) &&
620 ST->isTruncatingStore() && ST->getStoredVT() == MVT::i8;
624 def pre_truncsti16 : PatFrag<(ops node:$val, node:$base, node:$offset),
625 (ist node:$val, node:$base, node:$offset), [{
626 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
627 ISD::MemIndexedMode AM = ST->getAddressingMode();
628 return (AM == ISD::PRE_INC || AM == ISD::PRE_DEC) &&
629 ST->isTruncatingStore() && ST->getStoredVT() == MVT::i16;
633 def pre_truncsti32 : PatFrag<(ops node:$val, node:$base, node:$offset),
634 (ist node:$val, node:$base, node:$offset), [{
635 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
636 ISD::MemIndexedMode AM = ST->getAddressingMode();
637 return (AM == ISD::PRE_INC || AM == ISD::PRE_DEC) &&
638 ST->isTruncatingStore() && ST->getStoredVT() == MVT::i32;
642 def pre_truncstf32 : PatFrag<(ops node:$val, node:$base, node:$offset),
643 (ist node:$val, node:$base, node:$offset), [{
644 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
645 ISD::MemIndexedMode AM = ST->getAddressingMode();
646 return (AM == ISD::PRE_INC || AM == ISD::PRE_DEC) &&
647 ST->isTruncatingStore() && ST->getStoredVT() == MVT::f32;
652 def post_store : PatFrag<(ops node:$val, node:$ptr, node:$offset),
653 (ist node:$val, node:$ptr, node:$offset), [{
654 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
655 ISD::MemIndexedMode AM = ST->getAddressingMode();
656 return !ST->isTruncatingStore() &&
657 (AM == ISD::POST_INC || AM == ISD::POST_DEC);
662 def post_truncsti1 : PatFrag<(ops node:$val, node:$base, node:$offset),
663 (ist node:$val, node:$base, node:$offset), [{
664 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
665 ISD::MemIndexedMode AM = ST->getAddressingMode();
666 return (AM == ISD::POST_INC || AM == ISD::POST_DEC) &&
667 ST->isTruncatingStore() && ST->getStoredVT() == MVT::i1;
671 def post_truncsti8 : PatFrag<(ops node:$val, node:$base, node:$offset),
672 (ist node:$val, node:$base, node:$offset), [{
673 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
674 ISD::MemIndexedMode AM = ST->getAddressingMode();
675 return (AM == ISD::POST_INC || AM == ISD::POST_DEC) &&
676 ST->isTruncatingStore() && ST->getStoredVT() == MVT::i8;
680 def post_truncsti16 : PatFrag<(ops node:$val, node:$base, node:$offset),
681 (ist node:$val, node:$base, node:$offset), [{
682 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
683 ISD::MemIndexedMode AM = ST->getAddressingMode();
684 return (AM == ISD::POST_INC || AM == ISD::POST_DEC) &&
685 ST->isTruncatingStore() && ST->getStoredVT() == MVT::i16;
689 def post_truncsti32 : PatFrag<(ops node:$val, node:$base, node:$offset),
690 (ist node:$val, node:$base, node:$offset), [{
691 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
692 ISD::MemIndexedMode AM = ST->getAddressingMode();
693 return (AM == ISD::POST_INC || AM == ISD::POST_DEC) &&
694 ST->isTruncatingStore() && ST->getStoredVT() == MVT::i32;
698 def post_truncstf32 : PatFrag<(ops node:$val, node:$base, node:$offset),
699 (ist node:$val, node:$base, node:$offset), [{
700 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
701 ISD::MemIndexedMode AM = ST->getAddressingMode();
702 return (AM == ISD::POST_INC || AM == ISD::POST_DEC) &&
703 ST->isTruncatingStore() && ST->getStoredVT() == MVT::f32;
708 // setcc convenience fragments.
709 def setoeq : PatFrag<(ops node:$lhs, node:$rhs),
710 (setcc node:$lhs, node:$rhs, SETOEQ)>;
711 def setogt : PatFrag<(ops node:$lhs, node:$rhs),
712 (setcc node:$lhs, node:$rhs, SETOGT)>;
713 def setoge : PatFrag<(ops node:$lhs, node:$rhs),
714 (setcc node:$lhs, node:$rhs, SETOGE)>;
715 def setolt : PatFrag<(ops node:$lhs, node:$rhs),
716 (setcc node:$lhs, node:$rhs, SETOLT)>;
717 def setole : PatFrag<(ops node:$lhs, node:$rhs),
718 (setcc node:$lhs, node:$rhs, SETOLE)>;
719 def setone : PatFrag<(ops node:$lhs, node:$rhs),
720 (setcc node:$lhs, node:$rhs, SETONE)>;
721 def seto : PatFrag<(ops node:$lhs, node:$rhs),
722 (setcc node:$lhs, node:$rhs, SETO)>;
723 def setuo : PatFrag<(ops node:$lhs, node:$rhs),
724 (setcc node:$lhs, node:$rhs, SETUO)>;
725 def setueq : PatFrag<(ops node:$lhs, node:$rhs),
726 (setcc node:$lhs, node:$rhs, SETUEQ)>;
727 def setugt : PatFrag<(ops node:$lhs, node:$rhs),
728 (setcc node:$lhs, node:$rhs, SETUGT)>;
729 def setuge : PatFrag<(ops node:$lhs, node:$rhs),
730 (setcc node:$lhs, node:$rhs, SETUGE)>;
731 def setult : PatFrag<(ops node:$lhs, node:$rhs),
732 (setcc node:$lhs, node:$rhs, SETULT)>;
733 def setule : PatFrag<(ops node:$lhs, node:$rhs),
734 (setcc node:$lhs, node:$rhs, SETULE)>;
735 def setune : PatFrag<(ops node:$lhs, node:$rhs),
736 (setcc node:$lhs, node:$rhs, SETUNE)>;
737 def seteq : PatFrag<(ops node:$lhs, node:$rhs),
738 (setcc node:$lhs, node:$rhs, SETEQ)>;
739 def setgt : PatFrag<(ops node:$lhs, node:$rhs),
740 (setcc node:$lhs, node:$rhs, SETGT)>;
741 def setge : PatFrag<(ops node:$lhs, node:$rhs),
742 (setcc node:$lhs, node:$rhs, SETGE)>;
743 def setlt : PatFrag<(ops node:$lhs, node:$rhs),
744 (setcc node:$lhs, node:$rhs, SETLT)>;
745 def setle : PatFrag<(ops node:$lhs, node:$rhs),
746 (setcc node:$lhs, node:$rhs, SETLE)>;
747 def setne : PatFrag<(ops node:$lhs, node:$rhs),
748 (setcc node:$lhs, node:$rhs, SETNE)>;
750 //===----------------------------------------------------------------------===//
751 // Selection DAG Pattern Support.
753 // Patterns are what are actually matched against the target-flavored
754 // instruction selection DAG. Instructions defined by the target implicitly
755 // define patterns in most cases, but patterns can also be explicitly added when
756 // an operation is defined by a sequence of instructions (e.g. loading a large
757 // immediate value on RISC targets that do not support immediates as large as
761 class Pattern<dag patternToMatch, list<dag> resultInstrs> {
762 dag PatternToMatch = patternToMatch;
763 list<dag> ResultInstrs = resultInstrs;
764 list<Predicate> Predicates = []; // See class Instruction in Target.td.
765 int AddedComplexity = 0; // See class Instruction in Target.td.
768 // Pat - A simple (but common) form of a pattern, which produces a simple result
769 // not needing a full list.
770 class Pat<dag pattern, dag result> : Pattern<pattern, [result]>;
772 //===----------------------------------------------------------------------===//
773 // Complex pattern definitions.
775 // Complex patterns, e.g. X86 addressing mode, requires pattern matching code
776 // in C++. NumOperands is the number of operands returned by the select function;
777 // SelectFunc is the name of the function used to pattern match the max. pattern;
778 // RootNodes are the list of possible root nodes of the sub-dags to match.
779 // e.g. X86 addressing mode - def addr : ComplexPattern<4, "SelectAddr", [add]>;
781 class ComplexPattern<ValueType ty, int numops, string fn,
782 list<SDNode> roots = [], list<SDNodeProperty> props = []> {
784 int NumOperands = numops;
785 string SelectFunc = fn;
786 list<SDNode> RootNodes = roots;
787 list<SDNodeProperty> Properties = props;
790 //===----------------------------------------------------------------------===//
793 def SDT_dwarf_loc : SDTypeProfile<0, 3,
794 [SDTCisInt<0>, SDTCisInt<1>, SDTCisInt<2>]>;
795 def dwarf_loc : SDNode<"ISD::DEBUG_LOC", SDT_dwarf_loc,[SDNPHasChain]>;