1 //===- TargetSelectionDAG.td - Common code for DAG isels ---*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the target-independent interfaces used by SelectionDAG
11 // instruction selection generators.
13 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
16 // Selection DAG Type Constraint definitions.
18 // Note that the semantics of these constraints are hard coded into tblgen. To
19 // modify or add constraints, you have to hack tblgen.
22 class SDTypeConstraint<int opnum> {
23 int OperandNum = opnum;
26 // SDTCisVT - The specified operand has exactly this VT.
27 class SDTCisVT<int OpNum, ValueType vt> : SDTypeConstraint<OpNum> {
31 class SDTCisPtrTy<int OpNum> : SDTypeConstraint<OpNum>;
33 // SDTCisInt - The specified operand is has integer type.
34 class SDTCisInt<int OpNum> : SDTypeConstraint<OpNum>;
36 // SDTCisFP - The specified operand is has floating point type.
37 class SDTCisFP<int OpNum> : SDTypeConstraint<OpNum>;
39 // SDTCisSameAs - The two specified operands have identical types.
40 class SDTCisSameAs<int OpNum, int OtherOp> : SDTypeConstraint<OpNum> {
41 int OtherOperandNum = OtherOp;
44 // SDTCisVTSmallerThanOp - The specified operand is a VT SDNode, and its type is
45 // smaller than the 'Other' operand.
46 class SDTCisVTSmallerThanOp<int OpNum, int OtherOp> : SDTypeConstraint<OpNum> {
47 int OtherOperandNum = OtherOp;
50 class SDTCisOpSmallerThanOp<int SmallOp, int BigOp> : SDTypeConstraint<SmallOp>{
51 int BigOperandNum = BigOp;
54 /// SDTCisIntVectorOfSameSize - This indicates that ThisOp and OtherOp are
55 /// vector types, and that ThisOp is the result of
56 /// MVT::getIntVectorWithNumElements with the number of elements
58 class SDTCisIntVectorOfSameSize<int ThisOp, int OtherOp>
59 : SDTypeConstraint<ThisOp> {
60 int OtherOpNum = OtherOp;
63 /// SDTCisEltOfVec - This indicates that ThisOp is a scalar type of the same
64 /// type as the element type of OtherOp, which is a vector type.
65 class SDTCisEltOfVec<int ThisOp, int OtherOp>
66 : SDTypeConstraint<ThisOp> {
67 int OtherOpNum = OtherOp;
70 //===----------------------------------------------------------------------===//
71 // Selection DAG Type Profile definitions.
73 // These use the constraints defined above to describe the type requirements of
74 // the various nodes. These are not hard coded into tblgen, allowing targets to
75 // add their own if needed.
78 // SDTypeProfile - This profile describes the type requirements of a Selection
80 class SDTypeProfile<int numresults, int numoperands,
81 list<SDTypeConstraint> constraints> {
82 int NumResults = numresults;
83 int NumOperands = numoperands;
84 list<SDTypeConstraint> Constraints = constraints;
88 def SDTIntLeaf: SDTypeProfile<1, 0, [SDTCisInt<0>]>; // for 'imm'.
89 def SDTFPLeaf : SDTypeProfile<1, 0, [SDTCisFP<0>]>; // for 'fpimm'.
90 def SDTPtrLeaf: SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>; // for '&g'.
91 def SDTOther : SDTypeProfile<1, 0, [SDTCisVT<0, OtherVT>]>; // for 'vt'.
92 def SDTUNDEF : SDTypeProfile<1, 0, []>; // for 'undef'.
93 def SDTUnaryOp : SDTypeProfile<1, 1, []>; // bitconvert
95 def SDTIntBinOp : SDTypeProfile<1, 2, [ // add, and, or, xor, udiv, etc.
96 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<0>
98 def SDTIntShiftOp : SDTypeProfile<1, 2, [ // shl, sra, srl
99 SDTCisSameAs<0, 1>, SDTCisInt<0>, SDTCisInt<2>
101 def SDTFPBinOp : SDTypeProfile<1, 2, [ // fadd, fmul, etc.
102 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisFP<0>
104 def SDTFPSignOp : SDTypeProfile<1, 2, [ // fcopysign.
105 SDTCisSameAs<0, 1>, SDTCisFP<0>, SDTCisFP<2>
107 def SDTFPTernaryOp : SDTypeProfile<1, 3, [ // fmadd, fnmsub, etc.
108 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>, SDTCisFP<0>
110 def SDTIntUnaryOp : SDTypeProfile<1, 1, [ // ctlz
111 SDTCisSameAs<0, 1>, SDTCisInt<0>
113 def SDTIntExtendOp : SDTypeProfile<1, 1, [ // sext, zext, anyext
114 SDTCisInt<0>, SDTCisInt<1>, SDTCisOpSmallerThanOp<1, 0>
116 def SDTIntTruncOp : SDTypeProfile<1, 1, [ // trunc
117 SDTCisInt<0>, SDTCisInt<1>, SDTCisOpSmallerThanOp<0, 1>
119 def SDTFPUnaryOp : SDTypeProfile<1, 1, [ // fneg, fsqrt, etc
120 SDTCisSameAs<0, 1>, SDTCisFP<0>
122 def SDTFPRoundOp : SDTypeProfile<1, 1, [ // fround
123 SDTCisFP<0>, SDTCisFP<1>, SDTCisOpSmallerThanOp<0, 1>
125 def SDTFPExtendOp : SDTypeProfile<1, 1, [ // fextend
126 SDTCisFP<0>, SDTCisFP<1>, SDTCisOpSmallerThanOp<1, 0>
128 def SDTIntToFPOp : SDTypeProfile<1, 1, [ // [su]int_to_fp
129 SDTCisFP<0>, SDTCisInt<1>
131 def SDTFPToIntOp : SDTypeProfile<1, 1, [ // fp_to_[su]int
132 SDTCisInt<0>, SDTCisFP<1>
134 def SDTExtInreg : SDTypeProfile<1, 2, [ // sext_inreg
135 SDTCisSameAs<0, 1>, SDTCisInt<0>, SDTCisVT<2, OtherVT>,
136 SDTCisVTSmallerThanOp<2, 1>
139 def SDTSetCC : SDTypeProfile<1, 3, [ // setcc
140 SDTCisInt<0>, SDTCisSameAs<1, 2>, SDTCisVT<3, OtherVT>
143 def SDTSelect : SDTypeProfile<1, 3, [ // select
144 SDTCisInt<1>, SDTCisSameAs<0, 2>, SDTCisSameAs<2, 3>
147 def SDTSelectCC : SDTypeProfile<1, 5, [ // select_cc
148 SDTCisSameAs<1, 2>, SDTCisSameAs<3, 4>, SDTCisSameAs<0, 3>,
152 def SDTBr : SDTypeProfile<0, 1, [ // br
156 def SDTBrcond : SDTypeProfile<0, 2, [ // brcond
157 SDTCisInt<0>, SDTCisVT<1, OtherVT>
160 def SDTBrind : SDTypeProfile<0, 1, [ // brind
164 def SDTNone : SDTypeProfile<0, 0, []>; // ret, trap
166 def SDTLoad : SDTypeProfile<1, 1, [ // load
170 def SDTStore : SDTypeProfile<0, 2, [ // store
174 def SDTIStore : SDTypeProfile<1, 3, [ // indexed store
175 SDTCisSameAs<0, 2>, SDTCisPtrTy<0>, SDTCisPtrTy<3>
178 def SDTVecShuffle : SDTypeProfile<1, 3, [
179 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisIntVectorOfSameSize<3, 0>
181 def SDTVecExtract : SDTypeProfile<1, 2, [ // vector extract
182 SDTCisEltOfVec<0, 1>, SDTCisPtrTy<2>
184 def SDTVecInsert : SDTypeProfile<1, 3, [ // vector insert
185 SDTCisEltOfVec<2, 1>, SDTCisSameAs<0, 1>, SDTCisPtrTy<3>
188 def STDPrefetch : SDTypeProfile<0, 3, [ // prefetch
189 SDTCisPtrTy<0>, SDTCisSameAs<1, 2>, SDTCisInt<1>
192 def STDMemBarrier : SDTypeProfile<0, 5, [ // memory barier
193 SDTCisSameAs<0,1>, SDTCisSameAs<0,2>, SDTCisSameAs<0,3>, SDTCisSameAs<0,4>,
196 def STDAtomic3 : SDTypeProfile<1, 3, [
197 SDTCisSameAs<0,2>, SDTCisSameAs<0,3>, SDTCisInt<0>, SDTCisPtrTy<1>
199 def STDAtomic2 : SDTypeProfile<1, 2, [
200 SDTCisSameAs<0,2>, SDTCisInt<0>, SDTCisPtrTy<1>
203 class SDCallSeqStart<list<SDTypeConstraint> constraints> :
204 SDTypeProfile<0, 1, constraints>;
205 class SDCallSeqEnd<list<SDTypeConstraint> constraints> :
206 SDTypeProfile<0, 2, constraints>;
208 //===----------------------------------------------------------------------===//
209 // Selection DAG Node Properties.
211 // Note: These are hard coded into tblgen.
213 class SDNodeProperty;
214 def SDNPCommutative : SDNodeProperty; // X op Y == Y op X
215 def SDNPAssociative : SDNodeProperty; // (X op Y) op Z == X op (Y op Z)
216 def SDNPHasChain : SDNodeProperty; // R/W chain operand and result
217 def SDNPOutFlag : SDNodeProperty; // Write a flag result
218 def SDNPInFlag : SDNodeProperty; // Read a flag operand
219 def SDNPOptInFlag : SDNodeProperty; // Optionally read a flag operand
220 def SDNPMayStore : SDNodeProperty; // May write to memory, sets 'mayStore'.
221 def SDNPMayLoad : SDNodeProperty; // May read memory, sets 'mayLoad'.
222 def SDNPSideEffect : SDNodeProperty; // Sets 'HasUnmodelledSideEffects'.
223 def SDNPMemOperand : SDNodeProperty; // Touches memory, has assoc MemOperand
225 //===----------------------------------------------------------------------===//
226 // Selection DAG Node definitions.
228 class SDNode<string opcode, SDTypeProfile typeprof,
229 list<SDNodeProperty> props = [], string sdclass = "SDNode"> {
230 string Opcode = opcode;
231 string SDClass = sdclass;
232 list<SDNodeProperty> Properties = props;
233 SDTypeProfile TypeProfile = typeprof;
242 def imm : SDNode<"ISD::Constant" , SDTIntLeaf , [], "ConstantSDNode">;
243 def fpimm : SDNode<"ISD::ConstantFP", SDTFPLeaf , [], "ConstantFPSDNode">;
244 def vt : SDNode<"ISD::VALUETYPE" , SDTOther , [], "VTSDNode">;
245 def bb : SDNode<"ISD::BasicBlock", SDTOther , [], "BasicBlockSDNode">;
246 def cond : SDNode<"ISD::CONDCODE" , SDTOther , [], "CondCodeSDNode">;
247 def undef : SDNode<"ISD::UNDEF" , SDTUNDEF , []>;
248 def globaladdr : SDNode<"ISD::GlobalAddress", SDTPtrLeaf, [],
249 "GlobalAddressSDNode">;
250 def tglobaladdr : SDNode<"ISD::TargetGlobalAddress", SDTPtrLeaf, [],
251 "GlobalAddressSDNode">;
252 def globaltlsaddr : SDNode<"ISD::GlobalTLSAddress", SDTPtrLeaf, [],
253 "GlobalAddressSDNode">;
254 def tglobaltlsaddr : SDNode<"ISD::TargetGlobalTLSAddress", SDTPtrLeaf, [],
255 "GlobalAddressSDNode">;
256 def constpool : SDNode<"ISD::ConstantPool", SDTPtrLeaf, [],
257 "ConstantPoolSDNode">;
258 def tconstpool : SDNode<"ISD::TargetConstantPool", SDTPtrLeaf, [],
259 "ConstantPoolSDNode">;
260 def jumptable : SDNode<"ISD::JumpTable", SDTPtrLeaf, [],
262 def tjumptable : SDNode<"ISD::TargetJumpTable", SDTPtrLeaf, [],
264 def frameindex : SDNode<"ISD::FrameIndex", SDTPtrLeaf, [],
266 def tframeindex : SDNode<"ISD::TargetFrameIndex", SDTPtrLeaf, [],
268 def externalsym : SDNode<"ISD::ExternalSymbol", SDTPtrLeaf, [],
269 "ExternalSymbolSDNode">;
270 def texternalsym: SDNode<"ISD::TargetExternalSymbol", SDTPtrLeaf, [],
271 "ExternalSymbolSDNode">;
273 def add : SDNode<"ISD::ADD" , SDTIntBinOp ,
274 [SDNPCommutative, SDNPAssociative]>;
275 def sub : SDNode<"ISD::SUB" , SDTIntBinOp>;
276 def mul : SDNode<"ISD::MUL" , SDTIntBinOp,
277 [SDNPCommutative, SDNPAssociative]>;
278 def mulhs : SDNode<"ISD::MULHS" , SDTIntBinOp, [SDNPCommutative]>;
279 def mulhu : SDNode<"ISD::MULHU" , SDTIntBinOp, [SDNPCommutative]>;
280 def sdiv : SDNode<"ISD::SDIV" , SDTIntBinOp>;
281 def udiv : SDNode<"ISD::UDIV" , SDTIntBinOp>;
282 def srem : SDNode<"ISD::SREM" , SDTIntBinOp>;
283 def urem : SDNode<"ISD::UREM" , SDTIntBinOp>;
284 def srl : SDNode<"ISD::SRL" , SDTIntShiftOp>;
285 def sra : SDNode<"ISD::SRA" , SDTIntShiftOp>;
286 def shl : SDNode<"ISD::SHL" , SDTIntShiftOp>;
287 def rotl : SDNode<"ISD::ROTL" , SDTIntShiftOp>;
288 def rotr : SDNode<"ISD::ROTR" , SDTIntShiftOp>;
289 def and : SDNode<"ISD::AND" , SDTIntBinOp,
290 [SDNPCommutative, SDNPAssociative]>;
291 def or : SDNode<"ISD::OR" , SDTIntBinOp,
292 [SDNPCommutative, SDNPAssociative]>;
293 def xor : SDNode<"ISD::XOR" , SDTIntBinOp,
294 [SDNPCommutative, SDNPAssociative]>;
295 def addc : SDNode<"ISD::ADDC" , SDTIntBinOp,
296 [SDNPCommutative, SDNPOutFlag]>;
297 def adde : SDNode<"ISD::ADDE" , SDTIntBinOp,
298 [SDNPCommutative, SDNPOutFlag, SDNPInFlag]>;
299 def subc : SDNode<"ISD::SUBC" , SDTIntBinOp,
301 def sube : SDNode<"ISD::SUBE" , SDTIntBinOp,
302 [SDNPOutFlag, SDNPInFlag]>;
304 def sext_inreg : SDNode<"ISD::SIGN_EXTEND_INREG", SDTExtInreg>;
305 def bswap : SDNode<"ISD::BSWAP" , SDTIntUnaryOp>;
306 def ctlz : SDNode<"ISD::CTLZ" , SDTIntUnaryOp>;
307 def cttz : SDNode<"ISD::CTTZ" , SDTIntUnaryOp>;
308 def ctpop : SDNode<"ISD::CTPOP" , SDTIntUnaryOp>;
309 def sext : SDNode<"ISD::SIGN_EXTEND", SDTIntExtendOp>;
310 def zext : SDNode<"ISD::ZERO_EXTEND", SDTIntExtendOp>;
311 def anyext : SDNode<"ISD::ANY_EXTEND" , SDTIntExtendOp>;
312 def trunc : SDNode<"ISD::TRUNCATE" , SDTIntTruncOp>;
313 def bitconvert : SDNode<"ISD::BIT_CONVERT", SDTUnaryOp>;
314 def extractelt : SDNode<"ISD::EXTRACT_VECTOR_ELT", SDTVecExtract>;
315 def insertelt : SDNode<"ISD::INSERT_VECTOR_ELT", SDTVecInsert>;
318 def fadd : SDNode<"ISD::FADD" , SDTFPBinOp, [SDNPCommutative]>;
319 def fsub : SDNode<"ISD::FSUB" , SDTFPBinOp>;
320 def fmul : SDNode<"ISD::FMUL" , SDTFPBinOp, [SDNPCommutative]>;
321 def fdiv : SDNode<"ISD::FDIV" , SDTFPBinOp>;
322 def frem : SDNode<"ISD::FREM" , SDTFPBinOp>;
323 def fabs : SDNode<"ISD::FABS" , SDTFPUnaryOp>;
324 def fneg : SDNode<"ISD::FNEG" , SDTFPUnaryOp>;
325 def fsqrt : SDNode<"ISD::FSQRT" , SDTFPUnaryOp>;
326 def fsin : SDNode<"ISD::FSIN" , SDTFPUnaryOp>;
327 def fcos : SDNode<"ISD::FCOS" , SDTFPUnaryOp>;
328 def frint : SDNode<"ISD::FRINT" , SDTFPUnaryOp>;
329 def ftrunc : SDNode<"ISD::FTRUNC" , SDTFPUnaryOp>;
330 def fceil : SDNode<"ISD::FCEIL" , SDTFPUnaryOp>;
331 def ffloor : SDNode<"ISD::FFLOOR" , SDTFPUnaryOp>;
332 def fnearbyint : SDNode<"ISD::FNEARBYINT" , SDTFPUnaryOp>;
334 def fround : SDNode<"ISD::FP_ROUND" , SDTFPRoundOp>;
335 def fextend : SDNode<"ISD::FP_EXTEND" , SDTFPExtendOp>;
336 def fcopysign : SDNode<"ISD::FCOPYSIGN" , SDTFPSignOp>;
338 def sint_to_fp : SDNode<"ISD::SINT_TO_FP" , SDTIntToFPOp>;
339 def uint_to_fp : SDNode<"ISD::UINT_TO_FP" , SDTIntToFPOp>;
340 def fp_to_sint : SDNode<"ISD::FP_TO_SINT" , SDTFPToIntOp>;
341 def fp_to_uint : SDNode<"ISD::FP_TO_UINT" , SDTFPToIntOp>;
343 def setcc : SDNode<"ISD::SETCC" , SDTSetCC>;
344 def select : SDNode<"ISD::SELECT" , SDTSelect>;
345 def selectcc : SDNode<"ISD::SELECT_CC" , SDTSelectCC>;
346 def vsetcc : SDNode<"ISD::VSETCC" , SDTSetCC>;
348 def brcond : SDNode<"ISD::BRCOND" , SDTBrcond, [SDNPHasChain]>;
349 def brind : SDNode<"ISD::BRIND" , SDTBrind, [SDNPHasChain]>;
350 def br : SDNode<"ISD::BR" , SDTBr, [SDNPHasChain]>;
351 def ret : SDNode<"ISD::RET" , SDTNone, [SDNPHasChain]>;
352 def trap : SDNode<"ISD::TRAP" , SDTNone,
353 [SDNPHasChain, SDNPSideEffect]>;
355 def prefetch : SDNode<"ISD::PREFETCH" , STDPrefetch,
356 [SDNPHasChain, SDNPMayLoad, SDNPMayStore]>;
358 def membarrier : SDNode<"ISD::MEMBARRIER" , STDMemBarrier,
359 [SDNPHasChain, SDNPSideEffect]>;
361 def atomic_cmp_swap_8 : SDNode<"ISD::ATOMIC_CMP_SWAP_8" , STDAtomic3,
362 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
363 def atomic_load_add_8 : SDNode<"ISD::ATOMIC_LOAD_ADD_8" , STDAtomic2,
364 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
365 def atomic_swap_8 : SDNode<"ISD::ATOMIC_SWAP_8", STDAtomic2,
366 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
367 def atomic_load_sub_8 : SDNode<"ISD::ATOMIC_LOAD_SUB_8" , STDAtomic2,
368 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
369 def atomic_load_and_8 : SDNode<"ISD::ATOMIC_LOAD_AND_8" , STDAtomic2,
370 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
371 def atomic_load_or_8 : SDNode<"ISD::ATOMIC_LOAD_OR_8" , STDAtomic2,
372 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
373 def atomic_load_xor_8 : SDNode<"ISD::ATOMIC_LOAD_XOR_8" , STDAtomic2,
374 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
375 def atomic_load_nand_8: SDNode<"ISD::ATOMIC_LOAD_NAND_8", STDAtomic2,
376 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
377 def atomic_load_min_8 : SDNode<"ISD::ATOMIC_LOAD_MIN_8", STDAtomic2,
378 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
379 def atomic_load_max_8 : SDNode<"ISD::ATOMIC_LOAD_MAX_8", STDAtomic2,
380 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
381 def atomic_load_umin_8 : SDNode<"ISD::ATOMIC_LOAD_UMIN_8", STDAtomic2,
382 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
383 def atomic_load_umax_8 : SDNode<"ISD::ATOMIC_LOAD_UMAX_8", STDAtomic2,
384 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
385 def atomic_cmp_swap_16 : SDNode<"ISD::ATOMIC_CMP_SWAP_16" , STDAtomic3,
386 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
387 def atomic_load_add_16 : SDNode<"ISD::ATOMIC_LOAD_ADD_16" , STDAtomic2,
388 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
389 def atomic_swap_16 : SDNode<"ISD::ATOMIC_SWAP_16", STDAtomic2,
390 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
391 def atomic_load_sub_16 : SDNode<"ISD::ATOMIC_LOAD_SUB_16" , STDAtomic2,
392 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
393 def atomic_load_and_16 : SDNode<"ISD::ATOMIC_LOAD_AND_16" , STDAtomic2,
394 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
395 def atomic_load_or_16 : SDNode<"ISD::ATOMIC_LOAD_OR_16" , STDAtomic2,
396 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
397 def atomic_load_xor_16 : SDNode<"ISD::ATOMIC_LOAD_XOR_16" , STDAtomic2,
398 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
399 def atomic_load_nand_16: SDNode<"ISD::ATOMIC_LOAD_NAND_16", STDAtomic2,
400 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
401 def atomic_load_min_16 : SDNode<"ISD::ATOMIC_LOAD_MIN_16", STDAtomic2,
402 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
403 def atomic_load_max_16 : SDNode<"ISD::ATOMIC_LOAD_MAX_16", STDAtomic2,
404 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
405 def atomic_load_umin_16 : SDNode<"ISD::ATOMIC_LOAD_UMIN_16", STDAtomic2,
406 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
407 def atomic_load_umax_16 : SDNode<"ISD::ATOMIC_LOAD_UMAX_16", STDAtomic2,
408 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
409 def atomic_cmp_swap_32 : SDNode<"ISD::ATOMIC_CMP_SWAP_32" , STDAtomic3,
410 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
411 def atomic_load_add_32 : SDNode<"ISD::ATOMIC_LOAD_ADD_32" , STDAtomic2,
412 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
413 def atomic_swap_32 : SDNode<"ISD::ATOMIC_SWAP_32", STDAtomic2,
414 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
415 def atomic_load_sub_32 : SDNode<"ISD::ATOMIC_LOAD_SUB_32" , STDAtomic2,
416 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
417 def atomic_load_and_32 : SDNode<"ISD::ATOMIC_LOAD_AND_32" , STDAtomic2,
418 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
419 def atomic_load_or_32 : SDNode<"ISD::ATOMIC_LOAD_OR_32" , STDAtomic2,
420 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
421 def atomic_load_xor_32 : SDNode<"ISD::ATOMIC_LOAD_XOR_32" , STDAtomic2,
422 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
423 def atomic_load_nand_32: SDNode<"ISD::ATOMIC_LOAD_NAND_32", STDAtomic2,
424 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
425 def atomic_load_min_32 : SDNode<"ISD::ATOMIC_LOAD_MIN_32", STDAtomic2,
426 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
427 def atomic_load_max_32 : SDNode<"ISD::ATOMIC_LOAD_MAX_32", STDAtomic2,
428 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
429 def atomic_load_umin_32 : SDNode<"ISD::ATOMIC_LOAD_UMIN_32", STDAtomic2,
430 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
431 def atomic_load_umax_32 : SDNode<"ISD::ATOMIC_LOAD_UMAX_32", STDAtomic2,
432 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
433 def atomic_cmp_swap_64 : SDNode<"ISD::ATOMIC_CMP_SWAP_64" , STDAtomic3,
434 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
435 def atomic_load_add_64 : SDNode<"ISD::ATOMIC_LOAD_ADD_64" , STDAtomic2,
436 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
437 def atomic_swap_64 : SDNode<"ISD::ATOMIC_SWAP_64", STDAtomic2,
438 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
439 def atomic_load_sub_64 : SDNode<"ISD::ATOMIC_LOAD_SUB_64" , STDAtomic2,
440 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
441 def atomic_load_and_64 : SDNode<"ISD::ATOMIC_LOAD_AND_64" , STDAtomic2,
442 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
443 def atomic_load_or_64 : SDNode<"ISD::ATOMIC_LOAD_OR_64" , STDAtomic2,
444 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
445 def atomic_load_xor_64 : SDNode<"ISD::ATOMIC_LOAD_XOR_64" , STDAtomic2,
446 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
447 def atomic_load_nand_64: SDNode<"ISD::ATOMIC_LOAD_NAND_64", STDAtomic2,
448 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
449 def atomic_load_min_64 : SDNode<"ISD::ATOMIC_LOAD_MIN_64", STDAtomic2,
450 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
451 def atomic_load_max_64 : SDNode<"ISD::ATOMIC_LOAD_MAX_64", STDAtomic2,
452 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
453 def atomic_load_umin_64 : SDNode<"ISD::ATOMIC_LOAD_UMIN_64", STDAtomic2,
454 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
455 def atomic_load_umax_64 : SDNode<"ISD::ATOMIC_LOAD_UMAX_64", STDAtomic2,
456 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
458 // Do not use ld, st directly. Use load, extload, sextload, zextload, store,
459 // and truncst (see below).
460 def ld : SDNode<"ISD::LOAD" , SDTLoad,
461 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
462 def st : SDNode<"ISD::STORE" , SDTStore,
463 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
464 def ist : SDNode<"ISD::STORE" , SDTIStore,
465 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
467 def vector_shuffle : SDNode<"ISD::VECTOR_SHUFFLE", SDTVecShuffle, []>;
468 def build_vector : SDNode<"ISD::BUILD_VECTOR", SDTypeProfile<1, -1, []>, []>;
469 def scalar_to_vector : SDNode<"ISD::SCALAR_TO_VECTOR", SDTypeProfile<1, 1, []>,
471 def vector_extract : SDNode<"ISD::EXTRACT_VECTOR_ELT",
472 SDTypeProfile<1, 2, [SDTCisPtrTy<2>]>, []>;
473 def vector_insert : SDNode<"ISD::INSERT_VECTOR_ELT",
474 SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisPtrTy<3>]>, []>;
476 def extract_subreg : SDNode<"ISD::EXTRACT_SUBREG",
477 SDTypeProfile<1, 2, []>>;
478 def insert_subreg : SDNode<"ISD::INSERT_SUBREG",
479 SDTypeProfile<1, 3, []>>;
481 // Nodes for intrinsics, you should use the intrinsic itself and let tblgen use
482 // these internally. Don't reference these directly.
483 def intrinsic_void : SDNode<"ISD::INTRINSIC_VOID",
484 SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>,
486 def intrinsic_w_chain : SDNode<"ISD::INTRINSIC_W_CHAIN",
487 SDTypeProfile<1, -1, [SDTCisPtrTy<1>]>,
489 def intrinsic_wo_chain : SDNode<"ISD::INTRINSIC_WO_CHAIN",
490 SDTypeProfile<1, -1, [SDTCisPtrTy<1>]>, []>;
493 //===----------------------------------------------------------------------===//
494 // Selection DAG Condition Codes
496 class CondCode; // ISD::CondCode enums
497 def SETOEQ : CondCode; def SETOGT : CondCode;
498 def SETOGE : CondCode; def SETOLT : CondCode; def SETOLE : CondCode;
499 def SETONE : CondCode; def SETO : CondCode; def SETUO : CondCode;
500 def SETUEQ : CondCode; def SETUGT : CondCode; def SETUGE : CondCode;
501 def SETULT : CondCode; def SETULE : CondCode; def SETUNE : CondCode;
503 def SETEQ : CondCode; def SETGT : CondCode; def SETGE : CondCode;
504 def SETLT : CondCode; def SETLE : CondCode; def SETNE : CondCode;
507 //===----------------------------------------------------------------------===//
508 // Selection DAG Node Transformation Functions.
510 // This mechanism allows targets to manipulate nodes in the output DAG once a
511 // match has been formed. This is typically used to manipulate immediate
514 class SDNodeXForm<SDNode opc, code xformFunction> {
516 code XFormFunction = xformFunction;
519 def NOOP_SDNodeXForm : SDNodeXForm<imm, [{}]>;
522 //===----------------------------------------------------------------------===//
523 // Selection DAG Pattern Fragments.
525 // Pattern fragments are reusable chunks of dags that match specific things.
526 // They can take arguments and have C++ predicates that control whether they
527 // match. They are intended to make the patterns for common instructions more
528 // compact and readable.
531 /// PatFrag - Represents a pattern fragment. This can match something on the
532 /// DAG, frame a single node to multiply nested other fragments.
534 class PatFrag<dag ops, dag frag, code pred = [{}],
535 SDNodeXForm xform = NOOP_SDNodeXForm> {
538 code Predicate = pred;
539 SDNodeXForm OperandTransform = xform;
542 // PatLeaf's are pattern fragments that have no operands. This is just a helper
543 // to define immediates and other common things concisely.
544 class PatLeaf<dag frag, code pred = [{}], SDNodeXForm xform = NOOP_SDNodeXForm>
545 : PatFrag<(ops), frag, pred, xform>;
549 def vtInt : PatLeaf<(vt), [{ return N->getVT().isInteger(); }]>;
550 def vtFP : PatLeaf<(vt), [{ return N->getVT().isFloatingPoint(); }]>;
552 def immAllOnes : PatLeaf<(imm), [{ return N->isAllOnesValue(); }]>;
553 def immAllOnesV: PatLeaf<(build_vector), [{
554 return ISD::isBuildVectorAllOnes(N);
556 def immAllOnesV_bc: PatLeaf<(bitconvert), [{
557 return ISD::isBuildVectorAllOnes(N);
559 def immAllZerosV: PatLeaf<(build_vector), [{
560 return ISD::isBuildVectorAllZeros(N);
562 def immAllZerosV_bc: PatLeaf<(bitconvert), [{
563 return ISD::isBuildVectorAllZeros(N);
568 // Other helper fragments.
569 def not : PatFrag<(ops node:$in), (xor node:$in, immAllOnes)>;
570 def vnot : PatFrag<(ops node:$in), (xor node:$in, immAllOnesV)>;
571 def vnot_conv : PatFrag<(ops node:$in), (xor node:$in, immAllOnesV_bc)>;
572 def ineg : PatFrag<(ops node:$in), (sub 0, node:$in)>;
575 def load : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
576 LoadSDNode *LD = cast<LoadSDNode>(N);
577 return LD->getExtensionType() == ISD::NON_EXTLOAD &&
578 LD->getAddressingMode() == ISD::UNINDEXED;
581 // extending load fragments.
582 def extloadi1 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
583 LoadSDNode *LD = cast<LoadSDNode>(N);
584 return LD->getExtensionType() == ISD::EXTLOAD &&
585 LD->getAddressingMode() == ISD::UNINDEXED &&
586 LD->getMemoryVT() == MVT::i1;
588 def extloadi8 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
589 LoadSDNode *LD = cast<LoadSDNode>(N);
590 return LD->getExtensionType() == ISD::EXTLOAD &&
591 LD->getAddressingMode() == ISD::UNINDEXED &&
592 LD->getMemoryVT() == MVT::i8;
594 def extloadi16 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
595 LoadSDNode *LD = cast<LoadSDNode>(N);
596 return LD->getExtensionType() == ISD::EXTLOAD &&
597 LD->getAddressingMode() == ISD::UNINDEXED &&
598 LD->getMemoryVT() == MVT::i16;
600 def extloadi32 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
601 LoadSDNode *LD = cast<LoadSDNode>(N);
602 return LD->getExtensionType() == ISD::EXTLOAD &&
603 LD->getAddressingMode() == ISD::UNINDEXED &&
604 LD->getMemoryVT() == MVT::i32;
606 def extloadf32 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
607 LoadSDNode *LD = cast<LoadSDNode>(N);
608 return LD->getExtensionType() == ISD::EXTLOAD &&
609 LD->getAddressingMode() == ISD::UNINDEXED &&
610 LD->getMemoryVT() == MVT::f32;
612 def extloadf64 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
613 LoadSDNode *LD = cast<LoadSDNode>(N);
614 return LD->getExtensionType() == ISD::EXTLOAD &&
615 LD->getAddressingMode() == ISD::UNINDEXED &&
616 LD->getMemoryVT() == MVT::f64;
619 def sextloadi1 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
620 LoadSDNode *LD = cast<LoadSDNode>(N);
621 return LD->getExtensionType() == ISD::SEXTLOAD &&
622 LD->getAddressingMode() == ISD::UNINDEXED &&
623 LD->getMemoryVT() == MVT::i1;
625 def sextloadi8 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
626 LoadSDNode *LD = cast<LoadSDNode>(N);
627 return LD->getExtensionType() == ISD::SEXTLOAD &&
628 LD->getAddressingMode() == ISD::UNINDEXED &&
629 LD->getMemoryVT() == MVT::i8;
631 def sextloadi16 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
632 LoadSDNode *LD = cast<LoadSDNode>(N);
633 return LD->getExtensionType() == ISD::SEXTLOAD &&
634 LD->getAddressingMode() == ISD::UNINDEXED &&
635 LD->getMemoryVT() == MVT::i16;
637 def sextloadi32 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
638 LoadSDNode *LD = cast<LoadSDNode>(N);
639 return LD->getExtensionType() == ISD::SEXTLOAD &&
640 LD->getAddressingMode() == ISD::UNINDEXED &&
641 LD->getMemoryVT() == MVT::i32;
644 def zextloadi1 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
645 LoadSDNode *LD = cast<LoadSDNode>(N);
646 return LD->getExtensionType() == ISD::ZEXTLOAD &&
647 LD->getAddressingMode() == ISD::UNINDEXED &&
648 LD->getMemoryVT() == MVT::i1;
650 def zextloadi8 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
651 LoadSDNode *LD = cast<LoadSDNode>(N);
652 return LD->getExtensionType() == ISD::ZEXTLOAD &&
653 LD->getAddressingMode() == ISD::UNINDEXED &&
654 LD->getMemoryVT() == MVT::i8;
656 def zextloadi16 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
657 LoadSDNode *LD = cast<LoadSDNode>(N);
658 return LD->getExtensionType() == ISD::ZEXTLOAD &&
659 LD->getAddressingMode() == ISD::UNINDEXED &&
660 LD->getMemoryVT() == MVT::i16;
662 def zextloadi32 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
663 LoadSDNode *LD = cast<LoadSDNode>(N);
664 return LD->getExtensionType() == ISD::ZEXTLOAD &&
665 LD->getAddressingMode() == ISD::UNINDEXED &&
666 LD->getMemoryVT() == MVT::i32;
670 def store : PatFrag<(ops node:$val, node:$ptr),
671 (st node:$val, node:$ptr), [{
672 StoreSDNode *ST = cast<StoreSDNode>(N);
673 return !ST->isTruncatingStore() &&
674 ST->getAddressingMode() == ISD::UNINDEXED;
677 // truncstore fragments.
678 def truncstorei8 : PatFrag<(ops node:$val, node:$ptr),
679 (st node:$val, node:$ptr), [{
680 StoreSDNode *ST = cast<StoreSDNode>(N);
681 return ST->isTruncatingStore() && ST->getMemoryVT() == MVT::i8 &&
682 ST->getAddressingMode() == ISD::UNINDEXED;
684 def truncstorei16 : PatFrag<(ops node:$val, node:$ptr),
685 (st node:$val, node:$ptr), [{
686 StoreSDNode *ST = cast<StoreSDNode>(N);
687 return ST->isTruncatingStore() && ST->getMemoryVT() == MVT::i16 &&
688 ST->getAddressingMode() == ISD::UNINDEXED;
690 def truncstorei32 : PatFrag<(ops node:$val, node:$ptr),
691 (st node:$val, node:$ptr), [{
692 StoreSDNode *ST = cast<StoreSDNode>(N);
693 return ST->isTruncatingStore() && ST->getMemoryVT() == MVT::i32 &&
694 ST->getAddressingMode() == ISD::UNINDEXED;
696 def truncstoref32 : PatFrag<(ops node:$val, node:$ptr),
697 (st node:$val, node:$ptr), [{
698 StoreSDNode *ST = cast<StoreSDNode>(N);
699 return ST->isTruncatingStore() && ST->getMemoryVT() == MVT::f32 &&
700 ST->getAddressingMode() == ISD::UNINDEXED;
702 def truncstoref64 : PatFrag<(ops node:$val, node:$ptr),
703 (st node:$val, node:$ptr), [{
704 StoreSDNode *ST = cast<StoreSDNode>(N);
705 return ST->isTruncatingStore() && ST->getMemoryVT() == MVT::f64 &&
706 ST->getAddressingMode() == ISD::UNINDEXED;
709 // indexed store fragments.
710 def pre_store : PatFrag<(ops node:$val, node:$base, node:$offset),
711 (ist node:$val, node:$base, node:$offset), [{
712 StoreSDNode *ST = cast<StoreSDNode>(N);
713 ISD::MemIndexedMode AM = ST->getAddressingMode();
714 return (AM == ISD::PRE_INC || AM == ISD::PRE_DEC) &&
715 !ST->isTruncatingStore();
718 def pre_truncsti1 : PatFrag<(ops node:$val, node:$base, node:$offset),
719 (ist node:$val, node:$base, node:$offset), [{
720 StoreSDNode *ST = cast<StoreSDNode>(N);
721 ISD::MemIndexedMode AM = ST->getAddressingMode();
722 return (AM == ISD::PRE_INC || AM == ISD::PRE_DEC) &&
723 ST->isTruncatingStore() && ST->getMemoryVT() == MVT::i1;
725 def pre_truncsti8 : PatFrag<(ops node:$val, node:$base, node:$offset),
726 (ist node:$val, node:$base, node:$offset), [{
727 StoreSDNode *ST = cast<StoreSDNode>(N);
728 ISD::MemIndexedMode AM = ST->getAddressingMode();
729 return (AM == ISD::PRE_INC || AM == ISD::PRE_DEC) &&
730 ST->isTruncatingStore() && ST->getMemoryVT() == MVT::i8;
732 def pre_truncsti16 : PatFrag<(ops node:$val, node:$base, node:$offset),
733 (ist node:$val, node:$base, node:$offset), [{
734 StoreSDNode *ST = cast<StoreSDNode>(N);
735 ISD::MemIndexedMode AM = ST->getAddressingMode();
736 return (AM == ISD::PRE_INC || AM == ISD::PRE_DEC) &&
737 ST->isTruncatingStore() && ST->getMemoryVT() == MVT::i16;
739 def pre_truncsti32 : PatFrag<(ops node:$val, node:$base, node:$offset),
740 (ist node:$val, node:$base, node:$offset), [{
741 StoreSDNode *ST = cast<StoreSDNode>(N);
742 ISD::MemIndexedMode AM = ST->getAddressingMode();
743 return (AM == ISD::PRE_INC || AM == ISD::PRE_DEC) &&
744 ST->isTruncatingStore() && ST->getMemoryVT() == MVT::i32;
746 def pre_truncstf32 : PatFrag<(ops node:$val, node:$base, node:$offset),
747 (ist node:$val, node:$base, node:$offset), [{
748 StoreSDNode *ST = cast<StoreSDNode>(N);
749 ISD::MemIndexedMode AM = ST->getAddressingMode();
750 return (AM == ISD::PRE_INC || AM == ISD::PRE_DEC) &&
751 ST->isTruncatingStore() && ST->getMemoryVT() == MVT::f32;
754 def post_store : PatFrag<(ops node:$val, node:$ptr, node:$offset),
755 (ist node:$val, node:$ptr, node:$offset), [{
756 StoreSDNode *ST = cast<StoreSDNode>(N);
757 ISD::MemIndexedMode AM = ST->getAddressingMode();
758 return !ST->isTruncatingStore() &&
759 (AM == ISD::POST_INC || AM == ISD::POST_DEC);
762 def post_truncsti1 : PatFrag<(ops node:$val, node:$base, node:$offset),
763 (ist node:$val, node:$base, node:$offset), [{
764 StoreSDNode *ST = cast<StoreSDNode>(N);
765 ISD::MemIndexedMode AM = ST->getAddressingMode();
766 return (AM == ISD::POST_INC || AM == ISD::POST_DEC) &&
767 ST->isTruncatingStore() && ST->getMemoryVT() == MVT::i1;
769 def post_truncsti8 : PatFrag<(ops node:$val, node:$base, node:$offset),
770 (ist node:$val, node:$base, node:$offset), [{
771 StoreSDNode *ST = cast<StoreSDNode>(N);
772 ISD::MemIndexedMode AM = ST->getAddressingMode();
773 return (AM == ISD::POST_INC || AM == ISD::POST_DEC) &&
774 ST->isTruncatingStore() && ST->getMemoryVT() == MVT::i8;
776 def post_truncsti16 : PatFrag<(ops node:$val, node:$base, node:$offset),
777 (ist node:$val, node:$base, node:$offset), [{
778 StoreSDNode *ST = cast<StoreSDNode>(N);
779 ISD::MemIndexedMode AM = ST->getAddressingMode();
780 return (AM == ISD::POST_INC || AM == ISD::POST_DEC) &&
781 ST->isTruncatingStore() && ST->getMemoryVT() == MVT::i16;
783 def post_truncsti32 : PatFrag<(ops node:$val, node:$base, node:$offset),
784 (ist node:$val, node:$base, node:$offset), [{
785 StoreSDNode *ST = cast<StoreSDNode>(N);
786 ISD::MemIndexedMode AM = ST->getAddressingMode();
787 return (AM == ISD::POST_INC || AM == ISD::POST_DEC) &&
788 ST->isTruncatingStore() && ST->getMemoryVT() == MVT::i32;
790 def post_truncstf32 : PatFrag<(ops node:$val, node:$base, node:$offset),
791 (ist node:$val, node:$base, node:$offset), [{
792 StoreSDNode *ST = cast<StoreSDNode>(N);
793 ISD::MemIndexedMode AM = ST->getAddressingMode();
794 return (AM == ISD::POST_INC || AM == ISD::POST_DEC) &&
795 ST->isTruncatingStore() && ST->getMemoryVT() == MVT::f32;
798 // setcc convenience fragments.
799 def setoeq : PatFrag<(ops node:$lhs, node:$rhs),
800 (setcc node:$lhs, node:$rhs, SETOEQ)>;
801 def setogt : PatFrag<(ops node:$lhs, node:$rhs),
802 (setcc node:$lhs, node:$rhs, SETOGT)>;
803 def setoge : PatFrag<(ops node:$lhs, node:$rhs),
804 (setcc node:$lhs, node:$rhs, SETOGE)>;
805 def setolt : PatFrag<(ops node:$lhs, node:$rhs),
806 (setcc node:$lhs, node:$rhs, SETOLT)>;
807 def setole : PatFrag<(ops node:$lhs, node:$rhs),
808 (setcc node:$lhs, node:$rhs, SETOLE)>;
809 def setone : PatFrag<(ops node:$lhs, node:$rhs),
810 (setcc node:$lhs, node:$rhs, SETONE)>;
811 def seto : PatFrag<(ops node:$lhs, node:$rhs),
812 (setcc node:$lhs, node:$rhs, SETO)>;
813 def setuo : PatFrag<(ops node:$lhs, node:$rhs),
814 (setcc node:$lhs, node:$rhs, SETUO)>;
815 def setueq : PatFrag<(ops node:$lhs, node:$rhs),
816 (setcc node:$lhs, node:$rhs, SETUEQ)>;
817 def setugt : PatFrag<(ops node:$lhs, node:$rhs),
818 (setcc node:$lhs, node:$rhs, SETUGT)>;
819 def setuge : PatFrag<(ops node:$lhs, node:$rhs),
820 (setcc node:$lhs, node:$rhs, SETUGE)>;
821 def setult : PatFrag<(ops node:$lhs, node:$rhs),
822 (setcc node:$lhs, node:$rhs, SETULT)>;
823 def setule : PatFrag<(ops node:$lhs, node:$rhs),
824 (setcc node:$lhs, node:$rhs, SETULE)>;
825 def setune : PatFrag<(ops node:$lhs, node:$rhs),
826 (setcc node:$lhs, node:$rhs, SETUNE)>;
827 def seteq : PatFrag<(ops node:$lhs, node:$rhs),
828 (setcc node:$lhs, node:$rhs, SETEQ)>;
829 def setgt : PatFrag<(ops node:$lhs, node:$rhs),
830 (setcc node:$lhs, node:$rhs, SETGT)>;
831 def setge : PatFrag<(ops node:$lhs, node:$rhs),
832 (setcc node:$lhs, node:$rhs, SETGE)>;
833 def setlt : PatFrag<(ops node:$lhs, node:$rhs),
834 (setcc node:$lhs, node:$rhs, SETLT)>;
835 def setle : PatFrag<(ops node:$lhs, node:$rhs),
836 (setcc node:$lhs, node:$rhs, SETLE)>;
837 def setne : PatFrag<(ops node:$lhs, node:$rhs),
838 (setcc node:$lhs, node:$rhs, SETNE)>;
840 //===----------------------------------------------------------------------===//
841 // Selection DAG Pattern Support.
843 // Patterns are what are actually matched against the target-flavored
844 // instruction selection DAG. Instructions defined by the target implicitly
845 // define patterns in most cases, but patterns can also be explicitly added when
846 // an operation is defined by a sequence of instructions (e.g. loading a large
847 // immediate value on RISC targets that do not support immediates as large as
851 class Pattern<dag patternToMatch, list<dag> resultInstrs> {
852 dag PatternToMatch = patternToMatch;
853 list<dag> ResultInstrs = resultInstrs;
854 list<Predicate> Predicates = []; // See class Instruction in Target.td.
855 int AddedComplexity = 0; // See class Instruction in Target.td.
858 // Pat - A simple (but common) form of a pattern, which produces a simple result
859 // not needing a full list.
860 class Pat<dag pattern, dag result> : Pattern<pattern, [result]>;
862 //===----------------------------------------------------------------------===//
863 // Complex pattern definitions.
867 // Pass the parent Operand as root to CP function rather
868 // than the root of the sub-DAG
869 def CPAttrParentAsRoot : CPAttribute;
871 // Complex patterns, e.g. X86 addressing mode, requires pattern matching code
872 // in C++. NumOperands is the number of operands returned by the select function;
873 // SelectFunc is the name of the function used to pattern match the max. pattern;
874 // RootNodes are the list of possible root nodes of the sub-dags to match.
875 // e.g. X86 addressing mode - def addr : ComplexPattern<4, "SelectAddr", [add]>;
877 class ComplexPattern<ValueType ty, int numops, string fn,
878 list<SDNode> roots = [], list<SDNodeProperty> props = [],
879 list<CPAttribute> attrs = []> {
881 int NumOperands = numops;
882 string SelectFunc = fn;
883 list<SDNode> RootNodes = roots;
884 list<SDNodeProperty> Properties = props;
885 list<CPAttribute> Attributes = attrs;
888 //===----------------------------------------------------------------------===//
891 def SDT_dwarf_loc : SDTypeProfile<0, 3,
892 [SDTCisInt<0>, SDTCisInt<1>, SDTCisInt<2>]>;
893 def dwarf_loc : SDNode<"ISD::DEBUG_LOC", SDT_dwarf_loc,[SDNPHasChain]>;