1 //===- TargetSelectionDAG.td - Common code for DAG isels ---*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the target-independent interfaces used by SelectionDAG
11 // instruction selection generators.
13 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
16 // Selection DAG Type Constraint definitions.
18 // Note that the semantics of these constraints are hard coded into tblgen. To
19 // modify or add constraints, you have to hack tblgen.
22 class SDTypeConstraint<int opnum> {
23 int OperandNum = opnum;
26 // SDTCisVT - The specified operand has exactly this VT.
27 class SDTCisVT<int OpNum, ValueType vt> : SDTypeConstraint<OpNum> {
31 class SDTCisPtrTy<int OpNum> : SDTypeConstraint<OpNum>;
33 // SDTCisInt - The specified operand is has integer type.
34 class SDTCisInt<int OpNum> : SDTypeConstraint<OpNum>;
36 // SDTCisFP - The specified operand is has floating point type.
37 class SDTCisFP<int OpNum> : SDTypeConstraint<OpNum>;
39 // SDTCisSameAs - The two specified operands have identical types.
40 class SDTCisSameAs<int OpNum, int OtherOp> : SDTypeConstraint<OpNum> {
41 int OtherOperandNum = OtherOp;
44 // SDTCisVTSmallerThanOp - The specified operand is a VT SDNode, and its type is
45 // smaller than the 'Other' operand.
46 class SDTCisVTSmallerThanOp<int OpNum, int OtherOp> : SDTypeConstraint<OpNum> {
47 int OtherOperandNum = OtherOp;
50 class SDTCisOpSmallerThanOp<int SmallOp, int BigOp> : SDTypeConstraint<SmallOp>{
51 int BigOperandNum = BigOp;
54 /// SDTCisIntVectorOfSameSize - This indicates that ThisOp and OtherOp are
55 /// vector types, and that ThisOp is the result of
56 /// MVT::getIntVectorWithNumElements with the number of elements
58 class SDTCisIntVectorOfSameSize<int ThisOp, int OtherOp>
59 : SDTypeConstraint<ThisOp> {
60 int OtherOpNum = OtherOp;
63 /// SDTCisEltOfVec - This indicates that ThisOp is a scalar type of the same
64 /// type as the element type of OtherOp, which is a vector type.
65 class SDTCisEltOfVec<int ThisOp, int OtherOp>
66 : SDTypeConstraint<ThisOp> {
67 int OtherOpNum = OtherOp;
70 //===----------------------------------------------------------------------===//
71 // Selection DAG Type Profile definitions.
73 // These use the constraints defined above to describe the type requirements of
74 // the various nodes. These are not hard coded into tblgen, allowing targets to
75 // add their own if needed.
78 // SDTypeProfile - This profile describes the type requirements of a Selection
80 class SDTypeProfile<int numresults, int numoperands,
81 list<SDTypeConstraint> constraints> {
82 int NumResults = numresults;
83 int NumOperands = numoperands;
84 list<SDTypeConstraint> Constraints = constraints;
88 def SDTIntLeaf: SDTypeProfile<1, 0, [SDTCisInt<0>]>; // for 'imm'.
89 def SDTFPLeaf : SDTypeProfile<1, 0, [SDTCisFP<0>]>; // for 'fpimm'.
90 def SDTPtrLeaf: SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>; // for '&g'.
91 def SDTOther : SDTypeProfile<1, 0, [SDTCisVT<0, OtherVT>]>; // for 'vt'.
92 def SDTUNDEF : SDTypeProfile<1, 0, []>; // for 'undef'.
93 def SDTUnaryOp : SDTypeProfile<1, 1, []>; // bitconvert
95 def SDTIntBinOp : SDTypeProfile<1, 2, [ // add, and, or, xor, udiv, etc.
96 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<0>
98 def SDTIntShiftOp : SDTypeProfile<1, 2, [ // shl, sra, srl
99 SDTCisSameAs<0, 1>, SDTCisInt<0>, SDTCisInt<2>
101 def SDTFPBinOp : SDTypeProfile<1, 2, [ // fadd, fmul, etc.
102 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisFP<0>
104 def SDTFPSignOp : SDTypeProfile<1, 2, [ // fcopysign.
105 SDTCisSameAs<0, 1>, SDTCisFP<0>, SDTCisFP<2>
107 def SDTFPTernaryOp : SDTypeProfile<1, 3, [ // fmadd, fnmsub, etc.
108 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>, SDTCisFP<0>
110 def SDTIntUnaryOp : SDTypeProfile<1, 1, [ // ctlz
111 SDTCisSameAs<0, 1>, SDTCisInt<0>
113 def SDTIntExtendOp : SDTypeProfile<1, 1, [ // sext, zext, anyext
114 SDTCisInt<0>, SDTCisInt<1>, SDTCisOpSmallerThanOp<1, 0>
116 def SDTIntTruncOp : SDTypeProfile<1, 1, [ // trunc
117 SDTCisInt<0>, SDTCisInt<1>, SDTCisOpSmallerThanOp<0, 1>
119 def SDTFPUnaryOp : SDTypeProfile<1, 1, [ // fneg, fsqrt, etc
120 SDTCisSameAs<0, 1>, SDTCisFP<0>
122 def SDTFPRoundOp : SDTypeProfile<1, 1, [ // fround
123 SDTCisFP<0>, SDTCisFP<1>, SDTCisOpSmallerThanOp<0, 1>
125 def SDTFPExtendOp : SDTypeProfile<1, 1, [ // fextend
126 SDTCisFP<0>, SDTCisFP<1>, SDTCisOpSmallerThanOp<1, 0>
128 def SDTIntToFPOp : SDTypeProfile<1, 1, [ // [su]int_to_fp
129 SDTCisFP<0>, SDTCisInt<1>
131 def SDTFPToIntOp : SDTypeProfile<1, 1, [ // fp_to_[su]int
132 SDTCisInt<0>, SDTCisFP<1>
134 def SDTExtInreg : SDTypeProfile<1, 2, [ // sext_inreg
135 SDTCisSameAs<0, 1>, SDTCisInt<0>, SDTCisVT<2, OtherVT>,
136 SDTCisVTSmallerThanOp<2, 1>
139 def SDTSetCC : SDTypeProfile<1, 3, [ // setcc
140 SDTCisInt<0>, SDTCisSameAs<1, 2>, SDTCisVT<3, OtherVT>
143 def SDTSelect : SDTypeProfile<1, 3, [ // select
144 SDTCisInt<1>, SDTCisSameAs<0, 2>, SDTCisSameAs<2, 3>
147 def SDTSelectCC : SDTypeProfile<1, 5, [ // select_cc
148 SDTCisSameAs<1, 2>, SDTCisSameAs<3, 4>, SDTCisSameAs<0, 3>,
152 def SDTBr : SDTypeProfile<0, 1, [ // br
156 def SDTBrcond : SDTypeProfile<0, 2, [ // brcond
157 SDTCisInt<0>, SDTCisVT<1, OtherVT>
160 def SDTBrind : SDTypeProfile<0, 1, [ // brind
164 def SDTNone : SDTypeProfile<0, 0, []>; // ret, trap
166 def SDTLoad : SDTypeProfile<1, 1, [ // load
170 def SDTStore : SDTypeProfile<0, 2, [ // store
174 def SDTIStore : SDTypeProfile<1, 3, [ // indexed store
175 SDTCisSameAs<0, 2>, SDTCisPtrTy<0>, SDTCisPtrTy<3>
178 def SDTVecShuffle : SDTypeProfile<1, 3, [
179 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisIntVectorOfSameSize<3, 0>
181 def SDTVecExtract : SDTypeProfile<1, 2, [ // vector extract
182 SDTCisEltOfVec<0, 1>, SDTCisPtrTy<2>
184 def SDTVecInsert : SDTypeProfile<1, 3, [ // vector insert
185 SDTCisEltOfVec<2, 1>, SDTCisSameAs<0, 1>, SDTCisPtrTy<3>
188 def STDPrefetch : SDTypeProfile<0, 3, [ // prefetch
189 SDTCisPtrTy<0>, SDTCisSameAs<1, 2>, SDTCisInt<1>
192 def STDMemBarrier : SDTypeProfile<0, 5, [ // memory barier
193 SDTCisSameAs<0,1>, SDTCisSameAs<0,2>, SDTCisSameAs<0,3>, SDTCisSameAs<0,4>,
196 def STDAtomic3 : SDTypeProfile<1, 3, [
197 SDTCisSameAs<0,2>, SDTCisSameAs<0,3>, SDTCisInt<0>, SDTCisPtrTy<1>
199 def STDAtomic2 : SDTypeProfile<1, 2, [
200 SDTCisSameAs<0,2>, SDTCisInt<0>, SDTCisPtrTy<1>
203 class SDCallSeqStart<list<SDTypeConstraint> constraints> :
204 SDTypeProfile<0, 1, constraints>;
205 class SDCallSeqEnd<list<SDTypeConstraint> constraints> :
206 SDTypeProfile<0, 2, constraints>;
208 //===----------------------------------------------------------------------===//
209 // Selection DAG Node Properties.
211 // Note: These are hard coded into tblgen.
213 class SDNodeProperty;
214 def SDNPCommutative : SDNodeProperty; // X op Y == Y op X
215 def SDNPAssociative : SDNodeProperty; // (X op Y) op Z == X op (Y op Z)
216 def SDNPHasChain : SDNodeProperty; // R/W chain operand and result
217 def SDNPOutFlag : SDNodeProperty; // Write a flag result
218 def SDNPInFlag : SDNodeProperty; // Read a flag operand
219 def SDNPOptInFlag : SDNodeProperty; // Optionally read a flag operand
220 def SDNPMayStore : SDNodeProperty; // May write to memory, sets 'mayStore'.
221 def SDNPMayLoad : SDNodeProperty; // May read memory, sets 'mayLoad'.
222 def SDNPSideEffect : SDNodeProperty; // Sets 'HasUnmodelledSideEffects'.
224 //===----------------------------------------------------------------------===//
225 // Selection DAG Node definitions.
227 class SDNode<string opcode, SDTypeProfile typeprof,
228 list<SDNodeProperty> props = [], string sdclass = "SDNode"> {
229 string Opcode = opcode;
230 string SDClass = sdclass;
231 list<SDNodeProperty> Properties = props;
232 SDTypeProfile TypeProfile = typeprof;
241 def imm : SDNode<"ISD::Constant" , SDTIntLeaf , [], "ConstantSDNode">;
242 def fpimm : SDNode<"ISD::ConstantFP", SDTFPLeaf , [], "ConstantFPSDNode">;
243 def vt : SDNode<"ISD::VALUETYPE" , SDTOther , [], "VTSDNode">;
244 def bb : SDNode<"ISD::BasicBlock", SDTOther , [], "BasicBlockSDNode">;
245 def cond : SDNode<"ISD::CONDCODE" , SDTOther , [], "CondCodeSDNode">;
246 def undef : SDNode<"ISD::UNDEF" , SDTUNDEF , []>;
247 def globaladdr : SDNode<"ISD::GlobalAddress", SDTPtrLeaf, [],
248 "GlobalAddressSDNode">;
249 def tglobaladdr : SDNode<"ISD::TargetGlobalAddress", SDTPtrLeaf, [],
250 "GlobalAddressSDNode">;
251 def globaltlsaddr : SDNode<"ISD::GlobalTLSAddress", SDTPtrLeaf, [],
252 "GlobalAddressSDNode">;
253 def tglobaltlsaddr : SDNode<"ISD::TargetGlobalTLSAddress", SDTPtrLeaf, [],
254 "GlobalAddressSDNode">;
255 def constpool : SDNode<"ISD::ConstantPool", SDTPtrLeaf, [],
256 "ConstantPoolSDNode">;
257 def tconstpool : SDNode<"ISD::TargetConstantPool", SDTPtrLeaf, [],
258 "ConstantPoolSDNode">;
259 def jumptable : SDNode<"ISD::JumpTable", SDTPtrLeaf, [],
261 def tjumptable : SDNode<"ISD::TargetJumpTable", SDTPtrLeaf, [],
263 def frameindex : SDNode<"ISD::FrameIndex", SDTPtrLeaf, [],
265 def tframeindex : SDNode<"ISD::TargetFrameIndex", SDTPtrLeaf, [],
267 def externalsym : SDNode<"ISD::ExternalSymbol", SDTPtrLeaf, [],
268 "ExternalSymbolSDNode">;
269 def texternalsym: SDNode<"ISD::TargetExternalSymbol", SDTPtrLeaf, [],
270 "ExternalSymbolSDNode">;
272 def add : SDNode<"ISD::ADD" , SDTIntBinOp ,
273 [SDNPCommutative, SDNPAssociative]>;
274 def sub : SDNode<"ISD::SUB" , SDTIntBinOp>;
275 def mul : SDNode<"ISD::MUL" , SDTIntBinOp,
276 [SDNPCommutative, SDNPAssociative]>;
277 def mulhs : SDNode<"ISD::MULHS" , SDTIntBinOp, [SDNPCommutative]>;
278 def mulhu : SDNode<"ISD::MULHU" , SDTIntBinOp, [SDNPCommutative]>;
279 def sdiv : SDNode<"ISD::SDIV" , SDTIntBinOp>;
280 def udiv : SDNode<"ISD::UDIV" , SDTIntBinOp>;
281 def srem : SDNode<"ISD::SREM" , SDTIntBinOp>;
282 def urem : SDNode<"ISD::UREM" , SDTIntBinOp>;
283 def srl : SDNode<"ISD::SRL" , SDTIntShiftOp>;
284 def sra : SDNode<"ISD::SRA" , SDTIntShiftOp>;
285 def shl : SDNode<"ISD::SHL" , SDTIntShiftOp>;
286 def rotl : SDNode<"ISD::ROTL" , SDTIntShiftOp>;
287 def rotr : SDNode<"ISD::ROTR" , SDTIntShiftOp>;
288 def and : SDNode<"ISD::AND" , SDTIntBinOp,
289 [SDNPCommutative, SDNPAssociative]>;
290 def or : SDNode<"ISD::OR" , SDTIntBinOp,
291 [SDNPCommutative, SDNPAssociative]>;
292 def xor : SDNode<"ISD::XOR" , SDTIntBinOp,
293 [SDNPCommutative, SDNPAssociative]>;
294 def addc : SDNode<"ISD::ADDC" , SDTIntBinOp,
295 [SDNPCommutative, SDNPOutFlag]>;
296 def adde : SDNode<"ISD::ADDE" , SDTIntBinOp,
297 [SDNPCommutative, SDNPOutFlag, SDNPInFlag]>;
298 def subc : SDNode<"ISD::SUBC" , SDTIntBinOp,
300 def sube : SDNode<"ISD::SUBE" , SDTIntBinOp,
301 [SDNPOutFlag, SDNPInFlag]>;
303 def sext_inreg : SDNode<"ISD::SIGN_EXTEND_INREG", SDTExtInreg>;
304 def bswap : SDNode<"ISD::BSWAP" , SDTIntUnaryOp>;
305 def ctlz : SDNode<"ISD::CTLZ" , SDTIntUnaryOp>;
306 def cttz : SDNode<"ISD::CTTZ" , SDTIntUnaryOp>;
307 def ctpop : SDNode<"ISD::CTPOP" , SDTIntUnaryOp>;
308 def sext : SDNode<"ISD::SIGN_EXTEND", SDTIntExtendOp>;
309 def zext : SDNode<"ISD::ZERO_EXTEND", SDTIntExtendOp>;
310 def anyext : SDNode<"ISD::ANY_EXTEND" , SDTIntExtendOp>;
311 def trunc : SDNode<"ISD::TRUNCATE" , SDTIntTruncOp>;
312 def bitconvert : SDNode<"ISD::BIT_CONVERT", SDTUnaryOp>;
313 def extractelt : SDNode<"ISD::EXTRACT_VECTOR_ELT", SDTVecExtract>;
314 def insertelt : SDNode<"ISD::INSERT_VECTOR_ELT", SDTVecInsert>;
317 def fadd : SDNode<"ISD::FADD" , SDTFPBinOp, [SDNPCommutative]>;
318 def fsub : SDNode<"ISD::FSUB" , SDTFPBinOp>;
319 def fmul : SDNode<"ISD::FMUL" , SDTFPBinOp, [SDNPCommutative]>;
320 def fdiv : SDNode<"ISD::FDIV" , SDTFPBinOp>;
321 def frem : SDNode<"ISD::FREM" , SDTFPBinOp>;
322 def fabs : SDNode<"ISD::FABS" , SDTFPUnaryOp>;
323 def fneg : SDNode<"ISD::FNEG" , SDTFPUnaryOp>;
324 def fsqrt : SDNode<"ISD::FSQRT" , SDTFPUnaryOp>;
325 def fsin : SDNode<"ISD::FSIN" , SDTFPUnaryOp>;
326 def fcos : SDNode<"ISD::FCOS" , SDTFPUnaryOp>;
328 def fround : SDNode<"ISD::FP_ROUND" , SDTFPRoundOp>;
329 def fextend : SDNode<"ISD::FP_EXTEND" , SDTFPExtendOp>;
330 def fcopysign : SDNode<"ISD::FCOPYSIGN" , SDTFPSignOp>;
332 def sint_to_fp : SDNode<"ISD::SINT_TO_FP" , SDTIntToFPOp>;
333 def uint_to_fp : SDNode<"ISD::UINT_TO_FP" , SDTIntToFPOp>;
334 def fp_to_sint : SDNode<"ISD::FP_TO_SINT" , SDTFPToIntOp>;
335 def fp_to_uint : SDNode<"ISD::FP_TO_UINT" , SDTFPToIntOp>;
337 def setcc : SDNode<"ISD::SETCC" , SDTSetCC>;
338 def select : SDNode<"ISD::SELECT" , SDTSelect>;
339 def selectcc : SDNode<"ISD::SELECT_CC" , SDTSelectCC>;
340 def vsetcc : SDNode<"ISD::VSETCC" , SDTSetCC>;
342 def brcond : SDNode<"ISD::BRCOND" , SDTBrcond, [SDNPHasChain]>;
343 def brind : SDNode<"ISD::BRIND" , SDTBrind, [SDNPHasChain]>;
344 def br : SDNode<"ISD::BR" , SDTBr, [SDNPHasChain]>;
345 def ret : SDNode<"ISD::RET" , SDTNone, [SDNPHasChain]>;
346 def trap : SDNode<"ISD::TRAP" , SDTNone,
347 [SDNPHasChain, SDNPSideEffect]>;
349 def prefetch : SDNode<"ISD::PREFETCH" , STDPrefetch,
350 [SDNPHasChain, SDNPMayLoad, SDNPMayStore]>;
352 def membarrier : SDNode<"ISD::MEMBARRIER" , STDMemBarrier,
353 [SDNPHasChain, SDNPSideEffect]>;
355 // Do not use atomic_* directly, use atomic_*_size (see below)
356 def atomic_lcs : SDNode<"ISD::ATOMIC_LCS" , STDAtomic3,
357 [SDNPHasChain, SDNPMayStore, SDNPMayLoad]>;
358 def atomic_las : SDNode<"ISD::ATOMIC_LAS" , STDAtomic2,
359 [SDNPHasChain, SDNPMayStore, SDNPMayLoad]>;
360 def atomic_swap : SDNode<"ISD::ATOMIC_SWAP", STDAtomic2,
361 [SDNPHasChain, SDNPMayStore, SDNPMayLoad]>;
362 def atomic_lss : SDNode<"ISD::ATOMIC_LSS" , STDAtomic2,
363 [SDNPHasChain, SDNPMayStore, SDNPMayLoad]>;
364 def atomic_load_and : SDNode<"ISD::ATOMIC_LOAD_AND" , STDAtomic2,
365 [SDNPHasChain, SDNPMayStore, SDNPMayLoad]>;
366 def atomic_load_or : SDNode<"ISD::ATOMIC_LOAD_OR" , STDAtomic2,
367 [SDNPHasChain, SDNPMayStore, SDNPMayLoad]>;
368 def atomic_load_xor : SDNode<"ISD::ATOMIC_LOAD_XOR" , STDAtomic2,
369 [SDNPHasChain, SDNPMayStore, SDNPMayLoad]>;
370 def atomic_load_nand: SDNode<"ISD::ATOMIC_LOAD_NAND", STDAtomic2,
371 [SDNPHasChain, SDNPMayStore, SDNPMayLoad]>;
372 def atomic_load_min : SDNode<"ISD::ATOMIC_LOAD_MIN", STDAtomic2,
373 [SDNPHasChain, SDNPMayStore, SDNPMayLoad]>;
374 def atomic_load_max : SDNode<"ISD::ATOMIC_LOAD_MAX", STDAtomic2,
375 [SDNPHasChain, SDNPMayStore, SDNPMayLoad]>;
376 def atomic_load_umin : SDNode<"ISD::ATOMIC_LOAD_UMIN", STDAtomic2,
377 [SDNPHasChain, SDNPMayStore, SDNPMayLoad]>;
378 def atomic_load_umax : SDNode<"ISD::ATOMIC_LOAD_UMAX", STDAtomic2,
379 [SDNPHasChain, SDNPMayStore, SDNPMayLoad]>;
381 // Do not use ld, st directly. Use load, extload, sextload, zextload, store,
382 // and truncst (see below).
383 def ld : SDNode<"ISD::LOAD" , SDTLoad,
384 [SDNPHasChain, SDNPMayLoad]>;
385 def st : SDNode<"ISD::STORE" , SDTStore,
386 [SDNPHasChain, SDNPMayStore]>;
387 def ist : SDNode<"ISD::STORE" , SDTIStore,
388 [SDNPHasChain, SDNPMayStore]>;
390 def vector_shuffle : SDNode<"ISD::VECTOR_SHUFFLE", SDTVecShuffle, []>;
391 def build_vector : SDNode<"ISD::BUILD_VECTOR", SDTypeProfile<1, 0, []>, []>;
392 def scalar_to_vector : SDNode<"ISD::SCALAR_TO_VECTOR", SDTypeProfile<1, 1, []>,
394 def vector_extract : SDNode<"ISD::EXTRACT_VECTOR_ELT",
395 SDTypeProfile<1, 2, [SDTCisPtrTy<2>]>, []>;
396 def vector_insert : SDNode<"ISD::INSERT_VECTOR_ELT",
397 SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisPtrTy<3>]>, []>;
399 def extract_subreg : SDNode<"ISD::EXTRACT_SUBREG",
400 SDTypeProfile<1, 2, []>>;
401 def insert_subreg : SDNode<"ISD::INSERT_SUBREG",
402 SDTypeProfile<1, 3, []>>;
404 // Nodes for intrinsics, you should use the intrinsic itself and let tblgen use
405 // these internally. Don't reference these directly.
406 def intrinsic_void : SDNode<"ISD::INTRINSIC_VOID",
407 SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>,
409 def intrinsic_w_chain : SDNode<"ISD::INTRINSIC_W_CHAIN",
410 SDTypeProfile<1, -1, [SDTCisPtrTy<1>]>,
412 def intrinsic_wo_chain : SDNode<"ISD::INTRINSIC_WO_CHAIN",
413 SDTypeProfile<1, -1, [SDTCisPtrTy<1>]>, []>;
416 //===----------------------------------------------------------------------===//
417 // Selection DAG Condition Codes
419 class CondCode; // ISD::CondCode enums
420 def SETOEQ : CondCode; def SETOGT : CondCode;
421 def SETOGE : CondCode; def SETOLT : CondCode; def SETOLE : CondCode;
422 def SETONE : CondCode; def SETO : CondCode; def SETUO : CondCode;
423 def SETUEQ : CondCode; def SETUGT : CondCode; def SETUGE : CondCode;
424 def SETULT : CondCode; def SETULE : CondCode; def SETUNE : CondCode;
426 def SETEQ : CondCode; def SETGT : CondCode; def SETGE : CondCode;
427 def SETLT : CondCode; def SETLE : CondCode; def SETNE : CondCode;
430 //===----------------------------------------------------------------------===//
431 // Selection DAG Node Transformation Functions.
433 // This mechanism allows targets to manipulate nodes in the output DAG once a
434 // match has been formed. This is typically used to manipulate immediate
437 class SDNodeXForm<SDNode opc, code xformFunction> {
439 code XFormFunction = xformFunction;
442 def NOOP_SDNodeXForm : SDNodeXForm<imm, [{}]>;
445 //===----------------------------------------------------------------------===//
446 // Selection DAG Pattern Fragments.
448 // Pattern fragments are reusable chunks of dags that match specific things.
449 // They can take arguments and have C++ predicates that control whether they
450 // match. They are intended to make the patterns for common instructions more
451 // compact and readable.
454 /// PatFrag - Represents a pattern fragment. This can match something on the
455 /// DAG, frame a single node to multiply nested other fragments.
457 class PatFrag<dag ops, dag frag, code pred = [{}],
458 SDNodeXForm xform = NOOP_SDNodeXForm> {
461 code Predicate = pred;
462 SDNodeXForm OperandTransform = xform;
465 // PatLeaf's are pattern fragments that have no operands. This is just a helper
466 // to define immediates and other common things concisely.
467 class PatLeaf<dag frag, code pred = [{}], SDNodeXForm xform = NOOP_SDNodeXForm>
468 : PatFrag<(ops), frag, pred, xform>;
472 def vtInt : PatLeaf<(vt), [{ return N->getVT().isInteger(); }]>;
473 def vtFP : PatLeaf<(vt), [{ return N->getVT().isFloatingPoint(); }]>;
475 def immAllOnes : PatLeaf<(imm), [{ return N->isAllOnesValue(); }]>;
476 def immAllOnesV: PatLeaf<(build_vector), [{
477 return ISD::isBuildVectorAllOnes(N);
479 def immAllOnesV_bc: PatLeaf<(bitconvert), [{
480 return ISD::isBuildVectorAllOnes(N);
482 def immAllZerosV: PatLeaf<(build_vector), [{
483 return ISD::isBuildVectorAllZeros(N);
485 def immAllZerosV_bc: PatLeaf<(bitconvert), [{
486 return ISD::isBuildVectorAllZeros(N);
491 // Other helper fragments.
492 def not : PatFrag<(ops node:$in), (xor node:$in, immAllOnes)>;
493 def vnot : PatFrag<(ops node:$in), (xor node:$in, immAllOnesV)>;
494 def vnot_conv : PatFrag<(ops node:$in), (xor node:$in, immAllOnesV_bc)>;
495 def ineg : PatFrag<(ops node:$in), (sub 0, node:$in)>;
498 def load : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
499 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
500 return LD->getExtensionType() == ISD::NON_EXTLOAD &&
501 LD->getAddressingMode() == ISD::UNINDEXED;
505 // extending load fragments.
506 def extloadi1 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
507 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
508 return LD->getExtensionType() == ISD::EXTLOAD &&
509 LD->getAddressingMode() == ISD::UNINDEXED &&
510 LD->getMemoryVT() == MVT::i1;
513 def extloadi8 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
514 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
515 return LD->getExtensionType() == ISD::EXTLOAD &&
516 LD->getAddressingMode() == ISD::UNINDEXED &&
517 LD->getMemoryVT() == MVT::i8;
520 def extloadi16 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
521 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
522 return LD->getExtensionType() == ISD::EXTLOAD &&
523 LD->getAddressingMode() == ISD::UNINDEXED &&
524 LD->getMemoryVT() == MVT::i16;
527 def extloadi32 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
528 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
529 return LD->getExtensionType() == ISD::EXTLOAD &&
530 LD->getAddressingMode() == ISD::UNINDEXED &&
531 LD->getMemoryVT() == MVT::i32;
534 def extloadf32 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
535 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
536 return LD->getExtensionType() == ISD::EXTLOAD &&
537 LD->getAddressingMode() == ISD::UNINDEXED &&
538 LD->getMemoryVT() == MVT::f32;
541 def extloadf64 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
542 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
543 return LD->getExtensionType() == ISD::EXTLOAD &&
544 LD->getAddressingMode() == ISD::UNINDEXED &&
545 LD->getMemoryVT() == MVT::f64;
549 def sextloadi1 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
550 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
551 return LD->getExtensionType() == ISD::SEXTLOAD &&
552 LD->getAddressingMode() == ISD::UNINDEXED &&
553 LD->getMemoryVT() == MVT::i1;
556 def sextloadi8 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
557 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
558 return LD->getExtensionType() == ISD::SEXTLOAD &&
559 LD->getAddressingMode() == ISD::UNINDEXED &&
560 LD->getMemoryVT() == MVT::i8;
563 def sextloadi16 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
564 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
565 return LD->getExtensionType() == ISD::SEXTLOAD &&
566 LD->getAddressingMode() == ISD::UNINDEXED &&
567 LD->getMemoryVT() == MVT::i16;
570 def sextloadi32 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
571 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
572 return LD->getExtensionType() == ISD::SEXTLOAD &&
573 LD->getAddressingMode() == ISD::UNINDEXED &&
574 LD->getMemoryVT() == MVT::i32;
578 def zextloadi1 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
579 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
580 return LD->getExtensionType() == ISD::ZEXTLOAD &&
581 LD->getAddressingMode() == ISD::UNINDEXED &&
582 LD->getMemoryVT() == MVT::i1;
585 def zextloadi8 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
586 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
587 return LD->getExtensionType() == ISD::ZEXTLOAD &&
588 LD->getAddressingMode() == ISD::UNINDEXED &&
589 LD->getMemoryVT() == MVT::i8;
592 def zextloadi16 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
593 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
594 return LD->getExtensionType() == ISD::ZEXTLOAD &&
595 LD->getAddressingMode() == ISD::UNINDEXED &&
596 LD->getMemoryVT() == MVT::i16;
599 def zextloadi32 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
600 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
601 return LD->getExtensionType() == ISD::ZEXTLOAD &&
602 LD->getAddressingMode() == ISD::UNINDEXED &&
603 LD->getMemoryVT() == MVT::i32;
608 def store : PatFrag<(ops node:$val, node:$ptr),
609 (st node:$val, node:$ptr), [{
610 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
611 return !ST->isTruncatingStore() &&
612 ST->getAddressingMode() == ISD::UNINDEXED;
616 // truncstore fragments.
617 def truncstorei8 : PatFrag<(ops node:$val, node:$ptr),
618 (st node:$val, node:$ptr), [{
619 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
620 return ST->isTruncatingStore() && ST->getMemoryVT() == MVT::i8 &&
621 ST->getAddressingMode() == ISD::UNINDEXED;
624 def truncstorei16 : PatFrag<(ops node:$val, node:$ptr),
625 (st node:$val, node:$ptr), [{
626 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
627 return ST->isTruncatingStore() && ST->getMemoryVT() == MVT::i16 &&
628 ST->getAddressingMode() == ISD::UNINDEXED;
631 def truncstorei32 : PatFrag<(ops node:$val, node:$ptr),
632 (st node:$val, node:$ptr), [{
633 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
634 return ST->isTruncatingStore() && ST->getMemoryVT() == MVT::i32 &&
635 ST->getAddressingMode() == ISD::UNINDEXED;
638 def truncstoref32 : PatFrag<(ops node:$val, node:$ptr),
639 (st node:$val, node:$ptr), [{
640 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
641 return ST->isTruncatingStore() && ST->getMemoryVT() == MVT::f32 &&
642 ST->getAddressingMode() == ISD::UNINDEXED;
645 def truncstoref64 : PatFrag<(ops node:$val, node:$ptr),
646 (st node:$val, node:$ptr), [{
647 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
648 return ST->isTruncatingStore() && ST->getMemoryVT() == MVT::f64 &&
649 ST->getAddressingMode() == ISD::UNINDEXED;
653 // indexed store fragments.
654 def pre_store : PatFrag<(ops node:$val, node:$base, node:$offset),
655 (ist node:$val, node:$base, node:$offset), [{
656 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
657 ISD::MemIndexedMode AM = ST->getAddressingMode();
658 return (AM == ISD::PRE_INC || AM == ISD::PRE_DEC) &&
659 !ST->isTruncatingStore();
664 def pre_truncsti1 : PatFrag<(ops node:$val, node:$base, node:$offset),
665 (ist node:$val, node:$base, node:$offset), [{
666 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
667 ISD::MemIndexedMode AM = ST->getAddressingMode();
668 return (AM == ISD::PRE_INC || AM == ISD::PRE_DEC) &&
669 ST->isTruncatingStore() && ST->getMemoryVT() == MVT::i1;
673 def pre_truncsti8 : PatFrag<(ops node:$val, node:$base, node:$offset),
674 (ist node:$val, node:$base, node:$offset), [{
675 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
676 ISD::MemIndexedMode AM = ST->getAddressingMode();
677 return (AM == ISD::PRE_INC || AM == ISD::PRE_DEC) &&
678 ST->isTruncatingStore() && ST->getMemoryVT() == MVT::i8;
682 def pre_truncsti16 : PatFrag<(ops node:$val, node:$base, node:$offset),
683 (ist node:$val, node:$base, node:$offset), [{
684 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
685 ISD::MemIndexedMode AM = ST->getAddressingMode();
686 return (AM == ISD::PRE_INC || AM == ISD::PRE_DEC) &&
687 ST->isTruncatingStore() && ST->getMemoryVT() == MVT::i16;
691 def pre_truncsti32 : PatFrag<(ops node:$val, node:$base, node:$offset),
692 (ist node:$val, node:$base, node:$offset), [{
693 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
694 ISD::MemIndexedMode AM = ST->getAddressingMode();
695 return (AM == ISD::PRE_INC || AM == ISD::PRE_DEC) &&
696 ST->isTruncatingStore() && ST->getMemoryVT() == MVT::i32;
700 def pre_truncstf32 : PatFrag<(ops node:$val, node:$base, node:$offset),
701 (ist node:$val, node:$base, node:$offset), [{
702 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
703 ISD::MemIndexedMode AM = ST->getAddressingMode();
704 return (AM == ISD::PRE_INC || AM == ISD::PRE_DEC) &&
705 ST->isTruncatingStore() && ST->getMemoryVT() == MVT::f32;
710 def post_store : PatFrag<(ops node:$val, node:$ptr, node:$offset),
711 (ist node:$val, node:$ptr, node:$offset), [{
712 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
713 ISD::MemIndexedMode AM = ST->getAddressingMode();
714 return !ST->isTruncatingStore() &&
715 (AM == ISD::POST_INC || AM == ISD::POST_DEC);
720 def post_truncsti1 : PatFrag<(ops node:$val, node:$base, node:$offset),
721 (ist node:$val, node:$base, node:$offset), [{
722 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
723 ISD::MemIndexedMode AM = ST->getAddressingMode();
724 return (AM == ISD::POST_INC || AM == ISD::POST_DEC) &&
725 ST->isTruncatingStore() && ST->getMemoryVT() == MVT::i1;
729 def post_truncsti8 : PatFrag<(ops node:$val, node:$base, node:$offset),
730 (ist node:$val, node:$base, node:$offset), [{
731 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
732 ISD::MemIndexedMode AM = ST->getAddressingMode();
733 return (AM == ISD::POST_INC || AM == ISD::POST_DEC) &&
734 ST->isTruncatingStore() && ST->getMemoryVT() == MVT::i8;
738 def post_truncsti16 : PatFrag<(ops node:$val, node:$base, node:$offset),
739 (ist node:$val, node:$base, node:$offset), [{
740 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
741 ISD::MemIndexedMode AM = ST->getAddressingMode();
742 return (AM == ISD::POST_INC || AM == ISD::POST_DEC) &&
743 ST->isTruncatingStore() && ST->getMemoryVT() == MVT::i16;
747 def post_truncsti32 : PatFrag<(ops node:$val, node:$base, node:$offset),
748 (ist node:$val, node:$base, node:$offset), [{
749 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
750 ISD::MemIndexedMode AM = ST->getAddressingMode();
751 return (AM == ISD::POST_INC || AM == ISD::POST_DEC) &&
752 ST->isTruncatingStore() && ST->getMemoryVT() == MVT::i32;
756 def post_truncstf32 : PatFrag<(ops node:$val, node:$base, node:$offset),
757 (ist node:$val, node:$base, node:$offset), [{
758 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
759 ISD::MemIndexedMode AM = ST->getAddressingMode();
760 return (AM == ISD::POST_INC || AM == ISD::POST_DEC) &&
761 ST->isTruncatingStore() && ST->getMemoryVT() == MVT::f32;
767 def atomic_lcs_8 : PatFrag<(ops node:$ptr, node:$cmp, node:$swp),
768 (atomic_lcs node:$ptr, node:$cmp, node:$swp), [{
769 if (AtomicSDNode* V = dyn_cast<AtomicSDNode>(N))
770 return V->getVT() == MVT::i8;
773 def atomic_lcs_16 : PatFrag<(ops node:$ptr, node:$cmp, node:$swp),
774 (atomic_lcs node:$ptr, node:$cmp, node:$swp), [{
775 if (AtomicSDNode* V = dyn_cast<AtomicSDNode>(N))
776 return V->getVT() == MVT::i16;
779 def atomic_lcs_32 : PatFrag<(ops node:$ptr, node:$cmp, node:$swp),
780 (atomic_lcs node:$ptr, node:$cmp, node:$swp), [{
781 if (AtomicSDNode* V = dyn_cast<AtomicSDNode>(N))
782 return V->getVT() == MVT::i32;
785 def atomic_lcs_64 : PatFrag<(ops node:$ptr, node:$cmp, node:$swp),
786 (atomic_lcs node:$ptr, node:$cmp, node:$swp), [{
787 if (AtomicSDNode* V = dyn_cast<AtomicSDNode>(N))
788 return V->getVT() == MVT::i64;
792 def atomic_las_8 : PatFrag<(ops node:$ptr, node:$inc),
793 (atomic_las node:$ptr, node:$inc), [{
794 if (AtomicSDNode* V = dyn_cast<AtomicSDNode>(N))
795 return V->getVT() == MVT::i8;
798 def atomic_las_16 : PatFrag<(ops node:$ptr, node:$inc),
799 (atomic_las node:$ptr, node:$inc), [{
800 if (AtomicSDNode* V = dyn_cast<AtomicSDNode>(N))
801 return V->getVT() == MVT::i16;
804 def atomic_las_32 : PatFrag<(ops node:$ptr, node:$inc),
805 (atomic_las node:$ptr, node:$inc), [{
806 if (AtomicSDNode* V = dyn_cast<AtomicSDNode>(N))
807 return V->getVT() == MVT::i32;
810 def atomic_las_64 : PatFrag<(ops node:$ptr, node:$inc),
811 (atomic_las node:$ptr, node:$inc), [{
812 if (AtomicSDNode* V = dyn_cast<AtomicSDNode>(N))
813 return V->getVT() == MVT::i64;
817 def atomic_swap_8 : PatFrag<(ops node:$ptr, node:$inc),
818 (atomic_swap node:$ptr, node:$inc), [{
819 if (AtomicSDNode* V = dyn_cast<AtomicSDNode>(N))
820 return V->getVT() == MVT::i8;
823 def atomic_swap_16 : PatFrag<(ops node:$ptr, node:$inc),
824 (atomic_swap node:$ptr, node:$inc), [{
825 if (AtomicSDNode* V = dyn_cast<AtomicSDNode>(N))
826 return V->getVT() == MVT::i16;
829 def atomic_swap_32 : PatFrag<(ops node:$ptr, node:$inc),
830 (atomic_swap node:$ptr, node:$inc), [{
831 if (AtomicSDNode* V = dyn_cast<AtomicSDNode>(N))
832 return V->getVT() == MVT::i32;
835 def atomic_swap_64 : PatFrag<(ops node:$ptr, node:$inc),
836 (atomic_swap node:$ptr, node:$inc), [{
837 if (AtomicSDNode* V = dyn_cast<AtomicSDNode>(N))
838 return V->getVT() == MVT::i64;
844 // setcc convenience fragments.
845 def setoeq : PatFrag<(ops node:$lhs, node:$rhs),
846 (setcc node:$lhs, node:$rhs, SETOEQ)>;
847 def setogt : PatFrag<(ops node:$lhs, node:$rhs),
848 (setcc node:$lhs, node:$rhs, SETOGT)>;
849 def setoge : PatFrag<(ops node:$lhs, node:$rhs),
850 (setcc node:$lhs, node:$rhs, SETOGE)>;
851 def setolt : PatFrag<(ops node:$lhs, node:$rhs),
852 (setcc node:$lhs, node:$rhs, SETOLT)>;
853 def setole : PatFrag<(ops node:$lhs, node:$rhs),
854 (setcc node:$lhs, node:$rhs, SETOLE)>;
855 def setone : PatFrag<(ops node:$lhs, node:$rhs),
856 (setcc node:$lhs, node:$rhs, SETONE)>;
857 def seto : PatFrag<(ops node:$lhs, node:$rhs),
858 (setcc node:$lhs, node:$rhs, SETO)>;
859 def setuo : PatFrag<(ops node:$lhs, node:$rhs),
860 (setcc node:$lhs, node:$rhs, SETUO)>;
861 def setueq : PatFrag<(ops node:$lhs, node:$rhs),
862 (setcc node:$lhs, node:$rhs, SETUEQ)>;
863 def setugt : PatFrag<(ops node:$lhs, node:$rhs),
864 (setcc node:$lhs, node:$rhs, SETUGT)>;
865 def setuge : PatFrag<(ops node:$lhs, node:$rhs),
866 (setcc node:$lhs, node:$rhs, SETUGE)>;
867 def setult : PatFrag<(ops node:$lhs, node:$rhs),
868 (setcc node:$lhs, node:$rhs, SETULT)>;
869 def setule : PatFrag<(ops node:$lhs, node:$rhs),
870 (setcc node:$lhs, node:$rhs, SETULE)>;
871 def setune : PatFrag<(ops node:$lhs, node:$rhs),
872 (setcc node:$lhs, node:$rhs, SETUNE)>;
873 def seteq : PatFrag<(ops node:$lhs, node:$rhs),
874 (setcc node:$lhs, node:$rhs, SETEQ)>;
875 def setgt : PatFrag<(ops node:$lhs, node:$rhs),
876 (setcc node:$lhs, node:$rhs, SETGT)>;
877 def setge : PatFrag<(ops node:$lhs, node:$rhs),
878 (setcc node:$lhs, node:$rhs, SETGE)>;
879 def setlt : PatFrag<(ops node:$lhs, node:$rhs),
880 (setcc node:$lhs, node:$rhs, SETLT)>;
881 def setle : PatFrag<(ops node:$lhs, node:$rhs),
882 (setcc node:$lhs, node:$rhs, SETLE)>;
883 def setne : PatFrag<(ops node:$lhs, node:$rhs),
884 (setcc node:$lhs, node:$rhs, SETNE)>;
886 //===----------------------------------------------------------------------===//
887 // Selection DAG Pattern Support.
889 // Patterns are what are actually matched against the target-flavored
890 // instruction selection DAG. Instructions defined by the target implicitly
891 // define patterns in most cases, but patterns can also be explicitly added when
892 // an operation is defined by a sequence of instructions (e.g. loading a large
893 // immediate value on RISC targets that do not support immediates as large as
897 class Pattern<dag patternToMatch, list<dag> resultInstrs> {
898 dag PatternToMatch = patternToMatch;
899 list<dag> ResultInstrs = resultInstrs;
900 list<Predicate> Predicates = []; // See class Instruction in Target.td.
901 int AddedComplexity = 0; // See class Instruction in Target.td.
904 // Pat - A simple (but common) form of a pattern, which produces a simple result
905 // not needing a full list.
906 class Pat<dag pattern, dag result> : Pattern<pattern, [result]>;
908 //===----------------------------------------------------------------------===//
909 // Complex pattern definitions.
913 // Pass the parent Operand as root to CP function rather
914 // than the root of the sub-DAG
915 def CPAttrParentAsRoot : CPAttribute;
917 // Complex patterns, e.g. X86 addressing mode, requires pattern matching code
918 // in C++. NumOperands is the number of operands returned by the select function;
919 // SelectFunc is the name of the function used to pattern match the max. pattern;
920 // RootNodes are the list of possible root nodes of the sub-dags to match.
921 // e.g. X86 addressing mode - def addr : ComplexPattern<4, "SelectAddr", [add]>;
923 class ComplexPattern<ValueType ty, int numops, string fn,
924 list<SDNode> roots = [], list<SDNodeProperty> props = [],
925 list<CPAttribute> attrs = []> {
927 int NumOperands = numops;
928 string SelectFunc = fn;
929 list<SDNode> RootNodes = roots;
930 list<SDNodeProperty> Properties = props;
931 list<CPAttribute> Attributes = attrs;
934 //===----------------------------------------------------------------------===//
937 def SDT_dwarf_loc : SDTypeProfile<0, 3,
938 [SDTCisInt<0>, SDTCisInt<1>, SDTCisInt<2>]>;
939 def dwarf_loc : SDNode<"ISD::DEBUG_LOC", SDT_dwarf_loc,[SDNPHasChain]>;