1 //===- TargetSelectionDAG.td - Common code for DAG isels ---*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the target-independent interfaces used by SelectionDAG
11 // instruction selection generators.
13 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
16 // Selection DAG Type Constraint definitions.
18 // Note that the semantics of these constraints are hard coded into tblgen. To
19 // modify or add constraints, you have to hack tblgen.
22 class SDTypeConstraint<int opnum> {
23 int OperandNum = opnum;
26 // SDTCisVT - The specified operand has exactly this VT.
27 class SDTCisVT<int OpNum, ValueType vt> : SDTypeConstraint<OpNum> {
31 class SDTCisPtrTy<int OpNum> : SDTypeConstraint<OpNum>;
33 // SDTCisInt - The specified operand is has integer type.
34 class SDTCisInt<int OpNum> : SDTypeConstraint<OpNum>;
36 // SDTCisFP - The specified operand is has floating point type.
37 class SDTCisFP<int OpNum> : SDTypeConstraint<OpNum>;
39 // SDTCisSameAs - The two specified operands have identical types.
40 class SDTCisSameAs<int OpNum, int OtherOp> : SDTypeConstraint<OpNum> {
41 int OtherOperandNum = OtherOp;
44 // SDTCisVTSmallerThanOp - The specified operand is a VT SDNode, and its type is
45 // smaller than the 'Other' operand.
46 class SDTCisVTSmallerThanOp<int OpNum, int OtherOp> : SDTypeConstraint<OpNum> {
47 int OtherOperandNum = OtherOp;
50 class SDTCisOpSmallerThanOp<int SmallOp, int BigOp> : SDTypeConstraint<SmallOp>{
51 int BigOperandNum = BigOp;
54 /// SDTCisIntVectorOfSameSize - This indicates that ThisOp and OtherOp are
55 /// vector types, and that ThisOp is the result of
56 /// MVT::getIntVectorWithNumElements with the number of elements that ThisOp
58 class SDTCisIntVectorOfSameSize<int ThisOp, int OtherOp>
59 : SDTypeConstraint<ThisOp> {
60 int OtherOpNum = OtherOp;
63 /// SDTCisEltOfVec - This indicates that ThisOp is a scalar type of the same
64 /// type as the element type of OtherOp, which is a vector type.
65 class SDTCisEltOfVec<int ThisOp, int OtherOp>
66 : SDTypeConstraint<ThisOp> {
67 int OtherOpNum = OtherOp;
70 //===----------------------------------------------------------------------===//
71 // Selection DAG Type Profile definitions.
73 // These use the constraints defined above to describe the type requirements of
74 // the various nodes. These are not hard coded into tblgen, allowing targets to
75 // add their own if needed.
78 // SDTypeProfile - This profile describes the type requirements of a Selection
80 class SDTypeProfile<int numresults, int numoperands,
81 list<SDTypeConstraint> constraints> {
82 int NumResults = numresults;
83 int NumOperands = numoperands;
84 list<SDTypeConstraint> Constraints = constraints;
88 def SDTIntLeaf: SDTypeProfile<1, 0, [SDTCisInt<0>]>; // for 'imm'.
89 def SDTFPLeaf : SDTypeProfile<1, 0, [SDTCisFP<0>]>; // for 'fpimm'.
90 def SDTPtrLeaf: SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>; // for '&g'.
91 def SDTOther : SDTypeProfile<1, 0, [SDTCisVT<0, OtherVT>]>; // for 'vt'.
92 def SDTUNDEF : SDTypeProfile<1, 0, []>; // for 'undef'.
93 def SDTUnaryOp : SDTypeProfile<1, 1, []>; // bitconvert
95 def SDTIntBinOp : SDTypeProfile<1, 2, [ // add, and, or, xor, udiv, etc.
96 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<0>
98 def SDTIntShiftOp : SDTypeProfile<1, 2, [ // shl, sra, srl
99 SDTCisSameAs<0, 1>, SDTCisInt<0>, SDTCisInt<2>
101 def SDTFPBinOp : SDTypeProfile<1, 2, [ // fadd, fmul, etc.
102 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisFP<0>
104 def SDTFPSignOp : SDTypeProfile<1, 2, [ // fcopysign.
105 SDTCisSameAs<0, 1>, SDTCisFP<0>, SDTCisFP<2>
107 def SDTFPTernaryOp : SDTypeProfile<1, 3, [ // fmadd, fnmsub, etc.
108 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>, SDTCisFP<0>
110 def SDTIntUnaryOp : SDTypeProfile<1, 1, [ // ctlz
111 SDTCisSameAs<0, 1>, SDTCisInt<0>
113 def SDTIntExtendOp : SDTypeProfile<1, 1, [ // sext, zext, anyext
114 SDTCisInt<0>, SDTCisInt<1>, SDTCisOpSmallerThanOp<1, 0>
116 def SDTIntTruncOp : SDTypeProfile<1, 1, [ // trunc
117 SDTCisInt<0>, SDTCisInt<1>, SDTCisOpSmallerThanOp<0, 1>
119 def SDTFPUnaryOp : SDTypeProfile<1, 1, [ // fneg, fsqrt, etc
120 SDTCisSameAs<0, 1>, SDTCisFP<0>
122 def SDTFPRoundOp : SDTypeProfile<1, 1, [ // fround
123 SDTCisFP<0>, SDTCisFP<1>, SDTCisOpSmallerThanOp<0, 1>
125 def SDTFPExtendOp : SDTypeProfile<1, 1, [ // fextend
126 SDTCisFP<0>, SDTCisFP<1>, SDTCisOpSmallerThanOp<1, 0>
128 def SDTIntToFPOp : SDTypeProfile<1, 1, [ // [su]int_to_fp
129 SDTCisFP<0>, SDTCisInt<1>
131 def SDTFPToIntOp : SDTypeProfile<1, 1, [ // fp_to_[su]int
132 SDTCisInt<0>, SDTCisFP<1>
134 def SDTExtInreg : SDTypeProfile<1, 2, [ // sext_inreg
135 SDTCisSameAs<0, 1>, SDTCisInt<0>, SDTCisVT<2, OtherVT>,
136 SDTCisVTSmallerThanOp<2, 1>
139 def SDTSetCC : SDTypeProfile<1, 3, [ // setcc
140 SDTCisInt<0>, SDTCisSameAs<1, 2>, SDTCisVT<3, OtherVT>
143 def SDTSelect : SDTypeProfile<1, 3, [ // select
144 SDTCisInt<1>, SDTCisSameAs<0, 2>, SDTCisSameAs<2, 3>
147 def SDTSelectCC : SDTypeProfile<1, 5, [ // select_cc
148 SDTCisSameAs<1, 2>, SDTCisSameAs<3, 4>, SDTCisSameAs<0, 3>,
152 def SDTBr : SDTypeProfile<0, 1, [ // br
156 def SDTBrcond : SDTypeProfile<0, 2, [ // brcond
157 SDTCisInt<0>, SDTCisVT<1, OtherVT>
160 def SDTBrind : SDTypeProfile<0, 1, [ // brind
164 def SDTNone : SDTypeProfile<0, 0, []>; // ret, trap
166 def SDTLoad : SDTypeProfile<1, 1, [ // load
170 def SDTStore : SDTypeProfile<0, 2, [ // store
174 def SDTIStore : SDTypeProfile<1, 3, [ // indexed store
175 SDTCisSameAs<0, 2>, SDTCisPtrTy<0>, SDTCisPtrTy<3>
178 def SDTVecShuffle : SDTypeProfile<1, 3, [
179 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisIntVectorOfSameSize<3, 0>
181 def SDTVecExtract : SDTypeProfile<1, 2, [ // vector extract
182 SDTCisEltOfVec<0, 1>, SDTCisPtrTy<2>
184 def SDTVecInsert : SDTypeProfile<1, 3, [ // vector insert
185 SDTCisEltOfVec<2, 1>, SDTCisSameAs<0, 1>, SDTCisPtrTy<3>
188 def STDMemBarrier : SDTypeProfile<0, 5, [
189 SDTCisSameAs<0,1>, SDTCisSameAs<0,2>, SDTCisSameAs<0,3>, SDTCisSameAs<0,4>,
192 def STDAtomic3 : SDTypeProfile<1, 3, [
193 SDTCisSameAs<0,2>, SDTCisSameAs<0,3>, SDTCisInt<0>, SDTCisPtrTy<1>
195 def STDAtomic2 : SDTypeProfile<1, 2, [
196 SDTCisSameAs<0,2>, SDTCisInt<0>, SDTCisPtrTy<1>
199 class SDCallSeqStart<list<SDTypeConstraint> constraints> :
200 SDTypeProfile<0, 1, constraints>;
201 class SDCallSeqEnd<list<SDTypeConstraint> constraints> :
202 SDTypeProfile<0, 2, constraints>;
204 //===----------------------------------------------------------------------===//
205 // Selection DAG Node Properties.
207 // Note: These are hard coded into tblgen.
209 class SDNodeProperty;
210 def SDNPCommutative : SDNodeProperty; // X op Y == Y op X
211 def SDNPAssociative : SDNodeProperty; // (X op Y) op Z == X op (Y op Z)
212 def SDNPHasChain : SDNodeProperty; // R/W chain operand and result
213 def SDNPOutFlag : SDNodeProperty; // Write a flag result
214 def SDNPInFlag : SDNodeProperty; // Read a flag operand
215 def SDNPOptInFlag : SDNodeProperty; // Optionally read a flag operand
216 def SDNPMayStore : SDNodeProperty; // May write to memory, sets 'mayStore'.
217 def SDNPMayLoad : SDNodeProperty; // May read memory, sets 'mayLoad'.
218 def SDNPSideEffect : SDNodeProperty; // Sets 'HasUnmodelledSideEffects'.
220 //===----------------------------------------------------------------------===//
221 // Selection DAG Node definitions.
223 class SDNode<string opcode, SDTypeProfile typeprof,
224 list<SDNodeProperty> props = [], string sdclass = "SDNode"> {
225 string Opcode = opcode;
226 string SDClass = sdclass;
227 list<SDNodeProperty> Properties = props;
228 SDTypeProfile TypeProfile = typeprof;
237 def imm : SDNode<"ISD::Constant" , SDTIntLeaf , [], "ConstantSDNode">;
238 def fpimm : SDNode<"ISD::ConstantFP", SDTFPLeaf , [], "ConstantFPSDNode">;
239 def vt : SDNode<"ISD::VALUETYPE" , SDTOther , [], "VTSDNode">;
240 def bb : SDNode<"ISD::BasicBlock", SDTOther , [], "BasicBlockSDNode">;
241 def cond : SDNode<"ISD::CONDCODE" , SDTOther , [], "CondCodeSDNode">;
242 def undef : SDNode<"ISD::UNDEF" , SDTUNDEF , []>;
243 def globaladdr : SDNode<"ISD::GlobalAddress", SDTPtrLeaf, [],
244 "GlobalAddressSDNode">;
245 def tglobaladdr : SDNode<"ISD::TargetGlobalAddress", SDTPtrLeaf, [],
246 "GlobalAddressSDNode">;
247 def globaltlsaddr : SDNode<"ISD::GlobalTLSAddress", SDTPtrLeaf, [],
248 "GlobalAddressSDNode">;
249 def tglobaltlsaddr : SDNode<"ISD::TargetGlobalTLSAddress", SDTPtrLeaf, [],
250 "GlobalAddressSDNode">;
251 def constpool : SDNode<"ISD::ConstantPool", SDTPtrLeaf, [],
252 "ConstantPoolSDNode">;
253 def tconstpool : SDNode<"ISD::TargetConstantPool", SDTPtrLeaf, [],
254 "ConstantPoolSDNode">;
255 def jumptable : SDNode<"ISD::JumpTable", SDTPtrLeaf, [],
257 def tjumptable : SDNode<"ISD::TargetJumpTable", SDTPtrLeaf, [],
259 def frameindex : SDNode<"ISD::FrameIndex", SDTPtrLeaf, [],
261 def tframeindex : SDNode<"ISD::TargetFrameIndex", SDTPtrLeaf, [],
263 def externalsym : SDNode<"ISD::ExternalSymbol", SDTPtrLeaf, [],
264 "ExternalSymbolSDNode">;
265 def texternalsym: SDNode<"ISD::TargetExternalSymbol", SDTPtrLeaf, [],
266 "ExternalSymbolSDNode">;
268 def add : SDNode<"ISD::ADD" , SDTIntBinOp ,
269 [SDNPCommutative, SDNPAssociative]>;
270 def sub : SDNode<"ISD::SUB" , SDTIntBinOp>;
271 def mul : SDNode<"ISD::MUL" , SDTIntBinOp,
272 [SDNPCommutative, SDNPAssociative]>;
273 def mulhs : SDNode<"ISD::MULHS" , SDTIntBinOp, [SDNPCommutative]>;
274 def mulhu : SDNode<"ISD::MULHU" , SDTIntBinOp, [SDNPCommutative]>;
275 def sdiv : SDNode<"ISD::SDIV" , SDTIntBinOp>;
276 def udiv : SDNode<"ISD::UDIV" , SDTIntBinOp>;
277 def srem : SDNode<"ISD::SREM" , SDTIntBinOp>;
278 def urem : SDNode<"ISD::UREM" , SDTIntBinOp>;
279 def srl : SDNode<"ISD::SRL" , SDTIntShiftOp>;
280 def sra : SDNode<"ISD::SRA" , SDTIntShiftOp>;
281 def shl : SDNode<"ISD::SHL" , SDTIntShiftOp>;
282 def rotl : SDNode<"ISD::ROTL" , SDTIntShiftOp>;
283 def rotr : SDNode<"ISD::ROTR" , SDTIntShiftOp>;
284 def and : SDNode<"ISD::AND" , SDTIntBinOp,
285 [SDNPCommutative, SDNPAssociative]>;
286 def or : SDNode<"ISD::OR" , SDTIntBinOp,
287 [SDNPCommutative, SDNPAssociative]>;
288 def xor : SDNode<"ISD::XOR" , SDTIntBinOp,
289 [SDNPCommutative, SDNPAssociative]>;
290 def addc : SDNode<"ISD::ADDC" , SDTIntBinOp,
291 [SDNPCommutative, SDNPOutFlag]>;
292 def adde : SDNode<"ISD::ADDE" , SDTIntBinOp,
293 [SDNPCommutative, SDNPOutFlag, SDNPInFlag]>;
294 def subc : SDNode<"ISD::SUBC" , SDTIntBinOp,
296 def sube : SDNode<"ISD::SUBE" , SDTIntBinOp,
297 [SDNPOutFlag, SDNPInFlag]>;
299 def sext_inreg : SDNode<"ISD::SIGN_EXTEND_INREG", SDTExtInreg>;
300 def bswap : SDNode<"ISD::BSWAP" , SDTIntUnaryOp>;
301 def ctlz : SDNode<"ISD::CTLZ" , SDTIntUnaryOp>;
302 def cttz : SDNode<"ISD::CTTZ" , SDTIntUnaryOp>;
303 def ctpop : SDNode<"ISD::CTPOP" , SDTIntUnaryOp>;
304 def sext : SDNode<"ISD::SIGN_EXTEND", SDTIntExtendOp>;
305 def zext : SDNode<"ISD::ZERO_EXTEND", SDTIntExtendOp>;
306 def anyext : SDNode<"ISD::ANY_EXTEND" , SDTIntExtendOp>;
307 def trunc : SDNode<"ISD::TRUNCATE" , SDTIntTruncOp>;
308 def bitconvert : SDNode<"ISD::BIT_CONVERT", SDTUnaryOp>;
309 def extractelt : SDNode<"ISD::EXTRACT_VECTOR_ELT", SDTVecExtract>;
310 def insertelt : SDNode<"ISD::INSERT_VECTOR_ELT", SDTVecInsert>;
313 def fadd : SDNode<"ISD::FADD" , SDTFPBinOp, [SDNPCommutative]>;
314 def fsub : SDNode<"ISD::FSUB" , SDTFPBinOp>;
315 def fmul : SDNode<"ISD::FMUL" , SDTFPBinOp, [SDNPCommutative]>;
316 def fdiv : SDNode<"ISD::FDIV" , SDTFPBinOp>;
317 def frem : SDNode<"ISD::FREM" , SDTFPBinOp>;
318 def fabs : SDNode<"ISD::FABS" , SDTFPUnaryOp>;
319 def fneg : SDNode<"ISD::FNEG" , SDTFPUnaryOp>;
320 def fsqrt : SDNode<"ISD::FSQRT" , SDTFPUnaryOp>;
321 def fsin : SDNode<"ISD::FSIN" , SDTFPUnaryOp>;
322 def fcos : SDNode<"ISD::FCOS" , SDTFPUnaryOp>;
324 def fround : SDNode<"ISD::FP_ROUND" , SDTFPRoundOp>;
325 def fextend : SDNode<"ISD::FP_EXTEND" , SDTFPExtendOp>;
326 def fcopysign : SDNode<"ISD::FCOPYSIGN" , SDTFPSignOp>;
328 def sint_to_fp : SDNode<"ISD::SINT_TO_FP" , SDTIntToFPOp>;
329 def uint_to_fp : SDNode<"ISD::UINT_TO_FP" , SDTIntToFPOp>;
330 def fp_to_sint : SDNode<"ISD::FP_TO_SINT" , SDTFPToIntOp>;
331 def fp_to_uint : SDNode<"ISD::FP_TO_UINT" , SDTFPToIntOp>;
333 def setcc : SDNode<"ISD::SETCC" , SDTSetCC>;
334 def select : SDNode<"ISD::SELECT" , SDTSelect>;
335 def selectcc : SDNode<"ISD::SELECT_CC" , SDTSelectCC>;
337 def brcond : SDNode<"ISD::BRCOND" , SDTBrcond, [SDNPHasChain]>;
338 def brind : SDNode<"ISD::BRIND" , SDTBrind, [SDNPHasChain]>;
339 def br : SDNode<"ISD::BR" , SDTBr, [SDNPHasChain]>;
340 def ret : SDNode<"ISD::RET" , SDTNone, [SDNPHasChain]>;
341 def trap : SDNode<"ISD::TRAP" , SDTNone,
342 [SDNPHasChain, SDNPSideEffect]>;
343 def membarrier : SDNode<"ISD::MEMBARRIER" , STDMemBarrier,
344 [SDNPHasChain, SDNPSideEffect]>;
345 // Do not use atomic_* directly, use atomic_*_size (see below)
346 def atomic_lcs : SDNode<"ISD::ATOMIC_LCS", STDAtomic3,
347 [SDNPHasChain, SDNPMayStore, SDNPMayLoad]>;
348 def atomic_las : SDNode<"ISD::ATOMIC_LAS", STDAtomic2,
349 [SDNPHasChain, SDNPMayStore, SDNPMayLoad]>;
350 def atomic_swap : SDNode<"ISD::ATOMIC_SWAP", STDAtomic2,
351 [SDNPHasChain, SDNPMayStore, SDNPMayLoad]>;
353 // Do not use ld, st directly. Use load, extload, sextload, zextload, store,
354 // and truncst (see below).
355 def ld : SDNode<"ISD::LOAD" , SDTLoad,
356 [SDNPHasChain, SDNPMayLoad]>;
357 def st : SDNode<"ISD::STORE" , SDTStore,
358 [SDNPHasChain, SDNPMayStore]>;
359 def ist : SDNode<"ISD::STORE" , SDTIStore,
360 [SDNPHasChain, SDNPMayStore]>;
362 def vector_shuffle : SDNode<"ISD::VECTOR_SHUFFLE", SDTVecShuffle, []>;
363 def build_vector : SDNode<"ISD::BUILD_VECTOR", SDTypeProfile<1, 0, []>, []>;
364 def scalar_to_vector : SDNode<"ISD::SCALAR_TO_VECTOR", SDTypeProfile<1, 1, []>,
366 def vector_extract : SDNode<"ISD::EXTRACT_VECTOR_ELT",
367 SDTypeProfile<1, 2, [SDTCisPtrTy<2>]>, []>;
368 def vector_insert : SDNode<"ISD::INSERT_VECTOR_ELT",
369 SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisPtrTy<3>]>, []>;
371 def extract_subreg : SDNode<"ISD::EXTRACT_SUBREG",
372 SDTypeProfile<1, 2, []>>;
373 def insert_subreg : SDNode<"ISD::INSERT_SUBREG",
374 SDTypeProfile<1, 3, []>>;
376 // Nodes for intrinsics, you should use the intrinsic itself and let tblgen use
377 // these internally. Don't reference these directly.
378 def intrinsic_void : SDNode<"ISD::INTRINSIC_VOID",
379 SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>,
381 def intrinsic_w_chain : SDNode<"ISD::INTRINSIC_W_CHAIN",
382 SDTypeProfile<1, -1, [SDTCisPtrTy<1>]>,
384 def intrinsic_wo_chain : SDNode<"ISD::INTRINSIC_WO_CHAIN",
385 SDTypeProfile<1, -1, [SDTCisPtrTy<1>]>, []>;
388 //===----------------------------------------------------------------------===//
389 // Selection DAG Condition Codes
391 class CondCode; // ISD::CondCode enums
392 def SETOEQ : CondCode; def SETOGT : CondCode;
393 def SETOGE : CondCode; def SETOLT : CondCode; def SETOLE : CondCode;
394 def SETONE : CondCode; def SETO : CondCode; def SETUO : CondCode;
395 def SETUEQ : CondCode; def SETUGT : CondCode; def SETUGE : CondCode;
396 def SETULT : CondCode; def SETULE : CondCode; def SETUNE : CondCode;
398 def SETEQ : CondCode; def SETGT : CondCode; def SETGE : CondCode;
399 def SETLT : CondCode; def SETLE : CondCode; def SETNE : CondCode;
402 //===----------------------------------------------------------------------===//
403 // Selection DAG Node Transformation Functions.
405 // This mechanism allows targets to manipulate nodes in the output DAG once a
406 // match has been formed. This is typically used to manipulate immediate
409 class SDNodeXForm<SDNode opc, code xformFunction> {
411 code XFormFunction = xformFunction;
414 def NOOP_SDNodeXForm : SDNodeXForm<imm, [{}]>;
417 //===----------------------------------------------------------------------===//
418 // Selection DAG Pattern Fragments.
420 // Pattern fragments are reusable chunks of dags that match specific things.
421 // They can take arguments and have C++ predicates that control whether they
422 // match. They are intended to make the patterns for common instructions more
423 // compact and readable.
426 /// PatFrag - Represents a pattern fragment. This can match something on the
427 /// DAG, frame a single node to multiply nested other fragments.
429 class PatFrag<dag ops, dag frag, code pred = [{}],
430 SDNodeXForm xform = NOOP_SDNodeXForm> {
433 code Predicate = pred;
434 SDNodeXForm OperandTransform = xform;
437 // PatLeaf's are pattern fragments that have no operands. This is just a helper
438 // to define immediates and other common things concisely.
439 class PatLeaf<dag frag, code pred = [{}], SDNodeXForm xform = NOOP_SDNodeXForm>
440 : PatFrag<(ops), frag, pred, xform>;
444 def vtInt : PatLeaf<(vt), [{ return MVT::isInteger(N->getVT()); }]>;
445 def vtFP : PatLeaf<(vt), [{ return MVT::isFloatingPoint(N->getVT()); }]>;
447 def immAllOnes : PatLeaf<(imm), [{ return N->isAllOnesValue(); }]>;
448 def immAllOnesV: PatLeaf<(build_vector), [{
449 return ISD::isBuildVectorAllOnes(N);
451 def immAllOnesV_bc: PatLeaf<(bitconvert), [{
452 return ISD::isBuildVectorAllOnes(N);
454 def immAllZerosV: PatLeaf<(build_vector), [{
455 return ISD::isBuildVectorAllZeros(N);
457 def immAllZerosV_bc: PatLeaf<(bitconvert), [{
458 return ISD::isBuildVectorAllZeros(N);
463 // Other helper fragments.
464 def not : PatFrag<(ops node:$in), (xor node:$in, immAllOnes)>;
465 def vnot : PatFrag<(ops node:$in), (xor node:$in, immAllOnesV)>;
466 def vnot_conv : PatFrag<(ops node:$in), (xor node:$in, immAllOnesV_bc)>;
467 def ineg : PatFrag<(ops node:$in), (sub 0, node:$in)>;
470 def load : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
471 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
472 return LD->getExtensionType() == ISD::NON_EXTLOAD &&
473 LD->getAddressingMode() == ISD::UNINDEXED;
477 // extending load fragments.
478 def extloadi1 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
479 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
480 return LD->getExtensionType() == ISD::EXTLOAD &&
481 LD->getAddressingMode() == ISD::UNINDEXED &&
482 LD->getMemoryVT() == MVT::i1;
485 def extloadi8 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
486 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
487 return LD->getExtensionType() == ISD::EXTLOAD &&
488 LD->getAddressingMode() == ISD::UNINDEXED &&
489 LD->getMemoryVT() == MVT::i8;
492 def extloadi16 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
493 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
494 return LD->getExtensionType() == ISD::EXTLOAD &&
495 LD->getAddressingMode() == ISD::UNINDEXED &&
496 LD->getMemoryVT() == MVT::i16;
499 def extloadi32 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
500 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
501 return LD->getExtensionType() == ISD::EXTLOAD &&
502 LD->getAddressingMode() == ISD::UNINDEXED &&
503 LD->getMemoryVT() == MVT::i32;
506 def extloadf32 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
507 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
508 return LD->getExtensionType() == ISD::EXTLOAD &&
509 LD->getAddressingMode() == ISD::UNINDEXED &&
510 LD->getMemoryVT() == MVT::f32;
513 def extloadf64 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
514 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
515 return LD->getExtensionType() == ISD::EXTLOAD &&
516 LD->getAddressingMode() == ISD::UNINDEXED &&
517 LD->getMemoryVT() == MVT::f64;
521 def sextloadi1 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
522 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
523 return LD->getExtensionType() == ISD::SEXTLOAD &&
524 LD->getAddressingMode() == ISD::UNINDEXED &&
525 LD->getMemoryVT() == MVT::i1;
528 def sextloadi8 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
529 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
530 return LD->getExtensionType() == ISD::SEXTLOAD &&
531 LD->getAddressingMode() == ISD::UNINDEXED &&
532 LD->getMemoryVT() == MVT::i8;
535 def sextloadi16 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
536 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
537 return LD->getExtensionType() == ISD::SEXTLOAD &&
538 LD->getAddressingMode() == ISD::UNINDEXED &&
539 LD->getMemoryVT() == MVT::i16;
542 def sextloadi32 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
543 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
544 return LD->getExtensionType() == ISD::SEXTLOAD &&
545 LD->getAddressingMode() == ISD::UNINDEXED &&
546 LD->getMemoryVT() == MVT::i32;
550 def zextloadi1 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
551 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
552 return LD->getExtensionType() == ISD::ZEXTLOAD &&
553 LD->getAddressingMode() == ISD::UNINDEXED &&
554 LD->getMemoryVT() == MVT::i1;
557 def zextloadi8 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
558 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
559 return LD->getExtensionType() == ISD::ZEXTLOAD &&
560 LD->getAddressingMode() == ISD::UNINDEXED &&
561 LD->getMemoryVT() == MVT::i8;
564 def zextloadi16 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
565 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
566 return LD->getExtensionType() == ISD::ZEXTLOAD &&
567 LD->getAddressingMode() == ISD::UNINDEXED &&
568 LD->getMemoryVT() == MVT::i16;
571 def zextloadi32 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
572 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
573 return LD->getExtensionType() == ISD::ZEXTLOAD &&
574 LD->getAddressingMode() == ISD::UNINDEXED &&
575 LD->getMemoryVT() == MVT::i32;
580 def store : PatFrag<(ops node:$val, node:$ptr),
581 (st node:$val, node:$ptr), [{
582 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
583 return !ST->isTruncatingStore() &&
584 ST->getAddressingMode() == ISD::UNINDEXED;
588 // truncstore fragments.
589 def truncstorei8 : PatFrag<(ops node:$val, node:$ptr),
590 (st node:$val, node:$ptr), [{
591 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
592 return ST->isTruncatingStore() && ST->getMemoryVT() == MVT::i8 &&
593 ST->getAddressingMode() == ISD::UNINDEXED;
596 def truncstorei16 : PatFrag<(ops node:$val, node:$ptr),
597 (st node:$val, node:$ptr), [{
598 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
599 return ST->isTruncatingStore() && ST->getMemoryVT() == MVT::i16 &&
600 ST->getAddressingMode() == ISD::UNINDEXED;
603 def truncstorei32 : PatFrag<(ops node:$val, node:$ptr),
604 (st node:$val, node:$ptr), [{
605 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
606 return ST->isTruncatingStore() && ST->getMemoryVT() == MVT::i32 &&
607 ST->getAddressingMode() == ISD::UNINDEXED;
610 def truncstoref32 : PatFrag<(ops node:$val, node:$ptr),
611 (st node:$val, node:$ptr), [{
612 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
613 return ST->isTruncatingStore() && ST->getMemoryVT() == MVT::f32 &&
614 ST->getAddressingMode() == ISD::UNINDEXED;
617 def truncstoref64 : PatFrag<(ops node:$val, node:$ptr),
618 (st node:$val, node:$ptr), [{
619 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
620 return ST->isTruncatingStore() && ST->getMemoryVT() == MVT::f64 &&
621 ST->getAddressingMode() == ISD::UNINDEXED;
625 // indexed store fragments.
626 def pre_store : PatFrag<(ops node:$val, node:$base, node:$offset),
627 (ist node:$val, node:$base, node:$offset), [{
628 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
629 ISD::MemIndexedMode AM = ST->getAddressingMode();
630 return (AM == ISD::PRE_INC || AM == ISD::PRE_DEC) &&
631 !ST->isTruncatingStore();
636 def pre_truncsti1 : PatFrag<(ops node:$val, node:$base, node:$offset),
637 (ist node:$val, node:$base, node:$offset), [{
638 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
639 ISD::MemIndexedMode AM = ST->getAddressingMode();
640 return (AM == ISD::PRE_INC || AM == ISD::PRE_DEC) &&
641 ST->isTruncatingStore() && ST->getMemoryVT() == MVT::i1;
645 def pre_truncsti8 : PatFrag<(ops node:$val, node:$base, node:$offset),
646 (ist node:$val, node:$base, node:$offset), [{
647 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
648 ISD::MemIndexedMode AM = ST->getAddressingMode();
649 return (AM == ISD::PRE_INC || AM == ISD::PRE_DEC) &&
650 ST->isTruncatingStore() && ST->getMemoryVT() == MVT::i8;
654 def pre_truncsti16 : PatFrag<(ops node:$val, node:$base, node:$offset),
655 (ist node:$val, node:$base, node:$offset), [{
656 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
657 ISD::MemIndexedMode AM = ST->getAddressingMode();
658 return (AM == ISD::PRE_INC || AM == ISD::PRE_DEC) &&
659 ST->isTruncatingStore() && ST->getMemoryVT() == MVT::i16;
663 def pre_truncsti32 : PatFrag<(ops node:$val, node:$base, node:$offset),
664 (ist node:$val, node:$base, node:$offset), [{
665 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
666 ISD::MemIndexedMode AM = ST->getAddressingMode();
667 return (AM == ISD::PRE_INC || AM == ISD::PRE_DEC) &&
668 ST->isTruncatingStore() && ST->getMemoryVT() == MVT::i32;
672 def pre_truncstf32 : PatFrag<(ops node:$val, node:$base, node:$offset),
673 (ist node:$val, node:$base, node:$offset), [{
674 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
675 ISD::MemIndexedMode AM = ST->getAddressingMode();
676 return (AM == ISD::PRE_INC || AM == ISD::PRE_DEC) &&
677 ST->isTruncatingStore() && ST->getMemoryVT() == MVT::f32;
682 def post_store : PatFrag<(ops node:$val, node:$ptr, node:$offset),
683 (ist node:$val, node:$ptr, node:$offset), [{
684 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
685 ISD::MemIndexedMode AM = ST->getAddressingMode();
686 return !ST->isTruncatingStore() &&
687 (AM == ISD::POST_INC || AM == ISD::POST_DEC);
692 def post_truncsti1 : PatFrag<(ops node:$val, node:$base, node:$offset),
693 (ist node:$val, node:$base, node:$offset), [{
694 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
695 ISD::MemIndexedMode AM = ST->getAddressingMode();
696 return (AM == ISD::POST_INC || AM == ISD::POST_DEC) &&
697 ST->isTruncatingStore() && ST->getMemoryVT() == MVT::i1;
701 def post_truncsti8 : PatFrag<(ops node:$val, node:$base, node:$offset),
702 (ist node:$val, node:$base, node:$offset), [{
703 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
704 ISD::MemIndexedMode AM = ST->getAddressingMode();
705 return (AM == ISD::POST_INC || AM == ISD::POST_DEC) &&
706 ST->isTruncatingStore() && ST->getMemoryVT() == MVT::i8;
710 def post_truncsti16 : PatFrag<(ops node:$val, node:$base, node:$offset),
711 (ist node:$val, node:$base, node:$offset), [{
712 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
713 ISD::MemIndexedMode AM = ST->getAddressingMode();
714 return (AM == ISD::POST_INC || AM == ISD::POST_DEC) &&
715 ST->isTruncatingStore() && ST->getMemoryVT() == MVT::i16;
719 def post_truncsti32 : PatFrag<(ops node:$val, node:$base, node:$offset),
720 (ist node:$val, node:$base, node:$offset), [{
721 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
722 ISD::MemIndexedMode AM = ST->getAddressingMode();
723 return (AM == ISD::POST_INC || AM == ISD::POST_DEC) &&
724 ST->isTruncatingStore() && ST->getMemoryVT() == MVT::i32;
728 def post_truncstf32 : PatFrag<(ops node:$val, node:$base, node:$offset),
729 (ist node:$val, node:$base, node:$offset), [{
730 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
731 ISD::MemIndexedMode AM = ST->getAddressingMode();
732 return (AM == ISD::POST_INC || AM == ISD::POST_DEC) &&
733 ST->isTruncatingStore() && ST->getMemoryVT() == MVT::f32;
739 def atomic_lcs_8 : PatFrag<(ops node:$ptr, node:$cmp, node:$swp),
740 (atomic_lcs node:$ptr, node:$cmp, node:$swp), [{
741 if (AtomicSDNode* V = dyn_cast<AtomicSDNode>(N))
742 return V->getVT() == MVT::i8;
745 def atomic_lcs_16 : PatFrag<(ops node:$ptr, node:$cmp, node:$swp),
746 (atomic_lcs node:$ptr, node:$cmp, node:$swp), [{
747 if (AtomicSDNode* V = dyn_cast<AtomicSDNode>(N))
748 return V->getVT() == MVT::i16;
751 def atomic_lcs_32 : PatFrag<(ops node:$ptr, node:$cmp, node:$swp),
752 (atomic_lcs node:$ptr, node:$cmp, node:$swp), [{
753 if (AtomicSDNode* V = dyn_cast<AtomicSDNode>(N))
754 return V->getVT() == MVT::i32;
757 def atomic_lcs_64 : PatFrag<(ops node:$ptr, node:$cmp, node:$swp),
758 (atomic_lcs node:$ptr, node:$cmp, node:$swp), [{
759 if (AtomicSDNode* V = dyn_cast<AtomicSDNode>(N))
760 return V->getVT() == MVT::i64;
764 def atomic_las_8 : PatFrag<(ops node:$ptr, node:$inc),
765 (atomic_las node:$ptr, node:$inc), [{
766 if (AtomicSDNode* V = dyn_cast<AtomicSDNode>(N))
767 return V->getVT() == MVT::i8;
770 def atomic_las_16 : PatFrag<(ops node:$ptr, node:$inc),
771 (atomic_las node:$ptr, node:$inc), [{
772 if (AtomicSDNode* V = dyn_cast<AtomicSDNode>(N))
773 return V->getVT() == MVT::i16;
776 def atomic_las_32 : PatFrag<(ops node:$ptr, node:$inc),
777 (atomic_las node:$ptr, node:$inc), [{
778 if (AtomicSDNode* V = dyn_cast<AtomicSDNode>(N))
779 return V->getVT() == MVT::i32;
782 def atomic_las_64 : PatFrag<(ops node:$ptr, node:$inc),
783 (atomic_las node:$ptr, node:$inc), [{
784 if (AtomicSDNode* V = dyn_cast<AtomicSDNode>(N))
785 return V->getVT() == MVT::i64;
789 def atomic_swap_8 : PatFrag<(ops node:$ptr, node:$inc),
790 (atomic_swap node:$ptr, node:$inc), [{
791 if (AtomicSDNode* V = dyn_cast<AtomicSDNode>(N))
792 return V->getVT() == MVT::i8;
795 def atomic_swap_16 : PatFrag<(ops node:$ptr, node:$inc),
796 (atomic_swap node:$ptr, node:$inc), [{
797 if (AtomicSDNode* V = dyn_cast<AtomicSDNode>(N))
798 return V->getVT() == MVT::i16;
801 def atomic_swap_32 : PatFrag<(ops node:$ptr, node:$inc),
802 (atomic_swap node:$ptr, node:$inc), [{
803 if (AtomicSDNode* V = dyn_cast<AtomicSDNode>(N))
804 return V->getVT() == MVT::i32;
807 def atomic_swap_64 : PatFrag<(ops node:$ptr, node:$inc),
808 (atomic_swap node:$ptr, node:$inc), [{
809 if (AtomicSDNode* V = dyn_cast<AtomicSDNode>(N))
810 return V->getVT() == MVT::i64;
816 // setcc convenience fragments.
817 def setoeq : PatFrag<(ops node:$lhs, node:$rhs),
818 (setcc node:$lhs, node:$rhs, SETOEQ)>;
819 def setogt : PatFrag<(ops node:$lhs, node:$rhs),
820 (setcc node:$lhs, node:$rhs, SETOGT)>;
821 def setoge : PatFrag<(ops node:$lhs, node:$rhs),
822 (setcc node:$lhs, node:$rhs, SETOGE)>;
823 def setolt : PatFrag<(ops node:$lhs, node:$rhs),
824 (setcc node:$lhs, node:$rhs, SETOLT)>;
825 def setole : PatFrag<(ops node:$lhs, node:$rhs),
826 (setcc node:$lhs, node:$rhs, SETOLE)>;
827 def setone : PatFrag<(ops node:$lhs, node:$rhs),
828 (setcc node:$lhs, node:$rhs, SETONE)>;
829 def seto : PatFrag<(ops node:$lhs, node:$rhs),
830 (setcc node:$lhs, node:$rhs, SETO)>;
831 def setuo : PatFrag<(ops node:$lhs, node:$rhs),
832 (setcc node:$lhs, node:$rhs, SETUO)>;
833 def setueq : PatFrag<(ops node:$lhs, node:$rhs),
834 (setcc node:$lhs, node:$rhs, SETUEQ)>;
835 def setugt : PatFrag<(ops node:$lhs, node:$rhs),
836 (setcc node:$lhs, node:$rhs, SETUGT)>;
837 def setuge : PatFrag<(ops node:$lhs, node:$rhs),
838 (setcc node:$lhs, node:$rhs, SETUGE)>;
839 def setult : PatFrag<(ops node:$lhs, node:$rhs),
840 (setcc node:$lhs, node:$rhs, SETULT)>;
841 def setule : PatFrag<(ops node:$lhs, node:$rhs),
842 (setcc node:$lhs, node:$rhs, SETULE)>;
843 def setune : PatFrag<(ops node:$lhs, node:$rhs),
844 (setcc node:$lhs, node:$rhs, SETUNE)>;
845 def seteq : PatFrag<(ops node:$lhs, node:$rhs),
846 (setcc node:$lhs, node:$rhs, SETEQ)>;
847 def setgt : PatFrag<(ops node:$lhs, node:$rhs),
848 (setcc node:$lhs, node:$rhs, SETGT)>;
849 def setge : PatFrag<(ops node:$lhs, node:$rhs),
850 (setcc node:$lhs, node:$rhs, SETGE)>;
851 def setlt : PatFrag<(ops node:$lhs, node:$rhs),
852 (setcc node:$lhs, node:$rhs, SETLT)>;
853 def setle : PatFrag<(ops node:$lhs, node:$rhs),
854 (setcc node:$lhs, node:$rhs, SETLE)>;
855 def setne : PatFrag<(ops node:$lhs, node:$rhs),
856 (setcc node:$lhs, node:$rhs, SETNE)>;
858 //===----------------------------------------------------------------------===//
859 // Selection DAG Pattern Support.
861 // Patterns are what are actually matched against the target-flavored
862 // instruction selection DAG. Instructions defined by the target implicitly
863 // define patterns in most cases, but patterns can also be explicitly added when
864 // an operation is defined by a sequence of instructions (e.g. loading a large
865 // immediate value on RISC targets that do not support immediates as large as
869 class Pattern<dag patternToMatch, list<dag> resultInstrs> {
870 dag PatternToMatch = patternToMatch;
871 list<dag> ResultInstrs = resultInstrs;
872 list<Predicate> Predicates = []; // See class Instruction in Target.td.
873 int AddedComplexity = 0; // See class Instruction in Target.td.
876 // Pat - A simple (but common) form of a pattern, which produces a simple result
877 // not needing a full list.
878 class Pat<dag pattern, dag result> : Pattern<pattern, [result]>;
880 //===----------------------------------------------------------------------===//
881 // Complex pattern definitions.
885 // Pass the parent Operand as root to CP function rather
886 // than the root of the sub-DAG
887 def CPAttrParentAsRoot : CPAttribute;
889 // Complex patterns, e.g. X86 addressing mode, requires pattern matching code
890 // in C++. NumOperands is the number of operands returned by the select function;
891 // SelectFunc is the name of the function used to pattern match the max. pattern;
892 // RootNodes are the list of possible root nodes of the sub-dags to match.
893 // e.g. X86 addressing mode - def addr : ComplexPattern<4, "SelectAddr", [add]>;
895 class ComplexPattern<ValueType ty, int numops, string fn,
896 list<SDNode> roots = [], list<SDNodeProperty> props = [],
897 list<CPAttribute> attrs = []> {
899 int NumOperands = numops;
900 string SelectFunc = fn;
901 list<SDNode> RootNodes = roots;
902 list<SDNodeProperty> Properties = props;
903 list<CPAttribute> Attributes = attrs;
906 //===----------------------------------------------------------------------===//
909 def SDT_dwarf_loc : SDTypeProfile<0, 3,
910 [SDTCisInt<0>, SDTCisInt<1>, SDTCisInt<2>]>;
911 def dwarf_loc : SDNode<"ISD::DEBUG_LOC", SDT_dwarf_loc,[SDNPHasChain]>;