1 //===- TargetSelectionDAG.td - Common code for DAG isels ---*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the target-independent interfaces used by SelectionDAG
11 // instruction selection generators.
13 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
16 // Selection DAG Type Constraint definitions.
18 // Note that the semantics of these constraints are hard coded into tblgen. To
19 // modify or add constraints, you have to hack tblgen.
22 class SDTypeConstraint<int opnum> {
23 int OperandNum = opnum;
26 // SDTCisVT - The specified operand has exactly this VT.
27 class SDTCisVT<int OpNum, ValueType vt> : SDTypeConstraint<OpNum> {
31 class SDTCisPtrTy<int OpNum> : SDTypeConstraint<OpNum>;
33 // SDTCisInt - The specified operand is has integer type.
34 class SDTCisInt<int OpNum> : SDTypeConstraint<OpNum>;
36 // SDTCisFP - The specified operand is has floating point type.
37 class SDTCisFP<int OpNum> : SDTypeConstraint<OpNum>;
39 // SDTCisSameAs - The two specified operands have identical types.
40 class SDTCisSameAs<int OpNum, int OtherOp> : SDTypeConstraint<OpNum> {
41 int OtherOperandNum = OtherOp;
44 // SDTCisVTSmallerThanOp - The specified operand is a VT SDNode, and its type is
45 // smaller than the 'Other' operand.
46 class SDTCisVTSmallerThanOp<int OpNum, int OtherOp> : SDTypeConstraint<OpNum> {
47 int OtherOperandNum = OtherOp;
50 class SDTCisOpSmallerThanOp<int SmallOp, int BigOp> : SDTypeConstraint<SmallOp>{
51 int BigOperandNum = BigOp;
54 /// SDTCisIntVectorOfSameSize - This indicates that ThisOp and OtherOp are
55 /// vector types, and that ThisOp is the result of
56 /// MVT::getIntVectorWithNumElements with the number of elements that ThisOp
58 class SDTCisIntVectorOfSameSize<int ThisOp, int OtherOp>
59 : SDTypeConstraint<ThisOp> {
60 int OtherOpNum = OtherOp;
63 /// SDTCisEltOfVec - This indicates that ThisOp is a scalar type of the same
64 /// type as the element type of OtherOp, which is a vector type.
65 class SDTCisEltOfVec<int ThisOp, int OtherOp>
66 : SDTypeConstraint<ThisOp> {
67 int OtherOpNum = OtherOp;
70 //===----------------------------------------------------------------------===//
71 // Selection DAG Type Profile definitions.
73 // These use the constraints defined above to describe the type requirements of
74 // the various nodes. These are not hard coded into tblgen, allowing targets to
75 // add their own if needed.
78 // SDTypeProfile - This profile describes the type requirements of a Selection
80 class SDTypeProfile<int numresults, int numoperands,
81 list<SDTypeConstraint> constraints> {
82 int NumResults = numresults;
83 int NumOperands = numoperands;
84 list<SDTypeConstraint> Constraints = constraints;
88 def SDTIntLeaf: SDTypeProfile<1, 0, [SDTCisInt<0>]>; // for 'imm'.
89 def SDTFPLeaf : SDTypeProfile<1, 0, [SDTCisFP<0>]>; // for 'fpimm'.
90 def SDTPtrLeaf: SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>; // for '&g'.
91 def SDTOther : SDTypeProfile<1, 0, [SDTCisVT<0, OtherVT>]>; // for 'vt'.
92 def SDTUNDEF : SDTypeProfile<1, 0, []>; // for 'undef'.
93 def SDTUnaryOp : SDTypeProfile<1, 1, []>; // bitconvert
95 def SDTIntBinOp : SDTypeProfile<1, 2, [ // add, and, or, xor, udiv, etc.
96 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<0>
98 def SDTIntShiftOp : SDTypeProfile<1, 2, [ // shl, sra, srl
99 SDTCisSameAs<0, 1>, SDTCisInt<0>, SDTCisInt<2>
101 def SDTFPBinOp : SDTypeProfile<1, 2, [ // fadd, fmul, etc.
102 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisFP<0>
104 def SDTFPSignOp : SDTypeProfile<1, 2, [ // fcopysign.
105 SDTCisSameAs<0, 1>, SDTCisFP<0>, SDTCisFP<2>
107 def SDTFPTernaryOp : SDTypeProfile<1, 3, [ // fmadd, fnmsub, etc.
108 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>, SDTCisFP<0>
110 def SDTIntUnaryOp : SDTypeProfile<1, 1, [ // ctlz
111 SDTCisSameAs<0, 1>, SDTCisInt<0>
113 def SDTIntExtendOp : SDTypeProfile<1, 1, [ // sext, zext, anyext
114 SDTCisInt<0>, SDTCisInt<1>, SDTCisOpSmallerThanOp<1, 0>
116 def SDTIntTruncOp : SDTypeProfile<1, 1, [ // trunc
117 SDTCisInt<0>, SDTCisInt<1>, SDTCisOpSmallerThanOp<0, 1>
119 def SDTFPUnaryOp : SDTypeProfile<1, 1, [ // fneg, fsqrt, etc
120 SDTCisSameAs<0, 1>, SDTCisFP<0>
122 def SDTFPRoundOp : SDTypeProfile<1, 1, [ // fround
123 SDTCisFP<0>, SDTCisFP<1>, SDTCisOpSmallerThanOp<0, 1>
125 def SDTFPExtendOp : SDTypeProfile<1, 1, [ // fextend
126 SDTCisFP<0>, SDTCisFP<1>, SDTCisOpSmallerThanOp<1, 0>
128 def SDTIntToFPOp : SDTypeProfile<1, 1, [ // [su]int_to_fp
129 SDTCisFP<0>, SDTCisInt<1>
131 def SDTFPToIntOp : SDTypeProfile<1, 1, [ // fp_to_[su]int
132 SDTCisInt<0>, SDTCisFP<1>
134 def SDTExtInreg : SDTypeProfile<1, 2, [ // sext_inreg
135 SDTCisSameAs<0, 1>, SDTCisInt<0>, SDTCisVT<2, OtherVT>,
136 SDTCisVTSmallerThanOp<2, 1>
139 def SDTSetCC : SDTypeProfile<1, 3, [ // setcc
140 SDTCisInt<0>, SDTCisSameAs<1, 2>, SDTCisVT<3, OtherVT>
143 def SDTSelect : SDTypeProfile<1, 3, [ // select
144 SDTCisInt<1>, SDTCisSameAs<0, 2>, SDTCisSameAs<2, 3>
147 def SDTSelectCC : SDTypeProfile<1, 5, [ // select_cc
148 SDTCisSameAs<1, 2>, SDTCisSameAs<3, 4>, SDTCisSameAs<0, 3>,
152 def SDTBr : SDTypeProfile<0, 1, [ // br
156 def SDTBrcond : SDTypeProfile<0, 2, [ // brcond
157 SDTCisInt<0>, SDTCisVT<1, OtherVT>
160 def SDTBrind : SDTypeProfile<0, 1, [ // brind
164 def SDTNone : SDTypeProfile<0, 0, []>; // ret, trap
166 def SDTLoad : SDTypeProfile<1, 1, [ // load
170 def SDTStore : SDTypeProfile<0, 2, [ // store
174 def SDTIStore : SDTypeProfile<1, 3, [ // indexed store
175 SDTCisSameAs<0, 2>, SDTCisPtrTy<0>, SDTCisPtrTy<3>
178 def SDTVecShuffle : SDTypeProfile<1, 3, [
179 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisIntVectorOfSameSize<3, 0>
181 def SDTVecExtract : SDTypeProfile<1, 2, [ // vector extract
182 SDTCisEltOfVec<0, 1>, SDTCisPtrTy<2>
184 def SDTVecInsert : SDTypeProfile<1, 2, [ // vector insert
185 SDTCisEltOfVec<1, 0>, SDTCisPtrTy<2>
188 class SDCallSeqStart<list<SDTypeConstraint> constraints> :
189 SDTypeProfile<0, 1, constraints>;
190 class SDCallSeqEnd<list<SDTypeConstraint> constraints> :
191 SDTypeProfile<0, 2, constraints>;
193 //===----------------------------------------------------------------------===//
194 // Selection DAG Node Properties.
196 // Note: These are hard coded into tblgen.
198 class SDNodeProperty;
199 def SDNPCommutative : SDNodeProperty; // X op Y == Y op X
200 def SDNPAssociative : SDNodeProperty; // (X op Y) op Z == X op (Y op Z)
201 def SDNPHasChain : SDNodeProperty; // R/W chain operand and result
202 def SDNPOutFlag : SDNodeProperty; // Write a flag result
203 def SDNPInFlag : SDNodeProperty; // Read a flag operand
204 def SDNPOptInFlag : SDNodeProperty; // Optionally read a flag operand
205 def SDNPMayStore : SDNodeProperty; // May write to memory, sets 'mayStore'.
206 def SDNPMayLoad : SDNodeProperty; // May read memory, sets 'mayLoad'.
207 def SDNPSideEffect : SDNodeProperty; // Sets 'HasUnmodelledSideEffects'.
209 //===----------------------------------------------------------------------===//
210 // Selection DAG Node definitions.
212 class SDNode<string opcode, SDTypeProfile typeprof,
213 list<SDNodeProperty> props = [], string sdclass = "SDNode"> {
214 string Opcode = opcode;
215 string SDClass = sdclass;
216 list<SDNodeProperty> Properties = props;
217 SDTypeProfile TypeProfile = typeprof;
226 def imm : SDNode<"ISD::Constant" , SDTIntLeaf , [], "ConstantSDNode">;
227 def fpimm : SDNode<"ISD::TargetConstantFP",
228 SDTFPLeaf, [], "ConstantFPSDNode">;
229 def vt : SDNode<"ISD::VALUETYPE" , SDTOther , [], "VTSDNode">;
230 def bb : SDNode<"ISD::BasicBlock", SDTOther , [], "BasicBlockSDNode">;
231 def cond : SDNode<"ISD::CONDCODE" , SDTOther , [], "CondCodeSDNode">;
232 def undef : SDNode<"ISD::UNDEF" , SDTUNDEF , []>;
233 def globaladdr : SDNode<"ISD::GlobalAddress", SDTPtrLeaf, [],
234 "GlobalAddressSDNode">;
235 def tglobaladdr : SDNode<"ISD::TargetGlobalAddress", SDTPtrLeaf, [],
236 "GlobalAddressSDNode">;
237 def globaltlsaddr : SDNode<"ISD::GlobalTLSAddress", SDTPtrLeaf, [],
238 "GlobalAddressSDNode">;
239 def tglobaltlsaddr : SDNode<"ISD::TargetGlobalTLSAddress", SDTPtrLeaf, [],
240 "GlobalAddressSDNode">;
241 def constpool : SDNode<"ISD::ConstantPool", SDTPtrLeaf, [],
242 "ConstantPoolSDNode">;
243 def tconstpool : SDNode<"ISD::TargetConstantPool", SDTPtrLeaf, [],
244 "ConstantPoolSDNode">;
245 def jumptable : SDNode<"ISD::JumpTable", SDTPtrLeaf, [],
247 def tjumptable : SDNode<"ISD::TargetJumpTable", SDTPtrLeaf, [],
249 def frameindex : SDNode<"ISD::FrameIndex", SDTPtrLeaf, [],
251 def tframeindex : SDNode<"ISD::TargetFrameIndex", SDTPtrLeaf, [],
253 def externalsym : SDNode<"ISD::ExternalSymbol", SDTPtrLeaf, [],
254 "ExternalSymbolSDNode">;
255 def texternalsym: SDNode<"ISD::TargetExternalSymbol", SDTPtrLeaf, [],
256 "ExternalSymbolSDNode">;
258 def add : SDNode<"ISD::ADD" , SDTIntBinOp ,
259 [SDNPCommutative, SDNPAssociative]>;
260 def sub : SDNode<"ISD::SUB" , SDTIntBinOp>;
261 def mul : SDNode<"ISD::MUL" , SDTIntBinOp,
262 [SDNPCommutative, SDNPAssociative]>;
263 def mulhs : SDNode<"ISD::MULHS" , SDTIntBinOp, [SDNPCommutative]>;
264 def mulhu : SDNode<"ISD::MULHU" , SDTIntBinOp, [SDNPCommutative]>;
265 def sdiv : SDNode<"ISD::SDIV" , SDTIntBinOp>;
266 def udiv : SDNode<"ISD::UDIV" , SDTIntBinOp>;
267 def srem : SDNode<"ISD::SREM" , SDTIntBinOp>;
268 def urem : SDNode<"ISD::UREM" , SDTIntBinOp>;
269 def srl : SDNode<"ISD::SRL" , SDTIntShiftOp>;
270 def sra : SDNode<"ISD::SRA" , SDTIntShiftOp>;
271 def shl : SDNode<"ISD::SHL" , SDTIntShiftOp>;
272 def rotl : SDNode<"ISD::ROTL" , SDTIntShiftOp>;
273 def rotr : SDNode<"ISD::ROTR" , SDTIntShiftOp>;
274 def and : SDNode<"ISD::AND" , SDTIntBinOp,
275 [SDNPCommutative, SDNPAssociative]>;
276 def or : SDNode<"ISD::OR" , SDTIntBinOp,
277 [SDNPCommutative, SDNPAssociative]>;
278 def xor : SDNode<"ISD::XOR" , SDTIntBinOp,
279 [SDNPCommutative, SDNPAssociative]>;
280 def addc : SDNode<"ISD::ADDC" , SDTIntBinOp,
281 [SDNPCommutative, SDNPOutFlag]>;
282 def adde : SDNode<"ISD::ADDE" , SDTIntBinOp,
283 [SDNPCommutative, SDNPOutFlag, SDNPInFlag]>;
284 def subc : SDNode<"ISD::SUBC" , SDTIntBinOp,
286 def sube : SDNode<"ISD::SUBE" , SDTIntBinOp,
287 [SDNPOutFlag, SDNPInFlag]>;
289 def sext_inreg : SDNode<"ISD::SIGN_EXTEND_INREG", SDTExtInreg>;
290 def bswap : SDNode<"ISD::BSWAP" , SDTIntUnaryOp>;
291 def ctlz : SDNode<"ISD::CTLZ" , SDTIntUnaryOp>;
292 def cttz : SDNode<"ISD::CTTZ" , SDTIntUnaryOp>;
293 def ctpop : SDNode<"ISD::CTPOP" , SDTIntUnaryOp>;
294 def sext : SDNode<"ISD::SIGN_EXTEND", SDTIntExtendOp>;
295 def zext : SDNode<"ISD::ZERO_EXTEND", SDTIntExtendOp>;
296 def anyext : SDNode<"ISD::ANY_EXTEND" , SDTIntExtendOp>;
297 def trunc : SDNode<"ISD::TRUNCATE" , SDTIntTruncOp>;
298 def bitconvert : SDNode<"ISD::BIT_CONVERT", SDTUnaryOp>;
299 def extractelt : SDNode<"ISD::EXTRACT_VECTOR_ELT", SDTVecExtract>;
300 def insertelt : SDNode<"ISD::INSERT_VECTOR_ELT", SDTVecInsert>;
303 def fadd : SDNode<"ISD::FADD" , SDTFPBinOp, [SDNPCommutative]>;
304 def fsub : SDNode<"ISD::FSUB" , SDTFPBinOp>;
305 def fmul : SDNode<"ISD::FMUL" , SDTFPBinOp, [SDNPCommutative]>;
306 def fdiv : SDNode<"ISD::FDIV" , SDTFPBinOp>;
307 def frem : SDNode<"ISD::FREM" , SDTFPBinOp>;
308 def fabs : SDNode<"ISD::FABS" , SDTFPUnaryOp>;
309 def fneg : SDNode<"ISD::FNEG" , SDTFPUnaryOp>;
310 def fsqrt : SDNode<"ISD::FSQRT" , SDTFPUnaryOp>;
311 def fsin : SDNode<"ISD::FSIN" , SDTFPUnaryOp>;
312 def fcos : SDNode<"ISD::FCOS" , SDTFPUnaryOp>;
314 def fround : SDNode<"ISD::FP_ROUND" , SDTFPRoundOp>;
315 def fextend : SDNode<"ISD::FP_EXTEND" , SDTFPExtendOp>;
316 def fcopysign : SDNode<"ISD::FCOPYSIGN" , SDTFPSignOp>;
318 def sint_to_fp : SDNode<"ISD::SINT_TO_FP" , SDTIntToFPOp>;
319 def uint_to_fp : SDNode<"ISD::UINT_TO_FP" , SDTIntToFPOp>;
320 def fp_to_sint : SDNode<"ISD::FP_TO_SINT" , SDTFPToIntOp>;
321 def fp_to_uint : SDNode<"ISD::FP_TO_UINT" , SDTFPToIntOp>;
323 def setcc : SDNode<"ISD::SETCC" , SDTSetCC>;
324 def select : SDNode<"ISD::SELECT" , SDTSelect>;
325 def selectcc : SDNode<"ISD::SELECT_CC" , SDTSelectCC>;
327 def brcond : SDNode<"ISD::BRCOND" , SDTBrcond, [SDNPHasChain]>;
328 def brind : SDNode<"ISD::BRIND" , SDTBrind, [SDNPHasChain]>;
329 def br : SDNode<"ISD::BR" , SDTBr, [SDNPHasChain]>;
330 def ret : SDNode<"ISD::RET" , SDTNone, [SDNPHasChain]>;
331 def trap : SDNode<"ISD::TRAP" , SDTNone,
332 [SDNPHasChain, SDNPSideEffect]>;
334 // Do not use ld, st directly. Use load, extload, sextload, zextload, store,
335 // and truncst (see below).
336 def ld : SDNode<"ISD::LOAD" , SDTLoad,
337 [SDNPHasChain, SDNPMayLoad]>;
338 def st : SDNode<"ISD::STORE" , SDTStore,
339 [SDNPHasChain, SDNPMayStore]>;
340 def ist : SDNode<"ISD::STORE" , SDTIStore,
341 [SDNPHasChain, SDNPMayStore]>;
343 def vector_shuffle : SDNode<"ISD::VECTOR_SHUFFLE", SDTVecShuffle, []>;
344 def build_vector : SDNode<"ISD::BUILD_VECTOR", SDTypeProfile<1, 0, []>, []>;
345 def scalar_to_vector : SDNode<"ISD::SCALAR_TO_VECTOR", SDTypeProfile<1, 1, []>,
347 def vector_extract : SDNode<"ISD::EXTRACT_VECTOR_ELT",
348 SDTypeProfile<1, 2, [SDTCisPtrTy<2>]>, []>;
349 def vector_insert : SDNode<"ISD::INSERT_VECTOR_ELT",
350 SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisPtrTy<3>]>, []>;
352 def extract_subreg : SDNode<"ISD::EXTRACT_SUBREG",
353 SDTypeProfile<1, 2, []>>;
354 def insert_subreg : SDNode<"ISD::INSERT_SUBREG",
355 SDTypeProfile<1, 3, []>>;
357 // Nodes for intrinsics, you should use the intrinsic itself and let tblgen use
358 // these internally. Don't reference these directly.
359 def intrinsic_void : SDNode<"ISD::INTRINSIC_VOID",
360 SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>,
362 def intrinsic_w_chain : SDNode<"ISD::INTRINSIC_W_CHAIN",
363 SDTypeProfile<1, -1, [SDTCisPtrTy<1>]>,
365 def intrinsic_wo_chain : SDNode<"ISD::INTRINSIC_WO_CHAIN",
366 SDTypeProfile<1, -1, [SDTCisPtrTy<1>]>, []>;
369 //===----------------------------------------------------------------------===//
370 // Selection DAG Condition Codes
372 class CondCode; // ISD::CondCode enums
373 def SETOEQ : CondCode; def SETOGT : CondCode;
374 def SETOGE : CondCode; def SETOLT : CondCode; def SETOLE : CondCode;
375 def SETONE : CondCode; def SETO : CondCode; def SETUO : CondCode;
376 def SETUEQ : CondCode; def SETUGT : CondCode; def SETUGE : CondCode;
377 def SETULT : CondCode; def SETULE : CondCode; def SETUNE : CondCode;
379 def SETEQ : CondCode; def SETGT : CondCode; def SETGE : CondCode;
380 def SETLT : CondCode; def SETLE : CondCode; def SETNE : CondCode;
383 //===----------------------------------------------------------------------===//
384 // Selection DAG Node Transformation Functions.
386 // This mechanism allows targets to manipulate nodes in the output DAG once a
387 // match has been formed. This is typically used to manipulate immediate
390 class SDNodeXForm<SDNode opc, code xformFunction> {
392 code XFormFunction = xformFunction;
395 def NOOP_SDNodeXForm : SDNodeXForm<imm, [{}]>;
398 //===----------------------------------------------------------------------===//
399 // Selection DAG Pattern Fragments.
401 // Pattern fragments are reusable chunks of dags that match specific things.
402 // They can take arguments and have C++ predicates that control whether they
403 // match. They are intended to make the patterns for common instructions more
404 // compact and readable.
407 /// PatFrag - Represents a pattern fragment. This can match something on the
408 /// DAG, frame a single node to multiply nested other fragments.
410 class PatFrag<dag ops, dag frag, code pred = [{}],
411 SDNodeXForm xform = NOOP_SDNodeXForm> {
414 code Predicate = pred;
415 SDNodeXForm OperandTransform = xform;
418 // PatLeaf's are pattern fragments that have no operands. This is just a helper
419 // to define immediates and other common things concisely.
420 class PatLeaf<dag frag, code pred = [{}], SDNodeXForm xform = NOOP_SDNodeXForm>
421 : PatFrag<(ops), frag, pred, xform>;
425 def vtInt : PatLeaf<(vt), [{ return MVT::isInteger(N->getVT()); }]>;
426 def vtFP : PatLeaf<(vt), [{ return MVT::isFloatingPoint(N->getVT()); }]>;
428 def immAllOnes : PatLeaf<(imm), [{ return N->isAllOnesValue(); }]>;
429 def immAllOnesV: PatLeaf<(build_vector), [{
430 return ISD::isBuildVectorAllOnes(N);
432 def immAllOnesV_bc: PatLeaf<(bitconvert), [{
433 return ISD::isBuildVectorAllOnes(N);
435 def immAllZerosV: PatLeaf<(build_vector), [{
436 return ISD::isBuildVectorAllZeros(N);
438 def immAllZerosV_bc: PatLeaf<(bitconvert), [{
439 return ISD::isBuildVectorAllZeros(N);
444 // Other helper fragments.
445 def not : PatFrag<(ops node:$in), (xor node:$in, immAllOnes)>;
446 def vnot : PatFrag<(ops node:$in), (xor node:$in, immAllOnesV)>;
447 def vnot_conv : PatFrag<(ops node:$in), (xor node:$in, immAllOnesV_bc)>;
448 def ineg : PatFrag<(ops node:$in), (sub 0, node:$in)>;
451 def load : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
452 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
453 return LD->getExtensionType() == ISD::NON_EXTLOAD &&
454 LD->getAddressingMode() == ISD::UNINDEXED;
458 // extending load fragments.
459 def extloadi1 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
460 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
461 return LD->getExtensionType() == ISD::EXTLOAD &&
462 LD->getAddressingMode() == ISD::UNINDEXED &&
463 LD->getMemoryVT() == MVT::i1;
466 def extloadi8 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
467 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
468 return LD->getExtensionType() == ISD::EXTLOAD &&
469 LD->getAddressingMode() == ISD::UNINDEXED &&
470 LD->getMemoryVT() == MVT::i8;
473 def extloadi16 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
474 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
475 return LD->getExtensionType() == ISD::EXTLOAD &&
476 LD->getAddressingMode() == ISD::UNINDEXED &&
477 LD->getMemoryVT() == MVT::i16;
480 def extloadi32 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
481 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
482 return LD->getExtensionType() == ISD::EXTLOAD &&
483 LD->getAddressingMode() == ISD::UNINDEXED &&
484 LD->getMemoryVT() == MVT::i32;
487 def extloadf32 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
488 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
489 return LD->getExtensionType() == ISD::EXTLOAD &&
490 LD->getAddressingMode() == ISD::UNINDEXED &&
491 LD->getMemoryVT() == MVT::f32;
494 def extloadf64 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
495 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
496 return LD->getExtensionType() == ISD::EXTLOAD &&
497 LD->getAddressingMode() == ISD::UNINDEXED &&
498 LD->getMemoryVT() == MVT::f64;
502 def sextloadi1 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
503 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
504 return LD->getExtensionType() == ISD::SEXTLOAD &&
505 LD->getAddressingMode() == ISD::UNINDEXED &&
506 LD->getMemoryVT() == MVT::i1;
509 def sextloadi8 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
510 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
511 return LD->getExtensionType() == ISD::SEXTLOAD &&
512 LD->getAddressingMode() == ISD::UNINDEXED &&
513 LD->getMemoryVT() == MVT::i8;
516 def sextloadi16 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
517 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
518 return LD->getExtensionType() == ISD::SEXTLOAD &&
519 LD->getAddressingMode() == ISD::UNINDEXED &&
520 LD->getMemoryVT() == MVT::i16;
523 def sextloadi32 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
524 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
525 return LD->getExtensionType() == ISD::SEXTLOAD &&
526 LD->getAddressingMode() == ISD::UNINDEXED &&
527 LD->getMemoryVT() == MVT::i32;
531 def zextloadi1 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
532 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
533 return LD->getExtensionType() == ISD::ZEXTLOAD &&
534 LD->getAddressingMode() == ISD::UNINDEXED &&
535 LD->getMemoryVT() == MVT::i1;
538 def zextloadi8 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
539 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
540 return LD->getExtensionType() == ISD::ZEXTLOAD &&
541 LD->getAddressingMode() == ISD::UNINDEXED &&
542 LD->getMemoryVT() == MVT::i8;
545 def zextloadi16 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
546 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
547 return LD->getExtensionType() == ISD::ZEXTLOAD &&
548 LD->getAddressingMode() == ISD::UNINDEXED &&
549 LD->getMemoryVT() == MVT::i16;
552 def zextloadi32 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
553 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
554 return LD->getExtensionType() == ISD::ZEXTLOAD &&
555 LD->getAddressingMode() == ISD::UNINDEXED &&
556 LD->getMemoryVT() == MVT::i32;
561 def store : PatFrag<(ops node:$val, node:$ptr),
562 (st node:$val, node:$ptr), [{
563 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
564 return !ST->isTruncatingStore() &&
565 ST->getAddressingMode() == ISD::UNINDEXED;
569 // truncstore fragments.
570 def truncstorei8 : PatFrag<(ops node:$val, node:$ptr),
571 (st node:$val, node:$ptr), [{
572 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
573 return ST->isTruncatingStore() && ST->getMemoryVT() == MVT::i8 &&
574 ST->getAddressingMode() == ISD::UNINDEXED;
577 def truncstorei16 : PatFrag<(ops node:$val, node:$ptr),
578 (st node:$val, node:$ptr), [{
579 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
580 return ST->isTruncatingStore() && ST->getMemoryVT() == MVT::i16 &&
581 ST->getAddressingMode() == ISD::UNINDEXED;
584 def truncstorei32 : PatFrag<(ops node:$val, node:$ptr),
585 (st node:$val, node:$ptr), [{
586 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
587 return ST->isTruncatingStore() && ST->getMemoryVT() == MVT::i32 &&
588 ST->getAddressingMode() == ISD::UNINDEXED;
591 def truncstoref32 : PatFrag<(ops node:$val, node:$ptr),
592 (st node:$val, node:$ptr), [{
593 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
594 return ST->isTruncatingStore() && ST->getMemoryVT() == MVT::f32 &&
595 ST->getAddressingMode() == ISD::UNINDEXED;
598 def truncstoref64 : PatFrag<(ops node:$val, node:$ptr),
599 (st node:$val, node:$ptr), [{
600 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
601 return ST->isTruncatingStore() && ST->getMemoryVT() == MVT::f64 &&
602 ST->getAddressingMode() == ISD::UNINDEXED;
606 // indexed store fragments.
607 def pre_store : PatFrag<(ops node:$val, node:$base, node:$offset),
608 (ist node:$val, node:$base, node:$offset), [{
609 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
610 ISD::MemIndexedMode AM = ST->getAddressingMode();
611 return (AM == ISD::PRE_INC || AM == ISD::PRE_DEC) &&
612 !ST->isTruncatingStore();
617 def pre_truncsti1 : PatFrag<(ops node:$val, node:$base, node:$offset),
618 (ist node:$val, node:$base, node:$offset), [{
619 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
620 ISD::MemIndexedMode AM = ST->getAddressingMode();
621 return (AM == ISD::PRE_INC || AM == ISD::PRE_DEC) &&
622 ST->isTruncatingStore() && ST->getMemoryVT() == MVT::i1;
626 def pre_truncsti8 : PatFrag<(ops node:$val, node:$base, node:$offset),
627 (ist node:$val, node:$base, node:$offset), [{
628 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
629 ISD::MemIndexedMode AM = ST->getAddressingMode();
630 return (AM == ISD::PRE_INC || AM == ISD::PRE_DEC) &&
631 ST->isTruncatingStore() && ST->getMemoryVT() == MVT::i8;
635 def pre_truncsti16 : PatFrag<(ops node:$val, node:$base, node:$offset),
636 (ist node:$val, node:$base, node:$offset), [{
637 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
638 ISD::MemIndexedMode AM = ST->getAddressingMode();
639 return (AM == ISD::PRE_INC || AM == ISD::PRE_DEC) &&
640 ST->isTruncatingStore() && ST->getMemoryVT() == MVT::i16;
644 def pre_truncsti32 : PatFrag<(ops node:$val, node:$base, node:$offset),
645 (ist node:$val, node:$base, node:$offset), [{
646 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
647 ISD::MemIndexedMode AM = ST->getAddressingMode();
648 return (AM == ISD::PRE_INC || AM == ISD::PRE_DEC) &&
649 ST->isTruncatingStore() && ST->getMemoryVT() == MVT::i32;
653 def pre_truncstf32 : PatFrag<(ops node:$val, node:$base, node:$offset),
654 (ist node:$val, node:$base, node:$offset), [{
655 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
656 ISD::MemIndexedMode AM = ST->getAddressingMode();
657 return (AM == ISD::PRE_INC || AM == ISD::PRE_DEC) &&
658 ST->isTruncatingStore() && ST->getMemoryVT() == MVT::f32;
663 def post_store : PatFrag<(ops node:$val, node:$ptr, node:$offset),
664 (ist node:$val, node:$ptr, node:$offset), [{
665 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
666 ISD::MemIndexedMode AM = ST->getAddressingMode();
667 return !ST->isTruncatingStore() &&
668 (AM == ISD::POST_INC || AM == ISD::POST_DEC);
673 def post_truncsti1 : PatFrag<(ops node:$val, node:$base, node:$offset),
674 (ist node:$val, node:$base, node:$offset), [{
675 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
676 ISD::MemIndexedMode AM = ST->getAddressingMode();
677 return (AM == ISD::POST_INC || AM == ISD::POST_DEC) &&
678 ST->isTruncatingStore() && ST->getMemoryVT() == MVT::i1;
682 def post_truncsti8 : PatFrag<(ops node:$val, node:$base, node:$offset),
683 (ist node:$val, node:$base, node:$offset), [{
684 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
685 ISD::MemIndexedMode AM = ST->getAddressingMode();
686 return (AM == ISD::POST_INC || AM == ISD::POST_DEC) &&
687 ST->isTruncatingStore() && ST->getMemoryVT() == MVT::i8;
691 def post_truncsti16 : PatFrag<(ops node:$val, node:$base, node:$offset),
692 (ist node:$val, node:$base, node:$offset), [{
693 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
694 ISD::MemIndexedMode AM = ST->getAddressingMode();
695 return (AM == ISD::POST_INC || AM == ISD::POST_DEC) &&
696 ST->isTruncatingStore() && ST->getMemoryVT() == MVT::i16;
700 def post_truncsti32 : PatFrag<(ops node:$val, node:$base, node:$offset),
701 (ist node:$val, node:$base, node:$offset), [{
702 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
703 ISD::MemIndexedMode AM = ST->getAddressingMode();
704 return (AM == ISD::POST_INC || AM == ISD::POST_DEC) &&
705 ST->isTruncatingStore() && ST->getMemoryVT() == MVT::i32;
709 def post_truncstf32 : PatFrag<(ops node:$val, node:$base, node:$offset),
710 (ist node:$val, node:$base, node:$offset), [{
711 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
712 ISD::MemIndexedMode AM = ST->getAddressingMode();
713 return (AM == ISD::POST_INC || AM == ISD::POST_DEC) &&
714 ST->isTruncatingStore() && ST->getMemoryVT() == MVT::f32;
719 // setcc convenience fragments.
720 def setoeq : PatFrag<(ops node:$lhs, node:$rhs),
721 (setcc node:$lhs, node:$rhs, SETOEQ)>;
722 def setogt : PatFrag<(ops node:$lhs, node:$rhs),
723 (setcc node:$lhs, node:$rhs, SETOGT)>;
724 def setoge : PatFrag<(ops node:$lhs, node:$rhs),
725 (setcc node:$lhs, node:$rhs, SETOGE)>;
726 def setolt : PatFrag<(ops node:$lhs, node:$rhs),
727 (setcc node:$lhs, node:$rhs, SETOLT)>;
728 def setole : PatFrag<(ops node:$lhs, node:$rhs),
729 (setcc node:$lhs, node:$rhs, SETOLE)>;
730 def setone : PatFrag<(ops node:$lhs, node:$rhs),
731 (setcc node:$lhs, node:$rhs, SETONE)>;
732 def seto : PatFrag<(ops node:$lhs, node:$rhs),
733 (setcc node:$lhs, node:$rhs, SETO)>;
734 def setuo : PatFrag<(ops node:$lhs, node:$rhs),
735 (setcc node:$lhs, node:$rhs, SETUO)>;
736 def setueq : PatFrag<(ops node:$lhs, node:$rhs),
737 (setcc node:$lhs, node:$rhs, SETUEQ)>;
738 def setugt : PatFrag<(ops node:$lhs, node:$rhs),
739 (setcc node:$lhs, node:$rhs, SETUGT)>;
740 def setuge : PatFrag<(ops node:$lhs, node:$rhs),
741 (setcc node:$lhs, node:$rhs, SETUGE)>;
742 def setult : PatFrag<(ops node:$lhs, node:$rhs),
743 (setcc node:$lhs, node:$rhs, SETULT)>;
744 def setule : PatFrag<(ops node:$lhs, node:$rhs),
745 (setcc node:$lhs, node:$rhs, SETULE)>;
746 def setune : PatFrag<(ops node:$lhs, node:$rhs),
747 (setcc node:$lhs, node:$rhs, SETUNE)>;
748 def seteq : PatFrag<(ops node:$lhs, node:$rhs),
749 (setcc node:$lhs, node:$rhs, SETEQ)>;
750 def setgt : PatFrag<(ops node:$lhs, node:$rhs),
751 (setcc node:$lhs, node:$rhs, SETGT)>;
752 def setge : PatFrag<(ops node:$lhs, node:$rhs),
753 (setcc node:$lhs, node:$rhs, SETGE)>;
754 def setlt : PatFrag<(ops node:$lhs, node:$rhs),
755 (setcc node:$lhs, node:$rhs, SETLT)>;
756 def setle : PatFrag<(ops node:$lhs, node:$rhs),
757 (setcc node:$lhs, node:$rhs, SETLE)>;
758 def setne : PatFrag<(ops node:$lhs, node:$rhs),
759 (setcc node:$lhs, node:$rhs, SETNE)>;
761 //===----------------------------------------------------------------------===//
762 // Selection DAG Pattern Support.
764 // Patterns are what are actually matched against the target-flavored
765 // instruction selection DAG. Instructions defined by the target implicitly
766 // define patterns in most cases, but patterns can also be explicitly added when
767 // an operation is defined by a sequence of instructions (e.g. loading a large
768 // immediate value on RISC targets that do not support immediates as large as
772 class Pattern<dag patternToMatch, list<dag> resultInstrs> {
773 dag PatternToMatch = patternToMatch;
774 list<dag> ResultInstrs = resultInstrs;
775 list<Predicate> Predicates = []; // See class Instruction in Target.td.
776 int AddedComplexity = 0; // See class Instruction in Target.td.
779 // Pat - A simple (but common) form of a pattern, which produces a simple result
780 // not needing a full list.
781 class Pat<dag pattern, dag result> : Pattern<pattern, [result]>;
783 //===----------------------------------------------------------------------===//
784 // Complex pattern definitions.
788 // Pass the parent Operand as root to CP function rather
789 // than the root of the sub-DAG
790 def CPAttrParentAsRoot : CPAttribute;
792 // Complex patterns, e.g. X86 addressing mode, requires pattern matching code
793 // in C++. NumOperands is the number of operands returned by the select function;
794 // SelectFunc is the name of the function used to pattern match the max. pattern;
795 // RootNodes are the list of possible root nodes of the sub-dags to match.
796 // e.g. X86 addressing mode - def addr : ComplexPattern<4, "SelectAddr", [add]>;
798 class ComplexPattern<ValueType ty, int numops, string fn,
799 list<SDNode> roots = [], list<SDNodeProperty> props = [],
800 list<CPAttribute> attrs = []> {
802 int NumOperands = numops;
803 string SelectFunc = fn;
804 list<SDNode> RootNodes = roots;
805 list<SDNodeProperty> Properties = props;
806 list<CPAttribute> Attributes = attrs;
809 //===----------------------------------------------------------------------===//
812 def SDT_dwarf_loc : SDTypeProfile<0, 3,
813 [SDTCisInt<0>, SDTCisInt<1>, SDTCisInt<2>]>;
814 def dwarf_loc : SDNode<"ISD::DEBUG_LOC", SDT_dwarf_loc,[SDNPHasChain]>;