1 //===- TargetSelectionDAG.td - Common code for DAG isels ---*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the target-independent interfaces used by SelectionDAG
11 // instruction selection generators.
13 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
16 // Selection DAG Type Constraint definitions.
18 // Note that the semantics of these constraints are hard coded into tblgen. To
19 // modify or add constraints, you have to hack tblgen.
22 class SDTypeConstraint<int opnum> {
23 int OperandNum = opnum;
26 // SDTCisVT - The specified operand has exactly this VT.
27 class SDTCisVT<int OpNum, ValueType vt> : SDTypeConstraint<OpNum> {
31 class SDTCisPtrTy<int OpNum> : SDTypeConstraint<OpNum>;
33 // SDTCisInt - The specified operand is has integer type.
34 class SDTCisInt<int OpNum> : SDTypeConstraint<OpNum>;
36 // SDTCisFP - The specified operand is has floating point type.
37 class SDTCisFP<int OpNum> : SDTypeConstraint<OpNum>;
39 // SDTCisSameAs - The two specified operands have identical types.
40 class SDTCisSameAs<int OpNum, int OtherOp> : SDTypeConstraint<OpNum> {
41 int OtherOperandNum = OtherOp;
44 // SDTCisVTSmallerThanOp - The specified operand is a VT SDNode, and its type is
45 // smaller than the 'Other' operand.
46 class SDTCisVTSmallerThanOp<int OpNum, int OtherOp> : SDTypeConstraint<OpNum> {
47 int OtherOperandNum = OtherOp;
50 class SDTCisOpSmallerThanOp<int SmallOp, int BigOp> : SDTypeConstraint<SmallOp>{
51 int BigOperandNum = BigOp;
54 /// SDTCisIntVectorOfSameSize - This indicates that ThisOp and OtherOp are
55 /// vector types, and that ThisOp is the result of
56 /// MVT::getIntVectorWithNumElements with the number of elements
58 class SDTCisIntVectorOfSameSize<int ThisOp, int OtherOp>
59 : SDTypeConstraint<ThisOp> {
60 int OtherOpNum = OtherOp;
63 /// SDTCisEltOfVec - This indicates that ThisOp is a scalar type of the same
64 /// type as the element type of OtherOp, which is a vector type.
65 class SDTCisEltOfVec<int ThisOp, int OtherOp>
66 : SDTypeConstraint<ThisOp> {
67 int OtherOpNum = OtherOp;
70 //===----------------------------------------------------------------------===//
71 // Selection DAG Type Profile definitions.
73 // These use the constraints defined above to describe the type requirements of
74 // the various nodes. These are not hard coded into tblgen, allowing targets to
75 // add their own if needed.
78 // SDTypeProfile - This profile describes the type requirements of a Selection
80 class SDTypeProfile<int numresults, int numoperands,
81 list<SDTypeConstraint> constraints> {
82 int NumResults = numresults;
83 int NumOperands = numoperands;
84 list<SDTypeConstraint> Constraints = constraints;
88 def SDTIntLeaf: SDTypeProfile<1, 0, [SDTCisInt<0>]>; // for 'imm'.
89 def SDTFPLeaf : SDTypeProfile<1, 0, [SDTCisFP<0>]>; // for 'fpimm'.
90 def SDTPtrLeaf: SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>; // for '&g'.
91 def SDTOther : SDTypeProfile<1, 0, [SDTCisVT<0, OtherVT>]>; // for 'vt'.
92 def SDTUNDEF : SDTypeProfile<1, 0, []>; // for 'undef'.
93 def SDTUnaryOp : SDTypeProfile<1, 1, []>; // bitconvert
95 def SDTIntBinOp : SDTypeProfile<1, 2, [ // add, and, or, xor, udiv, etc.
96 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<0>
98 def SDTIntShiftOp : SDTypeProfile<1, 2, [ // shl, sra, srl
99 SDTCisSameAs<0, 1>, SDTCisInt<0>, SDTCisInt<2>
101 def SDTFPBinOp : SDTypeProfile<1, 2, [ // fadd, fmul, etc.
102 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisFP<0>
104 def SDTFPSignOp : SDTypeProfile<1, 2, [ // fcopysign.
105 SDTCisSameAs<0, 1>, SDTCisFP<0>, SDTCisFP<2>
107 def SDTFPTernaryOp : SDTypeProfile<1, 3, [ // fmadd, fnmsub, etc.
108 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>, SDTCisFP<0>
110 def SDTIntUnaryOp : SDTypeProfile<1, 1, [ // ctlz
111 SDTCisSameAs<0, 1>, SDTCisInt<0>
113 def SDTIntExtendOp : SDTypeProfile<1, 1, [ // sext, zext, anyext
114 SDTCisInt<0>, SDTCisInt<1>, SDTCisOpSmallerThanOp<1, 0>
116 def SDTIntTruncOp : SDTypeProfile<1, 1, [ // trunc
117 SDTCisInt<0>, SDTCisInt<1>, SDTCisOpSmallerThanOp<0, 1>
119 def SDTFPUnaryOp : SDTypeProfile<1, 1, [ // fneg, fsqrt, etc
120 SDTCisSameAs<0, 1>, SDTCisFP<0>
122 def SDTFPRoundOp : SDTypeProfile<1, 1, [ // fround
123 SDTCisFP<0>, SDTCisFP<1>, SDTCisOpSmallerThanOp<0, 1>
125 def SDTFPExtendOp : SDTypeProfile<1, 1, [ // fextend
126 SDTCisFP<0>, SDTCisFP<1>, SDTCisOpSmallerThanOp<1, 0>
128 def SDTIntToFPOp : SDTypeProfile<1, 1, [ // [su]int_to_fp
129 SDTCisFP<0>, SDTCisInt<1>
131 def SDTFPToIntOp : SDTypeProfile<1, 1, [ // fp_to_[su]int
132 SDTCisInt<0>, SDTCisFP<1>
134 def SDTExtInreg : SDTypeProfile<1, 2, [ // sext_inreg
135 SDTCisSameAs<0, 1>, SDTCisInt<0>, SDTCisVT<2, OtherVT>,
136 SDTCisVTSmallerThanOp<2, 1>
139 def SDTSetCC : SDTypeProfile<1, 3, [ // setcc
140 SDTCisInt<0>, SDTCisSameAs<1, 2>, SDTCisVT<3, OtherVT>
143 def SDTSelect : SDTypeProfile<1, 3, [ // select
144 SDTCisInt<1>, SDTCisSameAs<0, 2>, SDTCisSameAs<2, 3>
147 def SDTSelectCC : SDTypeProfile<1, 5, [ // select_cc
148 SDTCisSameAs<1, 2>, SDTCisSameAs<3, 4>, SDTCisSameAs<0, 3>,
152 def SDTBr : SDTypeProfile<0, 1, [ // br
156 def SDTBrcond : SDTypeProfile<0, 2, [ // brcond
157 SDTCisInt<0>, SDTCisVT<1, OtherVT>
160 def SDTBrind : SDTypeProfile<0, 1, [ // brind
164 def SDTNone : SDTypeProfile<0, 0, []>; // ret, trap
166 def SDTLoad : SDTypeProfile<1, 1, [ // load
170 def SDTStore : SDTypeProfile<0, 2, [ // store
174 def SDTIStore : SDTypeProfile<1, 3, [ // indexed store
175 SDTCisSameAs<0, 2>, SDTCisPtrTy<0>, SDTCisPtrTy<3>
178 def SDTVecShuffle : SDTypeProfile<1, 3, [
179 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisIntVectorOfSameSize<3, 0>
181 def SDTVecExtract : SDTypeProfile<1, 2, [ // vector extract
182 SDTCisEltOfVec<0, 1>, SDTCisPtrTy<2>
184 def SDTVecInsert : SDTypeProfile<1, 3, [ // vector insert
185 SDTCisEltOfVec<2, 1>, SDTCisSameAs<0, 1>, SDTCisPtrTy<3>
188 def STDPrefetch : SDTypeProfile<0, 3, [ // prefetch
189 SDTCisPtrTy<0>, SDTCisSameAs<1, 2>, SDTCisInt<1>
192 def STDMemBarrier : SDTypeProfile<0, 5, [ // memory barier
193 SDTCisSameAs<0,1>, SDTCisSameAs<0,2>, SDTCisSameAs<0,3>, SDTCisSameAs<0,4>,
196 def STDAtomic3 : SDTypeProfile<1, 3, [
197 SDTCisSameAs<0,2>, SDTCisSameAs<0,3>, SDTCisInt<0>, SDTCisPtrTy<1>
199 def STDAtomic2 : SDTypeProfile<1, 2, [
200 SDTCisSameAs<0,2>, SDTCisInt<0>, SDTCisPtrTy<1>
203 class SDCallSeqStart<list<SDTypeConstraint> constraints> :
204 SDTypeProfile<0, 1, constraints>;
205 class SDCallSeqEnd<list<SDTypeConstraint> constraints> :
206 SDTypeProfile<0, 2, constraints>;
208 //===----------------------------------------------------------------------===//
209 // Selection DAG Node Properties.
211 // Note: These are hard coded into tblgen.
213 class SDNodeProperty;
214 def SDNPCommutative : SDNodeProperty; // X op Y == Y op X
215 def SDNPAssociative : SDNodeProperty; // (X op Y) op Z == X op (Y op Z)
216 def SDNPHasChain : SDNodeProperty; // R/W chain operand and result
217 def SDNPOutFlag : SDNodeProperty; // Write a flag result
218 def SDNPInFlag : SDNodeProperty; // Read a flag operand
219 def SDNPOptInFlag : SDNodeProperty; // Optionally read a flag operand
220 def SDNPMayStore : SDNodeProperty; // May write to memory, sets 'mayStore'.
221 def SDNPMayLoad : SDNodeProperty; // May read memory, sets 'mayLoad'.
222 def SDNPSideEffect : SDNodeProperty; // Sets 'HasUnmodelledSideEffects'.
224 //===----------------------------------------------------------------------===//
225 // Selection DAG Node definitions.
227 class SDNode<string opcode, SDTypeProfile typeprof,
228 list<SDNodeProperty> props = [], string sdclass = "SDNode"> {
229 string Opcode = opcode;
230 string SDClass = sdclass;
231 list<SDNodeProperty> Properties = props;
232 SDTypeProfile TypeProfile = typeprof;
241 def imm : SDNode<"ISD::Constant" , SDTIntLeaf , [], "ConstantSDNode">;
242 def fpimm : SDNode<"ISD::ConstantFP", SDTFPLeaf , [], "ConstantFPSDNode">;
243 def vt : SDNode<"ISD::VALUETYPE" , SDTOther , [], "VTSDNode">;
244 def bb : SDNode<"ISD::BasicBlock", SDTOther , [], "BasicBlockSDNode">;
245 def cond : SDNode<"ISD::CONDCODE" , SDTOther , [], "CondCodeSDNode">;
246 def undef : SDNode<"ISD::UNDEF" , SDTUNDEF , []>;
247 def globaladdr : SDNode<"ISD::GlobalAddress", SDTPtrLeaf, [],
248 "GlobalAddressSDNode">;
249 def tglobaladdr : SDNode<"ISD::TargetGlobalAddress", SDTPtrLeaf, [],
250 "GlobalAddressSDNode">;
251 def globaltlsaddr : SDNode<"ISD::GlobalTLSAddress", SDTPtrLeaf, [],
252 "GlobalAddressSDNode">;
253 def tglobaltlsaddr : SDNode<"ISD::TargetGlobalTLSAddress", SDTPtrLeaf, [],
254 "GlobalAddressSDNode">;
255 def constpool : SDNode<"ISD::ConstantPool", SDTPtrLeaf, [],
256 "ConstantPoolSDNode">;
257 def tconstpool : SDNode<"ISD::TargetConstantPool", SDTPtrLeaf, [],
258 "ConstantPoolSDNode">;
259 def jumptable : SDNode<"ISD::JumpTable", SDTPtrLeaf, [],
261 def tjumptable : SDNode<"ISD::TargetJumpTable", SDTPtrLeaf, [],
263 def frameindex : SDNode<"ISD::FrameIndex", SDTPtrLeaf, [],
265 def tframeindex : SDNode<"ISD::TargetFrameIndex", SDTPtrLeaf, [],
267 def externalsym : SDNode<"ISD::ExternalSymbol", SDTPtrLeaf, [],
268 "ExternalSymbolSDNode">;
269 def texternalsym: SDNode<"ISD::TargetExternalSymbol", SDTPtrLeaf, [],
270 "ExternalSymbolSDNode">;
272 def add : SDNode<"ISD::ADD" , SDTIntBinOp ,
273 [SDNPCommutative, SDNPAssociative]>;
274 def sub : SDNode<"ISD::SUB" , SDTIntBinOp>;
275 def mul : SDNode<"ISD::MUL" , SDTIntBinOp,
276 [SDNPCommutative, SDNPAssociative]>;
277 def mulhs : SDNode<"ISD::MULHS" , SDTIntBinOp, [SDNPCommutative]>;
278 def mulhu : SDNode<"ISD::MULHU" , SDTIntBinOp, [SDNPCommutative]>;
279 def sdiv : SDNode<"ISD::SDIV" , SDTIntBinOp>;
280 def udiv : SDNode<"ISD::UDIV" , SDTIntBinOp>;
281 def srem : SDNode<"ISD::SREM" , SDTIntBinOp>;
282 def urem : SDNode<"ISD::UREM" , SDTIntBinOp>;
283 def srl : SDNode<"ISD::SRL" , SDTIntShiftOp>;
284 def sra : SDNode<"ISD::SRA" , SDTIntShiftOp>;
285 def shl : SDNode<"ISD::SHL" , SDTIntShiftOp>;
286 def rotl : SDNode<"ISD::ROTL" , SDTIntShiftOp>;
287 def rotr : SDNode<"ISD::ROTR" , SDTIntShiftOp>;
288 def and : SDNode<"ISD::AND" , SDTIntBinOp,
289 [SDNPCommutative, SDNPAssociative]>;
290 def or : SDNode<"ISD::OR" , SDTIntBinOp,
291 [SDNPCommutative, SDNPAssociative]>;
292 def xor : SDNode<"ISD::XOR" , SDTIntBinOp,
293 [SDNPCommutative, SDNPAssociative]>;
294 def addc : SDNode<"ISD::ADDC" , SDTIntBinOp,
295 [SDNPCommutative, SDNPOutFlag]>;
296 def adde : SDNode<"ISD::ADDE" , SDTIntBinOp,
297 [SDNPCommutative, SDNPOutFlag, SDNPInFlag]>;
298 def subc : SDNode<"ISD::SUBC" , SDTIntBinOp,
300 def sube : SDNode<"ISD::SUBE" , SDTIntBinOp,
301 [SDNPOutFlag, SDNPInFlag]>;
303 def sext_inreg : SDNode<"ISD::SIGN_EXTEND_INREG", SDTExtInreg>;
304 def bswap : SDNode<"ISD::BSWAP" , SDTIntUnaryOp>;
305 def ctlz : SDNode<"ISD::CTLZ" , SDTIntUnaryOp>;
306 def cttz : SDNode<"ISD::CTTZ" , SDTIntUnaryOp>;
307 def ctpop : SDNode<"ISD::CTPOP" , SDTIntUnaryOp>;
308 def sext : SDNode<"ISD::SIGN_EXTEND", SDTIntExtendOp>;
309 def zext : SDNode<"ISD::ZERO_EXTEND", SDTIntExtendOp>;
310 def anyext : SDNode<"ISD::ANY_EXTEND" , SDTIntExtendOp>;
311 def trunc : SDNode<"ISD::TRUNCATE" , SDTIntTruncOp>;
312 def bitconvert : SDNode<"ISD::BIT_CONVERT", SDTUnaryOp>;
313 def extractelt : SDNode<"ISD::EXTRACT_VECTOR_ELT", SDTVecExtract>;
314 def insertelt : SDNode<"ISD::INSERT_VECTOR_ELT", SDTVecInsert>;
317 def fadd : SDNode<"ISD::FADD" , SDTFPBinOp, [SDNPCommutative]>;
318 def fsub : SDNode<"ISD::FSUB" , SDTFPBinOp>;
319 def fmul : SDNode<"ISD::FMUL" , SDTFPBinOp, [SDNPCommutative]>;
320 def fdiv : SDNode<"ISD::FDIV" , SDTFPBinOp>;
321 def frem : SDNode<"ISD::FREM" , SDTFPBinOp>;
322 def fabs : SDNode<"ISD::FABS" , SDTFPUnaryOp>;
323 def fneg : SDNode<"ISD::FNEG" , SDTFPUnaryOp>;
324 def fsqrt : SDNode<"ISD::FSQRT" , SDTFPUnaryOp>;
325 def fsin : SDNode<"ISD::FSIN" , SDTFPUnaryOp>;
326 def fcos : SDNode<"ISD::FCOS" , SDTFPUnaryOp>;
328 def fround : SDNode<"ISD::FP_ROUND" , SDTFPRoundOp>;
329 def fextend : SDNode<"ISD::FP_EXTEND" , SDTFPExtendOp>;
330 def fcopysign : SDNode<"ISD::FCOPYSIGN" , SDTFPSignOp>;
332 def sint_to_fp : SDNode<"ISD::SINT_TO_FP" , SDTIntToFPOp>;
333 def uint_to_fp : SDNode<"ISD::UINT_TO_FP" , SDTIntToFPOp>;
334 def fp_to_sint : SDNode<"ISD::FP_TO_SINT" , SDTFPToIntOp>;
335 def fp_to_uint : SDNode<"ISD::FP_TO_UINT" , SDTFPToIntOp>;
337 def setcc : SDNode<"ISD::SETCC" , SDTSetCC>;
338 def select : SDNode<"ISD::SELECT" , SDTSelect>;
339 def selectcc : SDNode<"ISD::SELECT_CC" , SDTSelectCC>;
340 def vsetcc : SDNode<"ISD::VSETCC" , SDTSetCC>;
342 def brcond : SDNode<"ISD::BRCOND" , SDTBrcond, [SDNPHasChain]>;
343 def brind : SDNode<"ISD::BRIND" , SDTBrind, [SDNPHasChain]>;
344 def br : SDNode<"ISD::BR" , SDTBr, [SDNPHasChain]>;
345 def ret : SDNode<"ISD::RET" , SDTNone, [SDNPHasChain]>;
346 def trap : SDNode<"ISD::TRAP" , SDTNone,
347 [SDNPHasChain, SDNPSideEffect]>;
349 def prefetch : SDNode<"ISD::PREFETCH" , STDPrefetch,
350 [SDNPHasChain, SDNPMayLoad, SDNPMayStore]>;
352 def membarrier : SDNode<"ISD::MEMBARRIER" , STDMemBarrier,
353 [SDNPHasChain, SDNPSideEffect]>;
355 // Do not use atomic_* directly, use atomic_*_size (see below)
356 def atomic_lcs : SDNode<"ISD::ATOMIC_LCS" , STDAtomic3,
357 [SDNPHasChain, SDNPMayStore, SDNPMayLoad]>;
358 def atomic_las : SDNode<"ISD::ATOMIC_LAS" , STDAtomic2,
359 [SDNPHasChain, SDNPMayStore, SDNPMayLoad]>;
360 def atomic_swap : SDNode<"ISD::ATOMIC_SWAP", STDAtomic2,
361 [SDNPHasChain, SDNPMayStore, SDNPMayLoad]>;
362 def atomic_lss : SDNode<"ISD::ATOMIC_LSS" , STDAtomic2,
363 [SDNPHasChain, SDNPMayStore, SDNPMayLoad]>;
364 def atomic_load_and : SDNode<"ISD::ATOMIC_LOAD_AND" , STDAtomic2,
365 [SDNPHasChain, SDNPMayStore, SDNPMayLoad]>;
366 def atomic_load_or : SDNode<"ISD::ATOMIC_LOAD_OR" , STDAtomic2,
367 [SDNPHasChain, SDNPMayStore, SDNPMayLoad]>;
368 def atomic_load_xor : SDNode<"ISD::ATOMIC_LOAD_XOR" , STDAtomic2,
369 [SDNPHasChain, SDNPMayStore, SDNPMayLoad]>;
370 def atomic_load_min : SDNode<"ISD::ATOMIC_LOAD_MIN", STDAtomic2,
371 [SDNPHasChain, SDNPMayStore, SDNPMayLoad]>;
372 def atomic_load_max : SDNode<"ISD::ATOMIC_LOAD_MAX", STDAtomic2,
373 [SDNPHasChain, SDNPMayStore, SDNPMayLoad]>;
374 def atomic_load_umin : SDNode<"ISD::ATOMIC_LOAD_UMIN", STDAtomic2,
375 [SDNPHasChain, SDNPMayStore, SDNPMayLoad]>;
376 def atomic_load_umax : SDNode<"ISD::ATOMIC_LOAD_UMAX", STDAtomic2,
377 [SDNPHasChain, SDNPMayStore, SDNPMayLoad]>;
379 // Do not use ld, st directly. Use load, extload, sextload, zextload, store,
380 // and truncst (see below).
381 def ld : SDNode<"ISD::LOAD" , SDTLoad,
382 [SDNPHasChain, SDNPMayLoad]>;
383 def st : SDNode<"ISD::STORE" , SDTStore,
384 [SDNPHasChain, SDNPMayStore]>;
385 def ist : SDNode<"ISD::STORE" , SDTIStore,
386 [SDNPHasChain, SDNPMayStore]>;
388 def vector_shuffle : SDNode<"ISD::VECTOR_SHUFFLE", SDTVecShuffle, []>;
389 def build_vector : SDNode<"ISD::BUILD_VECTOR", SDTypeProfile<1, 0, []>, []>;
390 def scalar_to_vector : SDNode<"ISD::SCALAR_TO_VECTOR", SDTypeProfile<1, 1, []>,
392 def vector_extract : SDNode<"ISD::EXTRACT_VECTOR_ELT",
393 SDTypeProfile<1, 2, [SDTCisPtrTy<2>]>, []>;
394 def vector_insert : SDNode<"ISD::INSERT_VECTOR_ELT",
395 SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisPtrTy<3>]>, []>;
397 def extract_subreg : SDNode<"ISD::EXTRACT_SUBREG",
398 SDTypeProfile<1, 2, []>>;
399 def insert_subreg : SDNode<"ISD::INSERT_SUBREG",
400 SDTypeProfile<1, 3, []>>;
402 // Nodes for intrinsics, you should use the intrinsic itself and let tblgen use
403 // these internally. Don't reference these directly.
404 def intrinsic_void : SDNode<"ISD::INTRINSIC_VOID",
405 SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>,
407 def intrinsic_w_chain : SDNode<"ISD::INTRINSIC_W_CHAIN",
408 SDTypeProfile<1, -1, [SDTCisPtrTy<1>]>,
410 def intrinsic_wo_chain : SDNode<"ISD::INTRINSIC_WO_CHAIN",
411 SDTypeProfile<1, -1, [SDTCisPtrTy<1>]>, []>;
414 //===----------------------------------------------------------------------===//
415 // Selection DAG Condition Codes
417 class CondCode; // ISD::CondCode enums
418 def SETOEQ : CondCode; def SETOGT : CondCode;
419 def SETOGE : CondCode; def SETOLT : CondCode; def SETOLE : CondCode;
420 def SETONE : CondCode; def SETO : CondCode; def SETUO : CondCode;
421 def SETUEQ : CondCode; def SETUGT : CondCode; def SETUGE : CondCode;
422 def SETULT : CondCode; def SETULE : CondCode; def SETUNE : CondCode;
424 def SETEQ : CondCode; def SETGT : CondCode; def SETGE : CondCode;
425 def SETLT : CondCode; def SETLE : CondCode; def SETNE : CondCode;
428 //===----------------------------------------------------------------------===//
429 // Selection DAG Node Transformation Functions.
431 // This mechanism allows targets to manipulate nodes in the output DAG once a
432 // match has been formed. This is typically used to manipulate immediate
435 class SDNodeXForm<SDNode opc, code xformFunction> {
437 code XFormFunction = xformFunction;
440 def NOOP_SDNodeXForm : SDNodeXForm<imm, [{}]>;
443 //===----------------------------------------------------------------------===//
444 // Selection DAG Pattern Fragments.
446 // Pattern fragments are reusable chunks of dags that match specific things.
447 // They can take arguments and have C++ predicates that control whether they
448 // match. They are intended to make the patterns for common instructions more
449 // compact and readable.
452 /// PatFrag - Represents a pattern fragment. This can match something on the
453 /// DAG, frame a single node to multiply nested other fragments.
455 class PatFrag<dag ops, dag frag, code pred = [{}],
456 SDNodeXForm xform = NOOP_SDNodeXForm> {
459 code Predicate = pred;
460 SDNodeXForm OperandTransform = xform;
463 // PatLeaf's are pattern fragments that have no operands. This is just a helper
464 // to define immediates and other common things concisely.
465 class PatLeaf<dag frag, code pred = [{}], SDNodeXForm xform = NOOP_SDNodeXForm>
466 : PatFrag<(ops), frag, pred, xform>;
470 def vtInt : PatLeaf<(vt), [{ return N->getVT().isInteger(); }]>;
471 def vtFP : PatLeaf<(vt), [{ return N->getVT().isFloatingPoint(); }]>;
473 def immAllOnes : PatLeaf<(imm), [{ return N->isAllOnesValue(); }]>;
474 def immAllOnesV: PatLeaf<(build_vector), [{
475 return ISD::isBuildVectorAllOnes(N);
477 def immAllOnesV_bc: PatLeaf<(bitconvert), [{
478 return ISD::isBuildVectorAllOnes(N);
480 def immAllZerosV: PatLeaf<(build_vector), [{
481 return ISD::isBuildVectorAllZeros(N);
483 def immAllZerosV_bc: PatLeaf<(bitconvert), [{
484 return ISD::isBuildVectorAllZeros(N);
489 // Other helper fragments.
490 def not : PatFrag<(ops node:$in), (xor node:$in, immAllOnes)>;
491 def vnot : PatFrag<(ops node:$in), (xor node:$in, immAllOnesV)>;
492 def vnot_conv : PatFrag<(ops node:$in), (xor node:$in, immAllOnesV_bc)>;
493 def ineg : PatFrag<(ops node:$in), (sub 0, node:$in)>;
496 def load : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
497 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
498 return LD->getExtensionType() == ISD::NON_EXTLOAD &&
499 LD->getAddressingMode() == ISD::UNINDEXED;
503 // extending load fragments.
504 def extloadi1 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
505 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
506 return LD->getExtensionType() == ISD::EXTLOAD &&
507 LD->getAddressingMode() == ISD::UNINDEXED &&
508 LD->getMemoryVT() == MVT::i1;
511 def extloadi8 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
512 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
513 return LD->getExtensionType() == ISD::EXTLOAD &&
514 LD->getAddressingMode() == ISD::UNINDEXED &&
515 LD->getMemoryVT() == MVT::i8;
518 def extloadi16 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
519 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
520 return LD->getExtensionType() == ISD::EXTLOAD &&
521 LD->getAddressingMode() == ISD::UNINDEXED &&
522 LD->getMemoryVT() == MVT::i16;
525 def extloadi32 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
526 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
527 return LD->getExtensionType() == ISD::EXTLOAD &&
528 LD->getAddressingMode() == ISD::UNINDEXED &&
529 LD->getMemoryVT() == MVT::i32;
532 def extloadf32 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
533 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
534 return LD->getExtensionType() == ISD::EXTLOAD &&
535 LD->getAddressingMode() == ISD::UNINDEXED &&
536 LD->getMemoryVT() == MVT::f32;
539 def extloadf64 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
540 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
541 return LD->getExtensionType() == ISD::EXTLOAD &&
542 LD->getAddressingMode() == ISD::UNINDEXED &&
543 LD->getMemoryVT() == MVT::f64;
547 def sextloadi1 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
548 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
549 return LD->getExtensionType() == ISD::SEXTLOAD &&
550 LD->getAddressingMode() == ISD::UNINDEXED &&
551 LD->getMemoryVT() == MVT::i1;
554 def sextloadi8 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
555 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
556 return LD->getExtensionType() == ISD::SEXTLOAD &&
557 LD->getAddressingMode() == ISD::UNINDEXED &&
558 LD->getMemoryVT() == MVT::i8;
561 def sextloadi16 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
562 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
563 return LD->getExtensionType() == ISD::SEXTLOAD &&
564 LD->getAddressingMode() == ISD::UNINDEXED &&
565 LD->getMemoryVT() == MVT::i16;
568 def sextloadi32 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
569 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
570 return LD->getExtensionType() == ISD::SEXTLOAD &&
571 LD->getAddressingMode() == ISD::UNINDEXED &&
572 LD->getMemoryVT() == MVT::i32;
576 def zextloadi1 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
577 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
578 return LD->getExtensionType() == ISD::ZEXTLOAD &&
579 LD->getAddressingMode() == ISD::UNINDEXED &&
580 LD->getMemoryVT() == MVT::i1;
583 def zextloadi8 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
584 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
585 return LD->getExtensionType() == ISD::ZEXTLOAD &&
586 LD->getAddressingMode() == ISD::UNINDEXED &&
587 LD->getMemoryVT() == MVT::i8;
590 def zextloadi16 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
591 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
592 return LD->getExtensionType() == ISD::ZEXTLOAD &&
593 LD->getAddressingMode() == ISD::UNINDEXED &&
594 LD->getMemoryVT() == MVT::i16;
597 def zextloadi32 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
598 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
599 return LD->getExtensionType() == ISD::ZEXTLOAD &&
600 LD->getAddressingMode() == ISD::UNINDEXED &&
601 LD->getMemoryVT() == MVT::i32;
606 def store : PatFrag<(ops node:$val, node:$ptr),
607 (st node:$val, node:$ptr), [{
608 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
609 return !ST->isTruncatingStore() &&
610 ST->getAddressingMode() == ISD::UNINDEXED;
614 // truncstore fragments.
615 def truncstorei8 : PatFrag<(ops node:$val, node:$ptr),
616 (st node:$val, node:$ptr), [{
617 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
618 return ST->isTruncatingStore() && ST->getMemoryVT() == MVT::i8 &&
619 ST->getAddressingMode() == ISD::UNINDEXED;
622 def truncstorei16 : PatFrag<(ops node:$val, node:$ptr),
623 (st node:$val, node:$ptr), [{
624 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
625 return ST->isTruncatingStore() && ST->getMemoryVT() == MVT::i16 &&
626 ST->getAddressingMode() == ISD::UNINDEXED;
629 def truncstorei32 : PatFrag<(ops node:$val, node:$ptr),
630 (st node:$val, node:$ptr), [{
631 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
632 return ST->isTruncatingStore() && ST->getMemoryVT() == MVT::i32 &&
633 ST->getAddressingMode() == ISD::UNINDEXED;
636 def truncstoref32 : PatFrag<(ops node:$val, node:$ptr),
637 (st node:$val, node:$ptr), [{
638 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
639 return ST->isTruncatingStore() && ST->getMemoryVT() == MVT::f32 &&
640 ST->getAddressingMode() == ISD::UNINDEXED;
643 def truncstoref64 : PatFrag<(ops node:$val, node:$ptr),
644 (st node:$val, node:$ptr), [{
645 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
646 return ST->isTruncatingStore() && ST->getMemoryVT() == MVT::f64 &&
647 ST->getAddressingMode() == ISD::UNINDEXED;
651 // indexed store fragments.
652 def pre_store : PatFrag<(ops node:$val, node:$base, node:$offset),
653 (ist node:$val, node:$base, node:$offset), [{
654 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
655 ISD::MemIndexedMode AM = ST->getAddressingMode();
656 return (AM == ISD::PRE_INC || AM == ISD::PRE_DEC) &&
657 !ST->isTruncatingStore();
662 def pre_truncsti1 : PatFrag<(ops node:$val, node:$base, node:$offset),
663 (ist node:$val, node:$base, node:$offset), [{
664 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
665 ISD::MemIndexedMode AM = ST->getAddressingMode();
666 return (AM == ISD::PRE_INC || AM == ISD::PRE_DEC) &&
667 ST->isTruncatingStore() && ST->getMemoryVT() == MVT::i1;
671 def pre_truncsti8 : PatFrag<(ops node:$val, node:$base, node:$offset),
672 (ist node:$val, node:$base, node:$offset), [{
673 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
674 ISD::MemIndexedMode AM = ST->getAddressingMode();
675 return (AM == ISD::PRE_INC || AM == ISD::PRE_DEC) &&
676 ST->isTruncatingStore() && ST->getMemoryVT() == MVT::i8;
680 def pre_truncsti16 : PatFrag<(ops node:$val, node:$base, node:$offset),
681 (ist node:$val, node:$base, node:$offset), [{
682 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
683 ISD::MemIndexedMode AM = ST->getAddressingMode();
684 return (AM == ISD::PRE_INC || AM == ISD::PRE_DEC) &&
685 ST->isTruncatingStore() && ST->getMemoryVT() == MVT::i16;
689 def pre_truncsti32 : PatFrag<(ops node:$val, node:$base, node:$offset),
690 (ist node:$val, node:$base, node:$offset), [{
691 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
692 ISD::MemIndexedMode AM = ST->getAddressingMode();
693 return (AM == ISD::PRE_INC || AM == ISD::PRE_DEC) &&
694 ST->isTruncatingStore() && ST->getMemoryVT() == MVT::i32;
698 def pre_truncstf32 : PatFrag<(ops node:$val, node:$base, node:$offset),
699 (ist node:$val, node:$base, node:$offset), [{
700 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
701 ISD::MemIndexedMode AM = ST->getAddressingMode();
702 return (AM == ISD::PRE_INC || AM == ISD::PRE_DEC) &&
703 ST->isTruncatingStore() && ST->getMemoryVT() == MVT::f32;
708 def post_store : PatFrag<(ops node:$val, node:$ptr, node:$offset),
709 (ist node:$val, node:$ptr, node:$offset), [{
710 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
711 ISD::MemIndexedMode AM = ST->getAddressingMode();
712 return !ST->isTruncatingStore() &&
713 (AM == ISD::POST_INC || AM == ISD::POST_DEC);
718 def post_truncsti1 : PatFrag<(ops node:$val, node:$base, node:$offset),
719 (ist node:$val, node:$base, node:$offset), [{
720 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
721 ISD::MemIndexedMode AM = ST->getAddressingMode();
722 return (AM == ISD::POST_INC || AM == ISD::POST_DEC) &&
723 ST->isTruncatingStore() && ST->getMemoryVT() == MVT::i1;
727 def post_truncsti8 : PatFrag<(ops node:$val, node:$base, node:$offset),
728 (ist node:$val, node:$base, node:$offset), [{
729 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
730 ISD::MemIndexedMode AM = ST->getAddressingMode();
731 return (AM == ISD::POST_INC || AM == ISD::POST_DEC) &&
732 ST->isTruncatingStore() && ST->getMemoryVT() == MVT::i8;
736 def post_truncsti16 : PatFrag<(ops node:$val, node:$base, node:$offset),
737 (ist node:$val, node:$base, node:$offset), [{
738 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
739 ISD::MemIndexedMode AM = ST->getAddressingMode();
740 return (AM == ISD::POST_INC || AM == ISD::POST_DEC) &&
741 ST->isTruncatingStore() && ST->getMemoryVT() == MVT::i16;
745 def post_truncsti32 : PatFrag<(ops node:$val, node:$base, node:$offset),
746 (ist node:$val, node:$base, node:$offset), [{
747 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
748 ISD::MemIndexedMode AM = ST->getAddressingMode();
749 return (AM == ISD::POST_INC || AM == ISD::POST_DEC) &&
750 ST->isTruncatingStore() && ST->getMemoryVT() == MVT::i32;
754 def post_truncstf32 : PatFrag<(ops node:$val, node:$base, node:$offset),
755 (ist node:$val, node:$base, node:$offset), [{
756 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
757 ISD::MemIndexedMode AM = ST->getAddressingMode();
758 return (AM == ISD::POST_INC || AM == ISD::POST_DEC) &&
759 ST->isTruncatingStore() && ST->getMemoryVT() == MVT::f32;
765 def atomic_lcs_8 : PatFrag<(ops node:$ptr, node:$cmp, node:$swp),
766 (atomic_lcs node:$ptr, node:$cmp, node:$swp), [{
767 if (AtomicSDNode* V = dyn_cast<AtomicSDNode>(N))
768 return V->getVT() == MVT::i8;
771 def atomic_lcs_16 : PatFrag<(ops node:$ptr, node:$cmp, node:$swp),
772 (atomic_lcs node:$ptr, node:$cmp, node:$swp), [{
773 if (AtomicSDNode* V = dyn_cast<AtomicSDNode>(N))
774 return V->getVT() == MVT::i16;
777 def atomic_lcs_32 : PatFrag<(ops node:$ptr, node:$cmp, node:$swp),
778 (atomic_lcs node:$ptr, node:$cmp, node:$swp), [{
779 if (AtomicSDNode* V = dyn_cast<AtomicSDNode>(N))
780 return V->getVT() == MVT::i32;
783 def atomic_lcs_64 : PatFrag<(ops node:$ptr, node:$cmp, node:$swp),
784 (atomic_lcs node:$ptr, node:$cmp, node:$swp), [{
785 if (AtomicSDNode* V = dyn_cast<AtomicSDNode>(N))
786 return V->getVT() == MVT::i64;
790 def atomic_las_8 : PatFrag<(ops node:$ptr, node:$inc),
791 (atomic_las node:$ptr, node:$inc), [{
792 if (AtomicSDNode* V = dyn_cast<AtomicSDNode>(N))
793 return V->getVT() == MVT::i8;
796 def atomic_las_16 : PatFrag<(ops node:$ptr, node:$inc),
797 (atomic_las node:$ptr, node:$inc), [{
798 if (AtomicSDNode* V = dyn_cast<AtomicSDNode>(N))
799 return V->getVT() == MVT::i16;
802 def atomic_las_32 : PatFrag<(ops node:$ptr, node:$inc),
803 (atomic_las node:$ptr, node:$inc), [{
804 if (AtomicSDNode* V = dyn_cast<AtomicSDNode>(N))
805 return V->getVT() == MVT::i32;
808 def atomic_las_64 : PatFrag<(ops node:$ptr, node:$inc),
809 (atomic_las node:$ptr, node:$inc), [{
810 if (AtomicSDNode* V = dyn_cast<AtomicSDNode>(N))
811 return V->getVT() == MVT::i64;
815 def atomic_swap_8 : PatFrag<(ops node:$ptr, node:$inc),
816 (atomic_swap node:$ptr, node:$inc), [{
817 if (AtomicSDNode* V = dyn_cast<AtomicSDNode>(N))
818 return V->getVT() == MVT::i8;
821 def atomic_swap_16 : PatFrag<(ops node:$ptr, node:$inc),
822 (atomic_swap node:$ptr, node:$inc), [{
823 if (AtomicSDNode* V = dyn_cast<AtomicSDNode>(N))
824 return V->getVT() == MVT::i16;
827 def atomic_swap_32 : PatFrag<(ops node:$ptr, node:$inc),
828 (atomic_swap node:$ptr, node:$inc), [{
829 if (AtomicSDNode* V = dyn_cast<AtomicSDNode>(N))
830 return V->getVT() == MVT::i32;
833 def atomic_swap_64 : PatFrag<(ops node:$ptr, node:$inc),
834 (atomic_swap node:$ptr, node:$inc), [{
835 if (AtomicSDNode* V = dyn_cast<AtomicSDNode>(N))
836 return V->getVT() == MVT::i64;
842 // setcc convenience fragments.
843 def setoeq : PatFrag<(ops node:$lhs, node:$rhs),
844 (setcc node:$lhs, node:$rhs, SETOEQ)>;
845 def setogt : PatFrag<(ops node:$lhs, node:$rhs),
846 (setcc node:$lhs, node:$rhs, SETOGT)>;
847 def setoge : PatFrag<(ops node:$lhs, node:$rhs),
848 (setcc node:$lhs, node:$rhs, SETOGE)>;
849 def setolt : PatFrag<(ops node:$lhs, node:$rhs),
850 (setcc node:$lhs, node:$rhs, SETOLT)>;
851 def setole : PatFrag<(ops node:$lhs, node:$rhs),
852 (setcc node:$lhs, node:$rhs, SETOLE)>;
853 def setone : PatFrag<(ops node:$lhs, node:$rhs),
854 (setcc node:$lhs, node:$rhs, SETONE)>;
855 def seto : PatFrag<(ops node:$lhs, node:$rhs),
856 (setcc node:$lhs, node:$rhs, SETO)>;
857 def setuo : PatFrag<(ops node:$lhs, node:$rhs),
858 (setcc node:$lhs, node:$rhs, SETUO)>;
859 def setueq : PatFrag<(ops node:$lhs, node:$rhs),
860 (setcc node:$lhs, node:$rhs, SETUEQ)>;
861 def setugt : PatFrag<(ops node:$lhs, node:$rhs),
862 (setcc node:$lhs, node:$rhs, SETUGT)>;
863 def setuge : PatFrag<(ops node:$lhs, node:$rhs),
864 (setcc node:$lhs, node:$rhs, SETUGE)>;
865 def setult : PatFrag<(ops node:$lhs, node:$rhs),
866 (setcc node:$lhs, node:$rhs, SETULT)>;
867 def setule : PatFrag<(ops node:$lhs, node:$rhs),
868 (setcc node:$lhs, node:$rhs, SETULE)>;
869 def setune : PatFrag<(ops node:$lhs, node:$rhs),
870 (setcc node:$lhs, node:$rhs, SETUNE)>;
871 def seteq : PatFrag<(ops node:$lhs, node:$rhs),
872 (setcc node:$lhs, node:$rhs, SETEQ)>;
873 def setgt : PatFrag<(ops node:$lhs, node:$rhs),
874 (setcc node:$lhs, node:$rhs, SETGT)>;
875 def setge : PatFrag<(ops node:$lhs, node:$rhs),
876 (setcc node:$lhs, node:$rhs, SETGE)>;
877 def setlt : PatFrag<(ops node:$lhs, node:$rhs),
878 (setcc node:$lhs, node:$rhs, SETLT)>;
879 def setle : PatFrag<(ops node:$lhs, node:$rhs),
880 (setcc node:$lhs, node:$rhs, SETLE)>;
881 def setne : PatFrag<(ops node:$lhs, node:$rhs),
882 (setcc node:$lhs, node:$rhs, SETNE)>;
884 //===----------------------------------------------------------------------===//
885 // Selection DAG Pattern Support.
887 // Patterns are what are actually matched against the target-flavored
888 // instruction selection DAG. Instructions defined by the target implicitly
889 // define patterns in most cases, but patterns can also be explicitly added when
890 // an operation is defined by a sequence of instructions (e.g. loading a large
891 // immediate value on RISC targets that do not support immediates as large as
895 class Pattern<dag patternToMatch, list<dag> resultInstrs> {
896 dag PatternToMatch = patternToMatch;
897 list<dag> ResultInstrs = resultInstrs;
898 list<Predicate> Predicates = []; // See class Instruction in Target.td.
899 int AddedComplexity = 0; // See class Instruction in Target.td.
902 // Pat - A simple (but common) form of a pattern, which produces a simple result
903 // not needing a full list.
904 class Pat<dag pattern, dag result> : Pattern<pattern, [result]>;
906 //===----------------------------------------------------------------------===//
907 // Complex pattern definitions.
911 // Pass the parent Operand as root to CP function rather
912 // than the root of the sub-DAG
913 def CPAttrParentAsRoot : CPAttribute;
915 // Complex patterns, e.g. X86 addressing mode, requires pattern matching code
916 // in C++. NumOperands is the number of operands returned by the select function;
917 // SelectFunc is the name of the function used to pattern match the max. pattern;
918 // RootNodes are the list of possible root nodes of the sub-dags to match.
919 // e.g. X86 addressing mode - def addr : ComplexPattern<4, "SelectAddr", [add]>;
921 class ComplexPattern<ValueType ty, int numops, string fn,
922 list<SDNode> roots = [], list<SDNodeProperty> props = [],
923 list<CPAttribute> attrs = []> {
925 int NumOperands = numops;
926 string SelectFunc = fn;
927 list<SDNode> RootNodes = roots;
928 list<SDNodeProperty> Properties = props;
929 list<CPAttribute> Attributes = attrs;
932 //===----------------------------------------------------------------------===//
935 def SDT_dwarf_loc : SDTypeProfile<0, 3,
936 [SDTCisInt<0>, SDTCisInt<1>, SDTCisInt<2>]>;
937 def dwarf_loc : SDNode<"ISD::DEBUG_LOC", SDT_dwarf_loc,[SDNPHasChain]>;