1 //===- TargetSelectionDAG.td - Common code for DAG isels ---*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the target-independent interfaces used by SelectionDAG
11 // instruction selection generators.
13 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
16 // Selection DAG Type Constraint definitions.
18 // Note that the semantics of these constraints are hard coded into tblgen. To
19 // modify or add constraints, you have to hack tblgen.
22 class SDTypeConstraint<int opnum> {
23 int OperandNum = opnum;
26 // SDTCisVT - The specified operand has exactly this VT.
27 class SDTCisVT<int OpNum, ValueType vt> : SDTypeConstraint<OpNum> {
31 class SDTCisPtrTy<int OpNum> : SDTypeConstraint<OpNum>;
33 // SDTCisInt - The specified operand is has integer type.
34 class SDTCisInt<int OpNum> : SDTypeConstraint<OpNum>;
36 // SDTCisFP - The specified operand is has floating point type.
37 class SDTCisFP<int OpNum> : SDTypeConstraint<OpNum>;
39 // SDTCisSameAs - The two specified operands have identical types.
40 class SDTCisSameAs<int OpNum, int OtherOp> : SDTypeConstraint<OpNum> {
41 int OtherOperandNum = OtherOp;
44 // SDTCisVTSmallerThanOp - The specified operand is a VT SDNode, and its type is
45 // smaller than the 'Other' operand.
46 class SDTCisVTSmallerThanOp<int OpNum, int OtherOp> : SDTypeConstraint<OpNum> {
47 int OtherOperandNum = OtherOp;
50 class SDTCisOpSmallerThanOp<int SmallOp, int BigOp> : SDTypeConstraint<SmallOp>{
51 int BigOperandNum = BigOp;
54 /// SDTCisIntVectorOfSameSize - This indicates that ThisOp and OtherOp are
55 /// vector types, and that ThisOp is the result of
56 /// MVT::getIntVectorWithNumElements with the number of elements that ThisOp
58 class SDTCisIntVectorOfSameSize<int ThisOp, int OtherOp>
59 : SDTypeConstraint<ThisOp> {
60 int OtherOpNum = OtherOp;
63 /// SDTCisEltOfVec - This indicates that ThisOp is a scalar type of the same
64 /// type as the element type of OtherOp, which is a vector type.
65 class SDTCisEltOfVec<int ThisOp, int OtherOp>
66 : SDTypeConstraint<ThisOp> {
67 int OtherOpNum = OtherOp;
70 //===----------------------------------------------------------------------===//
71 // Selection DAG Type Profile definitions.
73 // These use the constraints defined above to describe the type requirements of
74 // the various nodes. These are not hard coded into tblgen, allowing targets to
75 // add their own if needed.
78 // SDTypeProfile - This profile describes the type requirements of a Selection
80 class SDTypeProfile<int numresults, int numoperands,
81 list<SDTypeConstraint> constraints> {
82 int NumResults = numresults;
83 int NumOperands = numoperands;
84 list<SDTypeConstraint> Constraints = constraints;
88 def SDTIntLeaf: SDTypeProfile<1, 0, [SDTCisInt<0>]>; // for 'imm'.
89 def SDTFPLeaf : SDTypeProfile<1, 0, [SDTCisFP<0>]>; // for 'fpimm'.
90 def SDTPtrLeaf: SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>; // for '&g'.
91 def SDTOther : SDTypeProfile<1, 0, [SDTCisVT<0, OtherVT>]>; // for 'vt'.
92 def SDTUNDEF : SDTypeProfile<1, 0, []>; // for 'undef'.
93 def SDTUnaryOp : SDTypeProfile<1, 1, []>; // bitconvert
95 def SDTIntBinOp : SDTypeProfile<1, 2, [ // add, and, or, xor, udiv, etc.
96 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<0>
98 def SDTIntShiftOp : SDTypeProfile<1, 2, [ // shl, sra, srl
99 SDTCisSameAs<0, 1>, SDTCisInt<0>, SDTCisInt<2>
101 def SDTFPBinOp : SDTypeProfile<1, 2, [ // fadd, fmul, etc.
102 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisFP<0>
104 def SDTFPSignOp : SDTypeProfile<1, 2, [ // fcopysign.
105 SDTCisSameAs<0, 1>, SDTCisFP<0>, SDTCisFP<2>
107 def SDTFPTernaryOp : SDTypeProfile<1, 3, [ // fmadd, fnmsub, etc.
108 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>, SDTCisFP<0>
110 def SDTIntUnaryOp : SDTypeProfile<1, 1, [ // ctlz
111 SDTCisSameAs<0, 1>, SDTCisInt<0>
113 def SDTIntExtendOp : SDTypeProfile<1, 1, [ // sext, zext, anyext
114 SDTCisInt<0>, SDTCisInt<1>, SDTCisOpSmallerThanOp<1, 0>
116 def SDTIntTruncOp : SDTypeProfile<1, 1, [ // trunc
117 SDTCisInt<0>, SDTCisInt<1>, SDTCisOpSmallerThanOp<0, 1>
119 def SDTFPUnaryOp : SDTypeProfile<1, 1, [ // fneg, fsqrt, etc
120 SDTCisSameAs<0, 1>, SDTCisFP<0>
122 def SDTFPRoundOp : SDTypeProfile<1, 1, [ // fround
123 SDTCisFP<0>, SDTCisFP<1>, SDTCisOpSmallerThanOp<0, 1>
125 def SDTFPExtendOp : SDTypeProfile<1, 1, [ // fextend
126 SDTCisFP<0>, SDTCisFP<1>, SDTCisOpSmallerThanOp<1, 0>
128 def SDTIntToFPOp : SDTypeProfile<1, 1, [ // [su]int_to_fp
129 SDTCisFP<0>, SDTCisInt<1>
131 def SDTFPToIntOp : SDTypeProfile<1, 1, [ // fp_to_[su]int
132 SDTCisInt<0>, SDTCisFP<1>
134 def SDTExtInreg : SDTypeProfile<1, 2, [ // sext_inreg
135 SDTCisSameAs<0, 1>, SDTCisInt<0>, SDTCisVT<2, OtherVT>,
136 SDTCisVTSmallerThanOp<2, 1>
139 def SDTSetCC : SDTypeProfile<1, 3, [ // setcc
140 SDTCisInt<0>, SDTCisSameAs<1, 2>, SDTCisVT<3, OtherVT>
143 def SDTSelect : SDTypeProfile<1, 3, [ // select
144 SDTCisInt<1>, SDTCisSameAs<0, 2>, SDTCisSameAs<2, 3>
147 def SDTSelectCC : SDTypeProfile<1, 5, [ // select_cc
148 SDTCisSameAs<1, 2>, SDTCisSameAs<3, 4>, SDTCisSameAs<0, 3>,
152 def SDTBr : SDTypeProfile<0, 1, [ // br
156 def SDTBrcond : SDTypeProfile<0, 2, [ // brcond
157 SDTCisInt<0>, SDTCisVT<1, OtherVT>
160 def SDTBrind : SDTypeProfile<0, 1, [ // brind
164 def SDTNone : SDTypeProfile<0, 0, []>; // ret, trap
166 def SDTLoad : SDTypeProfile<1, 1, [ // load
170 def SDTStore : SDTypeProfile<0, 2, [ // store
174 def SDTIStore : SDTypeProfile<1, 3, [ // indexed store
175 SDTCisSameAs<0, 2>, SDTCisPtrTy<0>, SDTCisPtrTy<3>
178 def SDTVecShuffle : SDTypeProfile<1, 3, [
179 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisIntVectorOfSameSize<3, 0>
181 def SDTVecExtract : SDTypeProfile<1, 2, [ // vector extract
182 SDTCisEltOfVec<0, 1>, SDTCisPtrTy<2>
184 def SDTVecInsert : SDTypeProfile<1, 3, [ // vector insert
185 SDTCisEltOfVec<2, 1>, SDTCisSameAs<0, 1>, SDTCisPtrTy<3>
188 def STDPrefetch : SDTypeProfile<0, 3, [ // prefetch
189 SDTCisPtrTy<0>, SDTCisSameAs<1, 2>, SDTCisInt<1>
192 def STDMemBarrier : SDTypeProfile<0, 5, [ // memory barier
193 SDTCisSameAs<0,1>, SDTCisSameAs<0,2>, SDTCisSameAs<0,3>, SDTCisSameAs<0,4>,
196 def STDAtomic3 : SDTypeProfile<1, 3, [
197 SDTCisSameAs<0,2>, SDTCisSameAs<0,3>, SDTCisInt<0>, SDTCisPtrTy<1>
199 def STDAtomic2 : SDTypeProfile<1, 2, [
200 SDTCisSameAs<0,2>, SDTCisInt<0>, SDTCisPtrTy<1>
203 class SDCallSeqStart<list<SDTypeConstraint> constraints> :
204 SDTypeProfile<0, 1, constraints>;
205 class SDCallSeqEnd<list<SDTypeConstraint> constraints> :
206 SDTypeProfile<0, 2, constraints>;
208 //===----------------------------------------------------------------------===//
209 // Selection DAG Node Properties.
211 // Note: These are hard coded into tblgen.
213 class SDNodeProperty;
214 def SDNPCommutative : SDNodeProperty; // X op Y == Y op X
215 def SDNPAssociative : SDNodeProperty; // (X op Y) op Z == X op (Y op Z)
216 def SDNPHasChain : SDNodeProperty; // R/W chain operand and result
217 def SDNPOutFlag : SDNodeProperty; // Write a flag result
218 def SDNPInFlag : SDNodeProperty; // Read a flag operand
219 def SDNPOptInFlag : SDNodeProperty; // Optionally read a flag operand
220 def SDNPMayStore : SDNodeProperty; // May write to memory, sets 'mayStore'.
221 def SDNPMayLoad : SDNodeProperty; // May read memory, sets 'mayLoad'.
222 def SDNPSideEffect : SDNodeProperty; // Sets 'HasUnmodelledSideEffects'.
224 //===----------------------------------------------------------------------===//
225 // Selection DAG Node definitions.
227 class SDNode<string opcode, SDTypeProfile typeprof,
228 list<SDNodeProperty> props = [], string sdclass = "SDNode"> {
229 string Opcode = opcode;
230 string SDClass = sdclass;
231 list<SDNodeProperty> Properties = props;
232 SDTypeProfile TypeProfile = typeprof;
241 def imm : SDNode<"ISD::Constant" , SDTIntLeaf , [], "ConstantSDNode">;
242 def fpimm : SDNode<"ISD::ConstantFP", SDTFPLeaf , [], "ConstantFPSDNode">;
243 def vt : SDNode<"ISD::VALUETYPE" , SDTOther , [], "VTSDNode">;
244 def bb : SDNode<"ISD::BasicBlock", SDTOther , [], "BasicBlockSDNode">;
245 def cond : SDNode<"ISD::CONDCODE" , SDTOther , [], "CondCodeSDNode">;
246 def undef : SDNode<"ISD::UNDEF" , SDTUNDEF , []>;
247 def globaladdr : SDNode<"ISD::GlobalAddress", SDTPtrLeaf, [],
248 "GlobalAddressSDNode">;
249 def tglobaladdr : SDNode<"ISD::TargetGlobalAddress", SDTPtrLeaf, [],
250 "GlobalAddressSDNode">;
251 def globaltlsaddr : SDNode<"ISD::GlobalTLSAddress", SDTPtrLeaf, [],
252 "GlobalAddressSDNode">;
253 def tglobaltlsaddr : SDNode<"ISD::TargetGlobalTLSAddress", SDTPtrLeaf, [],
254 "GlobalAddressSDNode">;
255 def constpool : SDNode<"ISD::ConstantPool", SDTPtrLeaf, [],
256 "ConstantPoolSDNode">;
257 def tconstpool : SDNode<"ISD::TargetConstantPool", SDTPtrLeaf, [],
258 "ConstantPoolSDNode">;
259 def jumptable : SDNode<"ISD::JumpTable", SDTPtrLeaf, [],
261 def tjumptable : SDNode<"ISD::TargetJumpTable", SDTPtrLeaf, [],
263 def frameindex : SDNode<"ISD::FrameIndex", SDTPtrLeaf, [],
265 def tframeindex : SDNode<"ISD::TargetFrameIndex", SDTPtrLeaf, [],
267 def externalsym : SDNode<"ISD::ExternalSymbol", SDTPtrLeaf, [],
268 "ExternalSymbolSDNode">;
269 def texternalsym: SDNode<"ISD::TargetExternalSymbol", SDTPtrLeaf, [],
270 "ExternalSymbolSDNode">;
272 def add : SDNode<"ISD::ADD" , SDTIntBinOp ,
273 [SDNPCommutative, SDNPAssociative]>;
274 def sub : SDNode<"ISD::SUB" , SDTIntBinOp>;
275 def mul : SDNode<"ISD::MUL" , SDTIntBinOp,
276 [SDNPCommutative, SDNPAssociative]>;
277 def mulhs : SDNode<"ISD::MULHS" , SDTIntBinOp, [SDNPCommutative]>;
278 def mulhu : SDNode<"ISD::MULHU" , SDTIntBinOp, [SDNPCommutative]>;
279 def sdiv : SDNode<"ISD::SDIV" , SDTIntBinOp>;
280 def udiv : SDNode<"ISD::UDIV" , SDTIntBinOp>;
281 def srem : SDNode<"ISD::SREM" , SDTIntBinOp>;
282 def urem : SDNode<"ISD::UREM" , SDTIntBinOp>;
283 def srl : SDNode<"ISD::SRL" , SDTIntShiftOp>;
284 def sra : SDNode<"ISD::SRA" , SDTIntShiftOp>;
285 def shl : SDNode<"ISD::SHL" , SDTIntShiftOp>;
286 def rotl : SDNode<"ISD::ROTL" , SDTIntShiftOp>;
287 def rotr : SDNode<"ISD::ROTR" , SDTIntShiftOp>;
288 def and : SDNode<"ISD::AND" , SDTIntBinOp,
289 [SDNPCommutative, SDNPAssociative]>;
290 def or : SDNode<"ISD::OR" , SDTIntBinOp,
291 [SDNPCommutative, SDNPAssociative]>;
292 def xor : SDNode<"ISD::XOR" , SDTIntBinOp,
293 [SDNPCommutative, SDNPAssociative]>;
294 def addc : SDNode<"ISD::ADDC" , SDTIntBinOp,
295 [SDNPCommutative, SDNPOutFlag]>;
296 def adde : SDNode<"ISD::ADDE" , SDTIntBinOp,
297 [SDNPCommutative, SDNPOutFlag, SDNPInFlag]>;
298 def subc : SDNode<"ISD::SUBC" , SDTIntBinOp,
300 def sube : SDNode<"ISD::SUBE" , SDTIntBinOp,
301 [SDNPOutFlag, SDNPInFlag]>;
303 def sext_inreg : SDNode<"ISD::SIGN_EXTEND_INREG", SDTExtInreg>;
304 def bswap : SDNode<"ISD::BSWAP" , SDTIntUnaryOp>;
305 def ctlz : SDNode<"ISD::CTLZ" , SDTIntUnaryOp>;
306 def cttz : SDNode<"ISD::CTTZ" , SDTIntUnaryOp>;
307 def ctpop : SDNode<"ISD::CTPOP" , SDTIntUnaryOp>;
308 def sext : SDNode<"ISD::SIGN_EXTEND", SDTIntExtendOp>;
309 def zext : SDNode<"ISD::ZERO_EXTEND", SDTIntExtendOp>;
310 def anyext : SDNode<"ISD::ANY_EXTEND" , SDTIntExtendOp>;
311 def trunc : SDNode<"ISD::TRUNCATE" , SDTIntTruncOp>;
312 def bitconvert : SDNode<"ISD::BIT_CONVERT", SDTUnaryOp>;
313 def extractelt : SDNode<"ISD::EXTRACT_VECTOR_ELT", SDTVecExtract>;
314 def insertelt : SDNode<"ISD::INSERT_VECTOR_ELT", SDTVecInsert>;
317 def fadd : SDNode<"ISD::FADD" , SDTFPBinOp, [SDNPCommutative]>;
318 def fsub : SDNode<"ISD::FSUB" , SDTFPBinOp>;
319 def fmul : SDNode<"ISD::FMUL" , SDTFPBinOp, [SDNPCommutative]>;
320 def fdiv : SDNode<"ISD::FDIV" , SDTFPBinOp>;
321 def frem : SDNode<"ISD::FREM" , SDTFPBinOp>;
322 def fabs : SDNode<"ISD::FABS" , SDTFPUnaryOp>;
323 def fneg : SDNode<"ISD::FNEG" , SDTFPUnaryOp>;
324 def fsqrt : SDNode<"ISD::FSQRT" , SDTFPUnaryOp>;
325 def fsin : SDNode<"ISD::FSIN" , SDTFPUnaryOp>;
326 def fcos : SDNode<"ISD::FCOS" , SDTFPUnaryOp>;
328 def fround : SDNode<"ISD::FP_ROUND" , SDTFPRoundOp>;
329 def fextend : SDNode<"ISD::FP_EXTEND" , SDTFPExtendOp>;
330 def fcopysign : SDNode<"ISD::FCOPYSIGN" , SDTFPSignOp>;
332 def sint_to_fp : SDNode<"ISD::SINT_TO_FP" , SDTIntToFPOp>;
333 def uint_to_fp : SDNode<"ISD::UINT_TO_FP" , SDTIntToFPOp>;
334 def fp_to_sint : SDNode<"ISD::FP_TO_SINT" , SDTFPToIntOp>;
335 def fp_to_uint : SDNode<"ISD::FP_TO_UINT" , SDTFPToIntOp>;
337 def setcc : SDNode<"ISD::SETCC" , SDTSetCC>;
338 def select : SDNode<"ISD::SELECT" , SDTSelect>;
339 def selectcc : SDNode<"ISD::SELECT_CC" , SDTSelectCC>;
341 def brcond : SDNode<"ISD::BRCOND" , SDTBrcond, [SDNPHasChain]>;
342 def brind : SDNode<"ISD::BRIND" , SDTBrind, [SDNPHasChain]>;
343 def br : SDNode<"ISD::BR" , SDTBr, [SDNPHasChain]>;
344 def ret : SDNode<"ISD::RET" , SDTNone, [SDNPHasChain]>;
345 def trap : SDNode<"ISD::TRAP" , SDTNone,
346 [SDNPHasChain, SDNPSideEffect]>;
348 def prefetch : SDNode<"ISD::PREFETCH" , STDPrefetch,
349 [SDNPHasChain, SDNPMayLoad, SDNPMayStore]>;
351 def membarrier : SDNode<"ISD::MEMBARRIER" , STDMemBarrier,
352 [SDNPHasChain, SDNPSideEffect]>;
354 // Do not use atomic_* directly, use atomic_*_size (see below)
355 def atomic_lcs : SDNode<"ISD::ATOMIC_LCS" , STDAtomic3,
356 [SDNPHasChain, SDNPMayStore, SDNPMayLoad]>;
357 def atomic_las : SDNode<"ISD::ATOMIC_LAS" , STDAtomic2,
358 [SDNPHasChain, SDNPMayStore, SDNPMayLoad]>;
359 def atomic_swap : SDNode<"ISD::ATOMIC_SWAP", STDAtomic2,
360 [SDNPHasChain, SDNPMayStore, SDNPMayLoad]>;
362 // Do not use ld, st directly. Use load, extload, sextload, zextload, store,
363 // and truncst (see below).
364 def ld : SDNode<"ISD::LOAD" , SDTLoad,
365 [SDNPHasChain, SDNPMayLoad]>;
366 def st : SDNode<"ISD::STORE" , SDTStore,
367 [SDNPHasChain, SDNPMayStore]>;
368 def ist : SDNode<"ISD::STORE" , SDTIStore,
369 [SDNPHasChain, SDNPMayStore]>;
371 def vector_shuffle : SDNode<"ISD::VECTOR_SHUFFLE", SDTVecShuffle, []>;
372 def build_vector : SDNode<"ISD::BUILD_VECTOR", SDTypeProfile<1, 0, []>, []>;
373 def scalar_to_vector : SDNode<"ISD::SCALAR_TO_VECTOR", SDTypeProfile<1, 1, []>,
375 def vector_extract : SDNode<"ISD::EXTRACT_VECTOR_ELT",
376 SDTypeProfile<1, 2, [SDTCisPtrTy<2>]>, []>;
377 def vector_insert : SDNode<"ISD::INSERT_VECTOR_ELT",
378 SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisPtrTy<3>]>, []>;
380 def extract_subreg : SDNode<"ISD::EXTRACT_SUBREG",
381 SDTypeProfile<1, 2, []>>;
382 def insert_subreg : SDNode<"ISD::INSERT_SUBREG",
383 SDTypeProfile<1, 3, []>>;
385 // Nodes for intrinsics, you should use the intrinsic itself and let tblgen use
386 // these internally. Don't reference these directly.
387 def intrinsic_void : SDNode<"ISD::INTRINSIC_VOID",
388 SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>,
390 def intrinsic_w_chain : SDNode<"ISD::INTRINSIC_W_CHAIN",
391 SDTypeProfile<1, -1, [SDTCisPtrTy<1>]>,
393 def intrinsic_wo_chain : SDNode<"ISD::INTRINSIC_WO_CHAIN",
394 SDTypeProfile<1, -1, [SDTCisPtrTy<1>]>, []>;
397 //===----------------------------------------------------------------------===//
398 // Selection DAG Condition Codes
400 class CondCode; // ISD::CondCode enums
401 def SETOEQ : CondCode; def SETOGT : CondCode;
402 def SETOGE : CondCode; def SETOLT : CondCode; def SETOLE : CondCode;
403 def SETONE : CondCode; def SETO : CondCode; def SETUO : CondCode;
404 def SETUEQ : CondCode; def SETUGT : CondCode; def SETUGE : CondCode;
405 def SETULT : CondCode; def SETULE : CondCode; def SETUNE : CondCode;
407 def SETEQ : CondCode; def SETGT : CondCode; def SETGE : CondCode;
408 def SETLT : CondCode; def SETLE : CondCode; def SETNE : CondCode;
411 //===----------------------------------------------------------------------===//
412 // Selection DAG Node Transformation Functions.
414 // This mechanism allows targets to manipulate nodes in the output DAG once a
415 // match has been formed. This is typically used to manipulate immediate
418 class SDNodeXForm<SDNode opc, code xformFunction> {
420 code XFormFunction = xformFunction;
423 def NOOP_SDNodeXForm : SDNodeXForm<imm, [{}]>;
426 //===----------------------------------------------------------------------===//
427 // Selection DAG Pattern Fragments.
429 // Pattern fragments are reusable chunks of dags that match specific things.
430 // They can take arguments and have C++ predicates that control whether they
431 // match. They are intended to make the patterns for common instructions more
432 // compact and readable.
435 /// PatFrag - Represents a pattern fragment. This can match something on the
436 /// DAG, frame a single node to multiply nested other fragments.
438 class PatFrag<dag ops, dag frag, code pred = [{}],
439 SDNodeXForm xform = NOOP_SDNodeXForm> {
442 code Predicate = pred;
443 SDNodeXForm OperandTransform = xform;
446 // PatLeaf's are pattern fragments that have no operands. This is just a helper
447 // to define immediates and other common things concisely.
448 class PatLeaf<dag frag, code pred = [{}], SDNodeXForm xform = NOOP_SDNodeXForm>
449 : PatFrag<(ops), frag, pred, xform>;
453 def vtInt : PatLeaf<(vt), [{ return MVT::isInteger(N->getVT()); }]>;
454 def vtFP : PatLeaf<(vt), [{ return MVT::isFloatingPoint(N->getVT()); }]>;
456 def immAllOnes : PatLeaf<(imm), [{ return N->isAllOnesValue(); }]>;
457 def immAllOnesV: PatLeaf<(build_vector), [{
458 return ISD::isBuildVectorAllOnes(N);
460 def immAllOnesV_bc: PatLeaf<(bitconvert), [{
461 return ISD::isBuildVectorAllOnes(N);
463 def immAllZerosV: PatLeaf<(build_vector), [{
464 return ISD::isBuildVectorAllZeros(N);
466 def immAllZerosV_bc: PatLeaf<(bitconvert), [{
467 return ISD::isBuildVectorAllZeros(N);
472 // Other helper fragments.
473 def not : PatFrag<(ops node:$in), (xor node:$in, immAllOnes)>;
474 def vnot : PatFrag<(ops node:$in), (xor node:$in, immAllOnesV)>;
475 def vnot_conv : PatFrag<(ops node:$in), (xor node:$in, immAllOnesV_bc)>;
476 def ineg : PatFrag<(ops node:$in), (sub 0, node:$in)>;
479 def load : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
480 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
481 return LD->getExtensionType() == ISD::NON_EXTLOAD &&
482 LD->getAddressingMode() == ISD::UNINDEXED;
486 // extending load fragments.
487 def extloadi1 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
488 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
489 return LD->getExtensionType() == ISD::EXTLOAD &&
490 LD->getAddressingMode() == ISD::UNINDEXED &&
491 LD->getMemoryVT() == MVT::i1;
494 def extloadi8 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
495 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
496 return LD->getExtensionType() == ISD::EXTLOAD &&
497 LD->getAddressingMode() == ISD::UNINDEXED &&
498 LD->getMemoryVT() == MVT::i8;
501 def extloadi16 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
502 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
503 return LD->getExtensionType() == ISD::EXTLOAD &&
504 LD->getAddressingMode() == ISD::UNINDEXED &&
505 LD->getMemoryVT() == MVT::i16;
508 def extloadi32 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
509 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
510 return LD->getExtensionType() == ISD::EXTLOAD &&
511 LD->getAddressingMode() == ISD::UNINDEXED &&
512 LD->getMemoryVT() == MVT::i32;
515 def extloadf32 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
516 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
517 return LD->getExtensionType() == ISD::EXTLOAD &&
518 LD->getAddressingMode() == ISD::UNINDEXED &&
519 LD->getMemoryVT() == MVT::f32;
522 def extloadf64 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
523 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
524 return LD->getExtensionType() == ISD::EXTLOAD &&
525 LD->getAddressingMode() == ISD::UNINDEXED &&
526 LD->getMemoryVT() == MVT::f64;
530 def sextloadi1 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
531 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
532 return LD->getExtensionType() == ISD::SEXTLOAD &&
533 LD->getAddressingMode() == ISD::UNINDEXED &&
534 LD->getMemoryVT() == MVT::i1;
537 def sextloadi8 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
538 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
539 return LD->getExtensionType() == ISD::SEXTLOAD &&
540 LD->getAddressingMode() == ISD::UNINDEXED &&
541 LD->getMemoryVT() == MVT::i8;
544 def sextloadi16 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
545 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
546 return LD->getExtensionType() == ISD::SEXTLOAD &&
547 LD->getAddressingMode() == ISD::UNINDEXED &&
548 LD->getMemoryVT() == MVT::i16;
551 def sextloadi32 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
552 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
553 return LD->getExtensionType() == ISD::SEXTLOAD &&
554 LD->getAddressingMode() == ISD::UNINDEXED &&
555 LD->getMemoryVT() == MVT::i32;
559 def zextloadi1 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
560 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
561 return LD->getExtensionType() == ISD::ZEXTLOAD &&
562 LD->getAddressingMode() == ISD::UNINDEXED &&
563 LD->getMemoryVT() == MVT::i1;
566 def zextloadi8 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
567 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
568 return LD->getExtensionType() == ISD::ZEXTLOAD &&
569 LD->getAddressingMode() == ISD::UNINDEXED &&
570 LD->getMemoryVT() == MVT::i8;
573 def zextloadi16 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
574 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
575 return LD->getExtensionType() == ISD::ZEXTLOAD &&
576 LD->getAddressingMode() == ISD::UNINDEXED &&
577 LD->getMemoryVT() == MVT::i16;
580 def zextloadi32 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
581 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
582 return LD->getExtensionType() == ISD::ZEXTLOAD &&
583 LD->getAddressingMode() == ISD::UNINDEXED &&
584 LD->getMemoryVT() == MVT::i32;
589 def store : PatFrag<(ops node:$val, node:$ptr),
590 (st node:$val, node:$ptr), [{
591 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
592 return !ST->isTruncatingStore() &&
593 ST->getAddressingMode() == ISD::UNINDEXED;
597 // truncstore fragments.
598 def truncstorei8 : PatFrag<(ops node:$val, node:$ptr),
599 (st node:$val, node:$ptr), [{
600 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
601 return ST->isTruncatingStore() && ST->getMemoryVT() == MVT::i8 &&
602 ST->getAddressingMode() == ISD::UNINDEXED;
605 def truncstorei16 : PatFrag<(ops node:$val, node:$ptr),
606 (st node:$val, node:$ptr), [{
607 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
608 return ST->isTruncatingStore() && ST->getMemoryVT() == MVT::i16 &&
609 ST->getAddressingMode() == ISD::UNINDEXED;
612 def truncstorei32 : PatFrag<(ops node:$val, node:$ptr),
613 (st node:$val, node:$ptr), [{
614 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
615 return ST->isTruncatingStore() && ST->getMemoryVT() == MVT::i32 &&
616 ST->getAddressingMode() == ISD::UNINDEXED;
619 def truncstoref32 : PatFrag<(ops node:$val, node:$ptr),
620 (st node:$val, node:$ptr), [{
621 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
622 return ST->isTruncatingStore() && ST->getMemoryVT() == MVT::f32 &&
623 ST->getAddressingMode() == ISD::UNINDEXED;
626 def truncstoref64 : PatFrag<(ops node:$val, node:$ptr),
627 (st node:$val, node:$ptr), [{
628 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
629 return ST->isTruncatingStore() && ST->getMemoryVT() == MVT::f64 &&
630 ST->getAddressingMode() == ISD::UNINDEXED;
634 // indexed store fragments.
635 def pre_store : PatFrag<(ops node:$val, node:$base, node:$offset),
636 (ist node:$val, node:$base, node:$offset), [{
637 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
638 ISD::MemIndexedMode AM = ST->getAddressingMode();
639 return (AM == ISD::PRE_INC || AM == ISD::PRE_DEC) &&
640 !ST->isTruncatingStore();
645 def pre_truncsti1 : PatFrag<(ops node:$val, node:$base, node:$offset),
646 (ist node:$val, node:$base, node:$offset), [{
647 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
648 ISD::MemIndexedMode AM = ST->getAddressingMode();
649 return (AM == ISD::PRE_INC || AM == ISD::PRE_DEC) &&
650 ST->isTruncatingStore() && ST->getMemoryVT() == MVT::i1;
654 def pre_truncsti8 : PatFrag<(ops node:$val, node:$base, node:$offset),
655 (ist node:$val, node:$base, node:$offset), [{
656 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
657 ISD::MemIndexedMode AM = ST->getAddressingMode();
658 return (AM == ISD::PRE_INC || AM == ISD::PRE_DEC) &&
659 ST->isTruncatingStore() && ST->getMemoryVT() == MVT::i8;
663 def pre_truncsti16 : PatFrag<(ops node:$val, node:$base, node:$offset),
664 (ist node:$val, node:$base, node:$offset), [{
665 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
666 ISD::MemIndexedMode AM = ST->getAddressingMode();
667 return (AM == ISD::PRE_INC || AM == ISD::PRE_DEC) &&
668 ST->isTruncatingStore() && ST->getMemoryVT() == MVT::i16;
672 def pre_truncsti32 : PatFrag<(ops node:$val, node:$base, node:$offset),
673 (ist node:$val, node:$base, node:$offset), [{
674 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
675 ISD::MemIndexedMode AM = ST->getAddressingMode();
676 return (AM == ISD::PRE_INC || AM == ISD::PRE_DEC) &&
677 ST->isTruncatingStore() && ST->getMemoryVT() == MVT::i32;
681 def pre_truncstf32 : PatFrag<(ops node:$val, node:$base, node:$offset),
682 (ist node:$val, node:$base, node:$offset), [{
683 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
684 ISD::MemIndexedMode AM = ST->getAddressingMode();
685 return (AM == ISD::PRE_INC || AM == ISD::PRE_DEC) &&
686 ST->isTruncatingStore() && ST->getMemoryVT() == MVT::f32;
691 def post_store : PatFrag<(ops node:$val, node:$ptr, node:$offset),
692 (ist node:$val, node:$ptr, node:$offset), [{
693 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
694 ISD::MemIndexedMode AM = ST->getAddressingMode();
695 return !ST->isTruncatingStore() &&
696 (AM == ISD::POST_INC || AM == ISD::POST_DEC);
701 def post_truncsti1 : PatFrag<(ops node:$val, node:$base, node:$offset),
702 (ist node:$val, node:$base, node:$offset), [{
703 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
704 ISD::MemIndexedMode AM = ST->getAddressingMode();
705 return (AM == ISD::POST_INC || AM == ISD::POST_DEC) &&
706 ST->isTruncatingStore() && ST->getMemoryVT() == MVT::i1;
710 def post_truncsti8 : PatFrag<(ops node:$val, node:$base, node:$offset),
711 (ist node:$val, node:$base, node:$offset), [{
712 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
713 ISD::MemIndexedMode AM = ST->getAddressingMode();
714 return (AM == ISD::POST_INC || AM == ISD::POST_DEC) &&
715 ST->isTruncatingStore() && ST->getMemoryVT() == MVT::i8;
719 def post_truncsti16 : PatFrag<(ops node:$val, node:$base, node:$offset),
720 (ist node:$val, node:$base, node:$offset), [{
721 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
722 ISD::MemIndexedMode AM = ST->getAddressingMode();
723 return (AM == ISD::POST_INC || AM == ISD::POST_DEC) &&
724 ST->isTruncatingStore() && ST->getMemoryVT() == MVT::i16;
728 def post_truncsti32 : PatFrag<(ops node:$val, node:$base, node:$offset),
729 (ist node:$val, node:$base, node:$offset), [{
730 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
731 ISD::MemIndexedMode AM = ST->getAddressingMode();
732 return (AM == ISD::POST_INC || AM == ISD::POST_DEC) &&
733 ST->isTruncatingStore() && ST->getMemoryVT() == MVT::i32;
737 def post_truncstf32 : PatFrag<(ops node:$val, node:$base, node:$offset),
738 (ist node:$val, node:$base, node:$offset), [{
739 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
740 ISD::MemIndexedMode AM = ST->getAddressingMode();
741 return (AM == ISD::POST_INC || AM == ISD::POST_DEC) &&
742 ST->isTruncatingStore() && ST->getMemoryVT() == MVT::f32;
748 def atomic_lcs_8 : PatFrag<(ops node:$ptr, node:$cmp, node:$swp),
749 (atomic_lcs node:$ptr, node:$cmp, node:$swp), [{
750 if (AtomicSDNode* V = dyn_cast<AtomicSDNode>(N))
751 return V->getVT() == MVT::i8;
754 def atomic_lcs_16 : PatFrag<(ops node:$ptr, node:$cmp, node:$swp),
755 (atomic_lcs node:$ptr, node:$cmp, node:$swp), [{
756 if (AtomicSDNode* V = dyn_cast<AtomicSDNode>(N))
757 return V->getVT() == MVT::i16;
760 def atomic_lcs_32 : PatFrag<(ops node:$ptr, node:$cmp, node:$swp),
761 (atomic_lcs node:$ptr, node:$cmp, node:$swp), [{
762 if (AtomicSDNode* V = dyn_cast<AtomicSDNode>(N))
763 return V->getVT() == MVT::i32;
766 def atomic_lcs_64 : PatFrag<(ops node:$ptr, node:$cmp, node:$swp),
767 (atomic_lcs node:$ptr, node:$cmp, node:$swp), [{
768 if (AtomicSDNode* V = dyn_cast<AtomicSDNode>(N))
769 return V->getVT() == MVT::i64;
773 def atomic_las_8 : PatFrag<(ops node:$ptr, node:$inc),
774 (atomic_las node:$ptr, node:$inc), [{
775 if (AtomicSDNode* V = dyn_cast<AtomicSDNode>(N))
776 return V->getVT() == MVT::i8;
779 def atomic_las_16 : PatFrag<(ops node:$ptr, node:$inc),
780 (atomic_las node:$ptr, node:$inc), [{
781 if (AtomicSDNode* V = dyn_cast<AtomicSDNode>(N))
782 return V->getVT() == MVT::i16;
785 def atomic_las_32 : PatFrag<(ops node:$ptr, node:$inc),
786 (atomic_las node:$ptr, node:$inc), [{
787 if (AtomicSDNode* V = dyn_cast<AtomicSDNode>(N))
788 return V->getVT() == MVT::i32;
791 def atomic_las_64 : PatFrag<(ops node:$ptr, node:$inc),
792 (atomic_las node:$ptr, node:$inc), [{
793 if (AtomicSDNode* V = dyn_cast<AtomicSDNode>(N))
794 return V->getVT() == MVT::i64;
798 def atomic_swap_8 : PatFrag<(ops node:$ptr, node:$inc),
799 (atomic_swap node:$ptr, node:$inc), [{
800 if (AtomicSDNode* V = dyn_cast<AtomicSDNode>(N))
801 return V->getVT() == MVT::i8;
804 def atomic_swap_16 : PatFrag<(ops node:$ptr, node:$inc),
805 (atomic_swap node:$ptr, node:$inc), [{
806 if (AtomicSDNode* V = dyn_cast<AtomicSDNode>(N))
807 return V->getVT() == MVT::i16;
810 def atomic_swap_32 : PatFrag<(ops node:$ptr, node:$inc),
811 (atomic_swap node:$ptr, node:$inc), [{
812 if (AtomicSDNode* V = dyn_cast<AtomicSDNode>(N))
813 return V->getVT() == MVT::i32;
816 def atomic_swap_64 : PatFrag<(ops node:$ptr, node:$inc),
817 (atomic_swap node:$ptr, node:$inc), [{
818 if (AtomicSDNode* V = dyn_cast<AtomicSDNode>(N))
819 return V->getVT() == MVT::i64;
825 // setcc convenience fragments.
826 def setoeq : PatFrag<(ops node:$lhs, node:$rhs),
827 (setcc node:$lhs, node:$rhs, SETOEQ)>;
828 def setogt : PatFrag<(ops node:$lhs, node:$rhs),
829 (setcc node:$lhs, node:$rhs, SETOGT)>;
830 def setoge : PatFrag<(ops node:$lhs, node:$rhs),
831 (setcc node:$lhs, node:$rhs, SETOGE)>;
832 def setolt : PatFrag<(ops node:$lhs, node:$rhs),
833 (setcc node:$lhs, node:$rhs, SETOLT)>;
834 def setole : PatFrag<(ops node:$lhs, node:$rhs),
835 (setcc node:$lhs, node:$rhs, SETOLE)>;
836 def setone : PatFrag<(ops node:$lhs, node:$rhs),
837 (setcc node:$lhs, node:$rhs, SETONE)>;
838 def seto : PatFrag<(ops node:$lhs, node:$rhs),
839 (setcc node:$lhs, node:$rhs, SETO)>;
840 def setuo : PatFrag<(ops node:$lhs, node:$rhs),
841 (setcc node:$lhs, node:$rhs, SETUO)>;
842 def setueq : PatFrag<(ops node:$lhs, node:$rhs),
843 (setcc node:$lhs, node:$rhs, SETUEQ)>;
844 def setugt : PatFrag<(ops node:$lhs, node:$rhs),
845 (setcc node:$lhs, node:$rhs, SETUGT)>;
846 def setuge : PatFrag<(ops node:$lhs, node:$rhs),
847 (setcc node:$lhs, node:$rhs, SETUGE)>;
848 def setult : PatFrag<(ops node:$lhs, node:$rhs),
849 (setcc node:$lhs, node:$rhs, SETULT)>;
850 def setule : PatFrag<(ops node:$lhs, node:$rhs),
851 (setcc node:$lhs, node:$rhs, SETULE)>;
852 def setune : PatFrag<(ops node:$lhs, node:$rhs),
853 (setcc node:$lhs, node:$rhs, SETUNE)>;
854 def seteq : PatFrag<(ops node:$lhs, node:$rhs),
855 (setcc node:$lhs, node:$rhs, SETEQ)>;
856 def setgt : PatFrag<(ops node:$lhs, node:$rhs),
857 (setcc node:$lhs, node:$rhs, SETGT)>;
858 def setge : PatFrag<(ops node:$lhs, node:$rhs),
859 (setcc node:$lhs, node:$rhs, SETGE)>;
860 def setlt : PatFrag<(ops node:$lhs, node:$rhs),
861 (setcc node:$lhs, node:$rhs, SETLT)>;
862 def setle : PatFrag<(ops node:$lhs, node:$rhs),
863 (setcc node:$lhs, node:$rhs, SETLE)>;
864 def setne : PatFrag<(ops node:$lhs, node:$rhs),
865 (setcc node:$lhs, node:$rhs, SETNE)>;
867 //===----------------------------------------------------------------------===//
868 // Selection DAG Pattern Support.
870 // Patterns are what are actually matched against the target-flavored
871 // instruction selection DAG. Instructions defined by the target implicitly
872 // define patterns in most cases, but patterns can also be explicitly added when
873 // an operation is defined by a sequence of instructions (e.g. loading a large
874 // immediate value on RISC targets that do not support immediates as large as
878 class Pattern<dag patternToMatch, list<dag> resultInstrs> {
879 dag PatternToMatch = patternToMatch;
880 list<dag> ResultInstrs = resultInstrs;
881 list<Predicate> Predicates = []; // See class Instruction in Target.td.
882 int AddedComplexity = 0; // See class Instruction in Target.td.
885 // Pat - A simple (but common) form of a pattern, which produces a simple result
886 // not needing a full list.
887 class Pat<dag pattern, dag result> : Pattern<pattern, [result]>;
889 //===----------------------------------------------------------------------===//
890 // Complex pattern definitions.
894 // Pass the parent Operand as root to CP function rather
895 // than the root of the sub-DAG
896 def CPAttrParentAsRoot : CPAttribute;
898 // Complex patterns, e.g. X86 addressing mode, requires pattern matching code
899 // in C++. NumOperands is the number of operands returned by the select function;
900 // SelectFunc is the name of the function used to pattern match the max. pattern;
901 // RootNodes are the list of possible root nodes of the sub-dags to match.
902 // e.g. X86 addressing mode - def addr : ComplexPattern<4, "SelectAddr", [add]>;
904 class ComplexPattern<ValueType ty, int numops, string fn,
905 list<SDNode> roots = [], list<SDNodeProperty> props = [],
906 list<CPAttribute> attrs = []> {
908 int NumOperands = numops;
909 string SelectFunc = fn;
910 list<SDNode> RootNodes = roots;
911 list<SDNodeProperty> Properties = props;
912 list<CPAttribute> Attributes = attrs;
915 //===----------------------------------------------------------------------===//
918 def SDT_dwarf_loc : SDTypeProfile<0, 3,
919 [SDTCisInt<0>, SDTCisInt<1>, SDTCisInt<2>]>;
920 def dwarf_loc : SDNode<"ISD::DEBUG_LOC", SDT_dwarf_loc,[SDNPHasChain]>;