1 //===- TargetSelectionDAG.td - Common code for DAG isels ---*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the target-independent interfaces used by SelectionDAG
11 // instruction selection generators.
13 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
16 // Selection DAG Type Constraint definitions.
18 // Note that the semantics of these constraints are hard coded into tblgen. To
19 // modify or add constraints, you have to hack tblgen.
22 class SDTypeConstraint<int opnum> {
23 int OperandNum = opnum;
26 // SDTCisVT - The specified operand has exactly this VT.
27 class SDTCisVT<int OpNum, ValueType vt> : SDTypeConstraint<OpNum> {
31 class SDTCisPtrTy<int OpNum> : SDTypeConstraint<OpNum>;
33 // SDTCisInt - The specified operand is has integer type.
34 class SDTCisInt<int OpNum> : SDTypeConstraint<OpNum>;
36 // SDTCisFP - The specified operand is has floating point type.
37 class SDTCisFP<int OpNum> : SDTypeConstraint<OpNum>;
39 // SDTCisSameAs - The two specified operands have identical types.
40 class SDTCisSameAs<int OpNum, int OtherOp> : SDTypeConstraint<OpNum> {
41 int OtherOperandNum = OtherOp;
44 // SDTCisVTSmallerThanOp - The specified operand is a VT SDNode, and its type is
45 // smaller than the 'Other' operand.
46 class SDTCisVTSmallerThanOp<int OpNum, int OtherOp> : SDTypeConstraint<OpNum> {
47 int OtherOperandNum = OtherOp;
50 class SDTCisOpSmallerThanOp<int SmallOp, int BigOp> : SDTypeConstraint<SmallOp>{
51 int BigOperandNum = BigOp;
54 /// SDTCisIntVectorOfSameSize - This indicates that ThisOp and OtherOp are
55 /// vector types, and that ThisOp is the result of
56 /// MVT::getIntVectorWithNumElements with the number of elements that ThisOp
58 class SDTCisIntVectorOfSameSize<int ThisOp, int OtherOp>
59 : SDTypeConstraint<ThisOp> {
60 int OtherOpNum = OtherOp;
63 //===----------------------------------------------------------------------===//
64 // Selection DAG Type Profile definitions.
66 // These use the constraints defined above to describe the type requirements of
67 // the various nodes. These are not hard coded into tblgen, allowing targets to
68 // add their own if needed.
71 // SDTypeProfile - This profile describes the type requirements of a Selection
73 class SDTypeProfile<int numresults, int numoperands,
74 list<SDTypeConstraint> constraints> {
75 int NumResults = numresults;
76 int NumOperands = numoperands;
77 list<SDTypeConstraint> Constraints = constraints;
81 def SDTIntLeaf: SDTypeProfile<1, 0, [SDTCisInt<0>]>; // for 'imm'.
82 def SDTFPLeaf : SDTypeProfile<1, 0, [SDTCisFP<0>]>; // for 'fpimm'.
83 def SDTPtrLeaf: SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>; // for '&g'.
84 def SDTOther : SDTypeProfile<1, 0, [SDTCisVT<0, OtherVT>]>; // for 'vt'.
85 def SDTUNDEF : SDTypeProfile<1, 0, []>; // for 'undef'.
86 def SDTUnaryOp : SDTypeProfile<1, 1, []>; // bitconvert
88 def SDTIntBinOp : SDTypeProfile<1, 2, [ // add, and, or, xor, udiv, etc.
89 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<0>
91 def SDTIntShiftOp : SDTypeProfile<1, 2, [ // shl, sra, srl
92 SDTCisSameAs<0, 1>, SDTCisInt<0>, SDTCisInt<2>
94 def SDTFPBinOp : SDTypeProfile<1, 2, [ // fadd, fmul, etc.
95 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisFP<0>
97 def SDTFPSignOp : SDTypeProfile<1, 2, [ // fcopysign.
98 SDTCisSameAs<0, 1>, SDTCisFP<0>, SDTCisFP<2>
100 def SDTFPTernaryOp : SDTypeProfile<1, 3, [ // fmadd, fnmsub, etc.
101 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>, SDTCisFP<0>
103 def SDTIntUnaryOp : SDTypeProfile<1, 1, [ // ctlz
104 SDTCisSameAs<0, 1>, SDTCisInt<0>
106 def SDTIntExtendOp : SDTypeProfile<1, 1, [ // sext, zext, anyext
107 SDTCisInt<0>, SDTCisInt<1>, SDTCisOpSmallerThanOp<1, 0>
109 def SDTIntTruncOp : SDTypeProfile<1, 1, [ // trunc
110 SDTCisInt<0>, SDTCisInt<1>, SDTCisOpSmallerThanOp<0, 1>
112 def SDTFPUnaryOp : SDTypeProfile<1, 1, [ // fneg, fsqrt, etc
113 SDTCisSameAs<0, 1>, SDTCisFP<0>
115 def SDTFPRoundOp : SDTypeProfile<1, 1, [ // fround
116 SDTCisFP<0>, SDTCisFP<1>, SDTCisOpSmallerThanOp<0, 1>
118 def SDTFPExtendOp : SDTypeProfile<1, 1, [ // fextend
119 SDTCisFP<0>, SDTCisFP<1>, SDTCisOpSmallerThanOp<1, 0>
121 def SDTIntToFPOp : SDTypeProfile<1, 1, [ // [su]int_to_fp
122 SDTCisFP<0>, SDTCisInt<1>
124 def SDTFPToIntOp : SDTypeProfile<1, 1, [ // fp_to_[su]int
125 SDTCisInt<0>, SDTCisFP<1>
127 def SDTExtInreg : SDTypeProfile<1, 2, [ // sext_inreg
128 SDTCisSameAs<0, 1>, SDTCisInt<0>, SDTCisVT<2, OtherVT>,
129 SDTCisVTSmallerThanOp<2, 1>
132 def SDTSetCC : SDTypeProfile<1, 3, [ // setcc
133 SDTCisInt<0>, SDTCisSameAs<1, 2>, SDTCisVT<3, OtherVT>
136 def SDTSelect : SDTypeProfile<1, 3, [ // select
137 SDTCisInt<1>, SDTCisSameAs<0, 2>, SDTCisSameAs<2, 3>
140 def SDTSelectCC : SDTypeProfile<1, 5, [ // select_cc
141 SDTCisSameAs<1, 2>, SDTCisSameAs<3, 4>, SDTCisSameAs<0, 3>,
145 def SDTBr : SDTypeProfile<0, 1, [ // br
149 def SDTBrcond : SDTypeProfile<0, 2, [ // brcond
150 SDTCisInt<0>, SDTCisVT<1, OtherVT>
153 def SDTBrind : SDTypeProfile<0, 1, [ // brind
157 def SDTRet : SDTypeProfile<0, 0, []>; // ret
159 def SDTLoad : SDTypeProfile<1, 1, [ // load
163 def SDTStore : SDTypeProfile<0, 2, [ // store
167 def SDTIStore : SDTypeProfile<1, 3, [ // indexed store
168 SDTCisSameAs<0, 2>, SDTCisPtrTy<0>, SDTCisPtrTy<3>
171 def SDTVecShuffle : SDTypeProfile<1, 3, [
172 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisIntVectorOfSameSize<3, 0>
175 //===----------------------------------------------------------------------===//
176 // Selection DAG Node Properties.
178 // Note: These are hard coded into tblgen.
180 class SDNodeProperty;
181 def SDNPCommutative : SDNodeProperty; // X op Y == Y op X
182 def SDNPAssociative : SDNodeProperty; // (X op Y) op Z == X op (Y op Z)
183 def SDNPHasChain : SDNodeProperty; // R/W chain operand and result
184 def SDNPOutFlag : SDNodeProperty; // Write a flag result
185 def SDNPInFlag : SDNodeProperty; // Read a flag operand
186 def SDNPOptInFlag : SDNodeProperty; // Optionally read a flag operand
188 //===----------------------------------------------------------------------===//
189 // Selection DAG Node definitions.
191 class SDNode<string opcode, SDTypeProfile typeprof,
192 list<SDNodeProperty> props = [], string sdclass = "SDNode"> {
193 string Opcode = opcode;
194 string SDClass = sdclass;
195 list<SDNodeProperty> Properties = props;
196 SDTypeProfile TypeProfile = typeprof;
203 def imm : SDNode<"ISD::Constant" , SDTIntLeaf , [], "ConstantSDNode">;
204 def fpimm : SDNode<"ISD::TargetConstantFP",
205 SDTFPLeaf, [], "ConstantFPSDNode">;
206 def vt : SDNode<"ISD::VALUETYPE" , SDTOther , [], "VTSDNode">;
207 def bb : SDNode<"ISD::BasicBlock", SDTOther , [], "BasicBlockSDNode">;
208 def cond : SDNode<"ISD::CONDCODE" , SDTOther , [], "CondCodeSDNode">;
209 def undef : SDNode<"ISD::UNDEF" , SDTUNDEF , []>;
210 def globaladdr : SDNode<"ISD::GlobalAddress", SDTPtrLeaf, [],
211 "GlobalAddressSDNode">;
212 def tglobaladdr : SDNode<"ISD::TargetGlobalAddress", SDTPtrLeaf, [],
213 "GlobalAddressSDNode">;
214 def globaltlsaddr : SDNode<"ISD::GlobalTLSAddress", SDTPtrLeaf, [],
215 "GlobalAddressSDNode">;
216 def tglobaltlsaddr : SDNode<"ISD::TargetGlobalTLSAddress", SDTPtrLeaf, [],
217 "GlobalAddressSDNode">;
218 def constpool : SDNode<"ISD::ConstantPool", SDTPtrLeaf, [],
219 "ConstantPoolSDNode">;
220 def tconstpool : SDNode<"ISD::TargetConstantPool", SDTPtrLeaf, [],
221 "ConstantPoolSDNode">;
222 def jumptable : SDNode<"ISD::JumpTable", SDTPtrLeaf, [],
224 def tjumptable : SDNode<"ISD::TargetJumpTable", SDTPtrLeaf, [],
226 def frameindex : SDNode<"ISD::FrameIndex", SDTPtrLeaf, [],
228 def tframeindex : SDNode<"ISD::TargetFrameIndex", SDTPtrLeaf, [],
230 def externalsym : SDNode<"ISD::ExternalSymbol", SDTPtrLeaf, [],
231 "ExternalSymbolSDNode">;
232 def texternalsym: SDNode<"ISD::TargetExternalSymbol", SDTPtrLeaf, [],
233 "ExternalSymbolSDNode">;
235 def add : SDNode<"ISD::ADD" , SDTIntBinOp ,
236 [SDNPCommutative, SDNPAssociative]>;
237 def sub : SDNode<"ISD::SUB" , SDTIntBinOp>;
238 def mul : SDNode<"ISD::MUL" , SDTIntBinOp,
239 [SDNPCommutative, SDNPAssociative]>;
240 def mulhs : SDNode<"ISD::MULHS" , SDTIntBinOp, [SDNPCommutative]>;
241 def mulhu : SDNode<"ISD::MULHU" , SDTIntBinOp, [SDNPCommutative]>;
242 def sdiv : SDNode<"ISD::SDIV" , SDTIntBinOp>;
243 def udiv : SDNode<"ISD::UDIV" , SDTIntBinOp>;
244 def srem : SDNode<"ISD::SREM" , SDTIntBinOp>;
245 def urem : SDNode<"ISD::UREM" , SDTIntBinOp>;
246 def srl : SDNode<"ISD::SRL" , SDTIntShiftOp>;
247 def sra : SDNode<"ISD::SRA" , SDTIntShiftOp>;
248 def shl : SDNode<"ISD::SHL" , SDTIntShiftOp>;
249 def rotl : SDNode<"ISD::ROTL" , SDTIntShiftOp>;
250 def rotr : SDNode<"ISD::ROTR" , SDTIntShiftOp>;
251 def and : SDNode<"ISD::AND" , SDTIntBinOp,
252 [SDNPCommutative, SDNPAssociative]>;
253 def or : SDNode<"ISD::OR" , SDTIntBinOp,
254 [SDNPCommutative, SDNPAssociative]>;
255 def xor : SDNode<"ISD::XOR" , SDTIntBinOp,
256 [SDNPCommutative, SDNPAssociative]>;
257 def addc : SDNode<"ISD::ADDC" , SDTIntBinOp,
258 [SDNPCommutative, SDNPOutFlag]>;
259 def adde : SDNode<"ISD::ADDE" , SDTIntBinOp,
260 [SDNPCommutative, SDNPOutFlag, SDNPInFlag]>;
261 def subc : SDNode<"ISD::SUBC" , SDTIntBinOp,
263 def sube : SDNode<"ISD::SUBE" , SDTIntBinOp,
264 [SDNPOutFlag, SDNPInFlag]>;
266 def sext_inreg : SDNode<"ISD::SIGN_EXTEND_INREG", SDTExtInreg>;
267 def bswap : SDNode<"ISD::BSWAP" , SDTIntUnaryOp>;
268 def ctlz : SDNode<"ISD::CTLZ" , SDTIntUnaryOp>;
269 def cttz : SDNode<"ISD::CTTZ" , SDTIntUnaryOp>;
270 def ctpop : SDNode<"ISD::CTPOP" , SDTIntUnaryOp>;
271 def sext : SDNode<"ISD::SIGN_EXTEND", SDTIntExtendOp>;
272 def zext : SDNode<"ISD::ZERO_EXTEND", SDTIntExtendOp>;
273 def anyext : SDNode<"ISD::ANY_EXTEND" , SDTIntExtendOp>;
274 def trunc : SDNode<"ISD::TRUNCATE" , SDTIntTruncOp>;
275 def bitconvert : SDNode<"ISD::BIT_CONVERT", SDTUnaryOp>;
277 def fadd : SDNode<"ISD::FADD" , SDTFPBinOp, [SDNPCommutative]>;
278 def fsub : SDNode<"ISD::FSUB" , SDTFPBinOp>;
279 def fmul : SDNode<"ISD::FMUL" , SDTFPBinOp, [SDNPCommutative]>;
280 def fdiv : SDNode<"ISD::FDIV" , SDTFPBinOp>;
281 def frem : SDNode<"ISD::FREM" , SDTFPBinOp>;
282 def fabs : SDNode<"ISD::FABS" , SDTFPUnaryOp>;
283 def fneg : SDNode<"ISD::FNEG" , SDTFPUnaryOp>;
284 def fsqrt : SDNode<"ISD::FSQRT" , SDTFPUnaryOp>;
285 def fsin : SDNode<"ISD::FSIN" , SDTFPUnaryOp>;
286 def fcos : SDNode<"ISD::FCOS" , SDTFPUnaryOp>;
288 def fround : SDNode<"ISD::FP_ROUND" , SDTFPRoundOp>;
289 def fextend : SDNode<"ISD::FP_EXTEND" , SDTFPExtendOp>;
290 def fcopysign : SDNode<"ISD::FCOPYSIGN" , SDTFPSignOp>;
292 def sint_to_fp : SDNode<"ISD::SINT_TO_FP" , SDTIntToFPOp>;
293 def uint_to_fp : SDNode<"ISD::UINT_TO_FP" , SDTIntToFPOp>;
294 def fp_to_sint : SDNode<"ISD::FP_TO_SINT" , SDTFPToIntOp>;
295 def fp_to_uint : SDNode<"ISD::FP_TO_UINT" , SDTFPToIntOp>;
297 def setcc : SDNode<"ISD::SETCC" , SDTSetCC>;
298 def select : SDNode<"ISD::SELECT" , SDTSelect>;
299 def selectcc : SDNode<"ISD::SELECT_CC" , SDTSelectCC>;
301 def brcond : SDNode<"ISD::BRCOND" , SDTBrcond, [SDNPHasChain]>;
302 def brind : SDNode<"ISD::BRIND" , SDTBrind, [SDNPHasChain]>;
303 def br : SDNode<"ISD::BR" , SDTBr, [SDNPHasChain]>;
304 def ret : SDNode<"ISD::RET" , SDTRet, [SDNPHasChain]>;
306 // Do not use ld, st directly. Use load, extload, sextload, zextload, store,
307 // and truncst (see below).
308 def ld : SDNode<"ISD::LOAD" , SDTLoad, [SDNPHasChain]>;
309 def st : SDNode<"ISD::STORE" , SDTStore, [SDNPHasChain]>;
310 def ist : SDNode<"ISD::STORE" , SDTIStore, [SDNPHasChain]>;
312 def vector_shuffle : SDNode<"ISD::VECTOR_SHUFFLE", SDTVecShuffle, []>;
313 def build_vector : SDNode<"ISD::BUILD_VECTOR", SDTypeProfile<1, 0, []>, []>;
314 def scalar_to_vector : SDNode<"ISD::SCALAR_TO_VECTOR", SDTypeProfile<1, 1, []>,
316 def vector_extract : SDNode<"ISD::EXTRACT_VECTOR_ELT",
317 SDTypeProfile<1, 2, [SDTCisPtrTy<2>]>, []>;
318 def vector_insert : SDNode<"ISD::INSERT_VECTOR_ELT",
319 SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisPtrTy<3>]>, []>;
321 // Nodes for intrinsics, you should use the intrinsic itself and let tblgen use
322 // these internally. Don't reference these directly.
323 def intrinsic_void : SDNode<"ISD::INTRINSIC_VOID",
324 SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>,
326 def intrinsic_w_chain : SDNode<"ISD::INTRINSIC_W_CHAIN",
327 SDTypeProfile<1, -1, [SDTCisPtrTy<1>]>,
329 def intrinsic_wo_chain : SDNode<"ISD::INTRINSIC_WO_CHAIN",
330 SDTypeProfile<1, -1, [SDTCisPtrTy<1>]>, []>;
333 //===----------------------------------------------------------------------===//
334 // Selection DAG Condition Codes
336 class CondCode; // ISD::CondCode enums
337 def SETOEQ : CondCode; def SETOGT : CondCode;
338 def SETOGE : CondCode; def SETOLT : CondCode; def SETOLE : CondCode;
339 def SETONE : CondCode; def SETO : CondCode; def SETUO : CondCode;
340 def SETUEQ : CondCode; def SETUGT : CondCode; def SETUGE : CondCode;
341 def SETULT : CondCode; def SETULE : CondCode; def SETUNE : CondCode;
343 def SETEQ : CondCode; def SETGT : CondCode; def SETGE : CondCode;
344 def SETLT : CondCode; def SETLE : CondCode; def SETNE : CondCode;
347 //===----------------------------------------------------------------------===//
348 // Selection DAG Node Transformation Functions.
350 // This mechanism allows targets to manipulate nodes in the output DAG once a
351 // match has been formed. This is typically used to manipulate immediate
354 class SDNodeXForm<SDNode opc, code xformFunction> {
356 code XFormFunction = xformFunction;
359 def NOOP_SDNodeXForm : SDNodeXForm<imm, [{}]>;
362 //===----------------------------------------------------------------------===//
363 // Selection DAG Pattern Fragments.
365 // Pattern fragments are reusable chunks of dags that match specific things.
366 // They can take arguments and have C++ predicates that control whether they
367 // match. They are intended to make the patterns for common instructions more
368 // compact and readable.
371 /// PatFrag - Represents a pattern fragment. This can match something on the
372 /// DAG, frame a single node to multiply nested other fragments.
374 class PatFrag<dag ops, dag frag, code pred = [{}],
375 SDNodeXForm xform = NOOP_SDNodeXForm> {
378 code Predicate = pred;
379 SDNodeXForm OperandTransform = xform;
382 // PatLeaf's are pattern fragments that have no operands. This is just a helper
383 // to define immediates and other common things concisely.
384 class PatLeaf<dag frag, code pred = [{}], SDNodeXForm xform = NOOP_SDNodeXForm>
385 : PatFrag<(ops), frag, pred, xform>;
389 def vtInt : PatLeaf<(vt), [{ return MVT::isInteger(N->getVT()); }]>;
390 def vtFP : PatLeaf<(vt), [{ return MVT::isFloatingPoint(N->getVT()); }]>;
392 def immAllOnes : PatLeaf<(imm), [{ return N->isAllOnesValue(); }]>;
393 def immAllOnesV: PatLeaf<(build_vector), [{
394 return ISD::isBuildVectorAllOnes(N);
396 def immAllZerosV: PatLeaf<(build_vector), [{
397 return ISD::isBuildVectorAllZeros(N);
400 def immAllOnesV_bc: PatLeaf<(bitconvert), [{
401 return ISD::isBuildVectorAllOnes(N);
405 // Other helper fragments.
406 def not : PatFrag<(ops node:$in), (xor node:$in, immAllOnes)>;
407 def vnot : PatFrag<(ops node:$in), (xor node:$in, immAllOnesV)>;
408 def vnot_conv : PatFrag<(ops node:$in), (xor node:$in, immAllOnesV_bc)>;
409 def ineg : PatFrag<(ops node:$in), (sub 0, node:$in)>;
412 def load : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
413 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
414 return LD->getExtensionType() == ISD::NON_EXTLOAD &&
415 LD->getAddressingMode() == ISD::UNINDEXED;
419 // extending load fragments.
420 def extloadi1 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
421 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
422 return LD->getExtensionType() == ISD::EXTLOAD &&
423 LD->getAddressingMode() == ISD::UNINDEXED &&
424 LD->getLoadedVT() == MVT::i1;
427 def extloadi8 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
428 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
429 return LD->getExtensionType() == ISD::EXTLOAD &&
430 LD->getAddressingMode() == ISD::UNINDEXED &&
431 LD->getLoadedVT() == MVT::i8;
434 def extloadi16 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
435 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
436 return LD->getExtensionType() == ISD::EXTLOAD &&
437 LD->getAddressingMode() == ISD::UNINDEXED &&
438 LD->getLoadedVT() == MVT::i16;
441 def extloadi32 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
442 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
443 return LD->getExtensionType() == ISD::EXTLOAD &&
444 LD->getAddressingMode() == ISD::UNINDEXED &&
445 LD->getLoadedVT() == MVT::i32;
448 def extloadf32 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
449 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
450 return LD->getExtensionType() == ISD::EXTLOAD &&
451 LD->getAddressingMode() == ISD::UNINDEXED &&
452 LD->getLoadedVT() == MVT::f32;
456 def sextloadi1 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
457 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
458 return LD->getExtensionType() == ISD::SEXTLOAD &&
459 LD->getAddressingMode() == ISD::UNINDEXED &&
460 LD->getLoadedVT() == MVT::i1;
463 def sextloadi8 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
464 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
465 return LD->getExtensionType() == ISD::SEXTLOAD &&
466 LD->getAddressingMode() == ISD::UNINDEXED &&
467 LD->getLoadedVT() == MVT::i8;
470 def sextloadi16 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
471 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
472 return LD->getExtensionType() == ISD::SEXTLOAD &&
473 LD->getAddressingMode() == ISD::UNINDEXED &&
474 LD->getLoadedVT() == MVT::i16;
477 def sextloadi32 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
478 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
479 return LD->getExtensionType() == ISD::SEXTLOAD &&
480 LD->getAddressingMode() == ISD::UNINDEXED &&
481 LD->getLoadedVT() == MVT::i32;
485 def zextloadi1 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
486 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
487 return LD->getExtensionType() == ISD::ZEXTLOAD &&
488 LD->getAddressingMode() == ISD::UNINDEXED &&
489 LD->getLoadedVT() == MVT::i1;
492 def zextloadi8 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
493 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
494 return LD->getExtensionType() == ISD::ZEXTLOAD &&
495 LD->getAddressingMode() == ISD::UNINDEXED &&
496 LD->getLoadedVT() == MVT::i8;
499 def zextloadi16 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
500 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
501 return LD->getExtensionType() == ISD::ZEXTLOAD &&
502 LD->getAddressingMode() == ISD::UNINDEXED &&
503 LD->getLoadedVT() == MVT::i16;
506 def zextloadi32 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
507 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
508 return LD->getExtensionType() == ISD::ZEXTLOAD &&
509 LD->getAddressingMode() == ISD::UNINDEXED &&
510 LD->getLoadedVT() == MVT::i32;
515 def store : PatFrag<(ops node:$val, node:$ptr),
516 (st node:$val, node:$ptr), [{
517 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
518 return !ST->isTruncatingStore() &&
519 ST->getAddressingMode() == ISD::UNINDEXED;
523 // truncstore fragments.
524 def truncstorei1 : PatFrag<(ops node:$val, node:$ptr),
525 (st node:$val, node:$ptr), [{
526 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
527 return ST->isTruncatingStore() && ST->getStoredVT() == MVT::i1 &&
528 ST->getAddressingMode() == ISD::UNINDEXED;
531 def truncstorei8 : PatFrag<(ops node:$val, node:$ptr),
532 (st node:$val, node:$ptr), [{
533 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
534 return ST->isTruncatingStore() && ST->getStoredVT() == MVT::i8 &&
535 ST->getAddressingMode() == ISD::UNINDEXED;
538 def truncstorei16 : PatFrag<(ops node:$val, node:$ptr),
539 (st node:$val, node:$ptr), [{
540 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
541 return ST->isTruncatingStore() && ST->getStoredVT() == MVT::i16 &&
542 ST->getAddressingMode() == ISD::UNINDEXED;
545 def truncstorei32 : PatFrag<(ops node:$val, node:$ptr),
546 (st node:$val, node:$ptr), [{
547 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
548 return ST->isTruncatingStore() && ST->getStoredVT() == MVT::i32 &&
549 ST->getAddressingMode() == ISD::UNINDEXED;
552 def truncstoref32 : PatFrag<(ops node:$val, node:$ptr),
553 (st node:$val, node:$ptr), [{
554 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
555 return ST->isTruncatingStore() && ST->getStoredVT() == MVT::f32 &&
556 ST->getAddressingMode() == ISD::UNINDEXED;
560 // indexed store fragments.
561 def pre_store : PatFrag<(ops node:$val, node:$base, node:$offset),
562 (ist node:$val, node:$base, node:$offset), [{
563 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
564 ISD::MemIndexedMode AM = ST->getAddressingMode();
565 return (AM == ISD::PRE_INC || AM == ISD::PRE_DEC) &&
566 !ST->isTruncatingStore();
571 def pre_truncsti1 : PatFrag<(ops node:$val, node:$base, node:$offset),
572 (ist node:$val, node:$base, node:$offset), [{
573 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
574 ISD::MemIndexedMode AM = ST->getAddressingMode();
575 return (AM == ISD::PRE_INC || AM == ISD::PRE_DEC) &&
576 ST->isTruncatingStore() && ST->getStoredVT() == MVT::i1;
580 def pre_truncsti8 : PatFrag<(ops node:$val, node:$base, node:$offset),
581 (ist node:$val, node:$base, node:$offset), [{
582 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
583 ISD::MemIndexedMode AM = ST->getAddressingMode();
584 return (AM == ISD::PRE_INC || AM == ISD::PRE_DEC) &&
585 ST->isTruncatingStore() && ST->getStoredVT() == MVT::i8;
589 def pre_truncsti16 : PatFrag<(ops node:$val, node:$base, node:$offset),
590 (ist node:$val, node:$base, node:$offset), [{
591 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
592 ISD::MemIndexedMode AM = ST->getAddressingMode();
593 return (AM == ISD::PRE_INC || AM == ISD::PRE_DEC) &&
594 ST->isTruncatingStore() && ST->getStoredVT() == MVT::i16;
598 def pre_truncsti32 : PatFrag<(ops node:$val, node:$base, node:$offset),
599 (ist node:$val, node:$base, node:$offset), [{
600 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
601 ISD::MemIndexedMode AM = ST->getAddressingMode();
602 return (AM == ISD::PRE_INC || AM == ISD::PRE_DEC) &&
603 ST->isTruncatingStore() && ST->getStoredVT() == MVT::i32;
607 def pre_truncstf32 : PatFrag<(ops node:$val, node:$base, node:$offset),
608 (ist node:$val, node:$base, node:$offset), [{
609 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
610 ISD::MemIndexedMode AM = ST->getAddressingMode();
611 return (AM == ISD::PRE_INC || AM == ISD::PRE_DEC) &&
612 ST->isTruncatingStore() && ST->getStoredVT() == MVT::f32;
617 def post_store : PatFrag<(ops node:$val, node:$ptr, node:$offset),
618 (ist node:$val, node:$ptr, node:$offset), [{
619 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
620 ISD::MemIndexedMode AM = ST->getAddressingMode();
621 return !ST->isTruncatingStore() &&
622 (AM == ISD::POST_INC || AM == ISD::POST_DEC);
627 def post_truncsti1 : PatFrag<(ops node:$val, node:$base, node:$offset),
628 (ist node:$val, node:$base, node:$offset), [{
629 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
630 ISD::MemIndexedMode AM = ST->getAddressingMode();
631 return (AM == ISD::POST_INC || AM == ISD::POST_DEC) &&
632 ST->isTruncatingStore() && ST->getStoredVT() == MVT::i1;
636 def post_truncsti8 : PatFrag<(ops node:$val, node:$base, node:$offset),
637 (ist node:$val, node:$base, node:$offset), [{
638 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
639 ISD::MemIndexedMode AM = ST->getAddressingMode();
640 return (AM == ISD::POST_INC || AM == ISD::POST_DEC) &&
641 ST->isTruncatingStore() && ST->getStoredVT() == MVT::i8;
645 def post_truncsti16 : PatFrag<(ops node:$val, node:$base, node:$offset),
646 (ist node:$val, node:$base, node:$offset), [{
647 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
648 ISD::MemIndexedMode AM = ST->getAddressingMode();
649 return (AM == ISD::POST_INC || AM == ISD::POST_DEC) &&
650 ST->isTruncatingStore() && ST->getStoredVT() == MVT::i16;
654 def post_truncsti32 : PatFrag<(ops node:$val, node:$base, node:$offset),
655 (ist node:$val, node:$base, node:$offset), [{
656 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
657 ISD::MemIndexedMode AM = ST->getAddressingMode();
658 return (AM == ISD::POST_INC || AM == ISD::POST_DEC) &&
659 ST->isTruncatingStore() && ST->getStoredVT() == MVT::i32;
663 def post_truncstf32 : PatFrag<(ops node:$val, node:$base, node:$offset),
664 (ist node:$val, node:$base, node:$offset), [{
665 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
666 ISD::MemIndexedMode AM = ST->getAddressingMode();
667 return (AM == ISD::POST_INC || AM == ISD::POST_DEC) &&
668 ST->isTruncatingStore() && ST->getStoredVT() == MVT::f32;
673 // setcc convenience fragments.
674 def setoeq : PatFrag<(ops node:$lhs, node:$rhs),
675 (setcc node:$lhs, node:$rhs, SETOEQ)>;
676 def setogt : PatFrag<(ops node:$lhs, node:$rhs),
677 (setcc node:$lhs, node:$rhs, SETOGT)>;
678 def setoge : PatFrag<(ops node:$lhs, node:$rhs),
679 (setcc node:$lhs, node:$rhs, SETOGE)>;
680 def setolt : PatFrag<(ops node:$lhs, node:$rhs),
681 (setcc node:$lhs, node:$rhs, SETOLT)>;
682 def setole : PatFrag<(ops node:$lhs, node:$rhs),
683 (setcc node:$lhs, node:$rhs, SETOLE)>;
684 def setone : PatFrag<(ops node:$lhs, node:$rhs),
685 (setcc node:$lhs, node:$rhs, SETONE)>;
686 def seto : PatFrag<(ops node:$lhs, node:$rhs),
687 (setcc node:$lhs, node:$rhs, SETO)>;
688 def setuo : PatFrag<(ops node:$lhs, node:$rhs),
689 (setcc node:$lhs, node:$rhs, SETUO)>;
690 def setueq : PatFrag<(ops node:$lhs, node:$rhs),
691 (setcc node:$lhs, node:$rhs, SETUEQ)>;
692 def setugt : PatFrag<(ops node:$lhs, node:$rhs),
693 (setcc node:$lhs, node:$rhs, SETUGT)>;
694 def setuge : PatFrag<(ops node:$lhs, node:$rhs),
695 (setcc node:$lhs, node:$rhs, SETUGE)>;
696 def setult : PatFrag<(ops node:$lhs, node:$rhs),
697 (setcc node:$lhs, node:$rhs, SETULT)>;
698 def setule : PatFrag<(ops node:$lhs, node:$rhs),
699 (setcc node:$lhs, node:$rhs, SETULE)>;
700 def setune : PatFrag<(ops node:$lhs, node:$rhs),
701 (setcc node:$lhs, node:$rhs, SETUNE)>;
702 def seteq : PatFrag<(ops node:$lhs, node:$rhs),
703 (setcc node:$lhs, node:$rhs, SETEQ)>;
704 def setgt : PatFrag<(ops node:$lhs, node:$rhs),
705 (setcc node:$lhs, node:$rhs, SETGT)>;
706 def setge : PatFrag<(ops node:$lhs, node:$rhs),
707 (setcc node:$lhs, node:$rhs, SETGE)>;
708 def setlt : PatFrag<(ops node:$lhs, node:$rhs),
709 (setcc node:$lhs, node:$rhs, SETLT)>;
710 def setle : PatFrag<(ops node:$lhs, node:$rhs),
711 (setcc node:$lhs, node:$rhs, SETLE)>;
712 def setne : PatFrag<(ops node:$lhs, node:$rhs),
713 (setcc node:$lhs, node:$rhs, SETNE)>;
715 //===----------------------------------------------------------------------===//
716 // Selection DAG Pattern Support.
718 // Patterns are what are actually matched against the target-flavored
719 // instruction selection DAG. Instructions defined by the target implicitly
720 // define patterns in most cases, but patterns can also be explicitly added when
721 // an operation is defined by a sequence of instructions (e.g. loading a large
722 // immediate value on RISC targets that do not support immediates as large as
726 class Pattern<dag patternToMatch, list<dag> resultInstrs> {
727 dag PatternToMatch = patternToMatch;
728 list<dag> ResultInstrs = resultInstrs;
729 list<Predicate> Predicates = []; // See class Instruction in Target.td.
730 int AddedComplexity = 0; // See class Instruction in Target.td.
733 // Pat - A simple (but common) form of a pattern, which produces a simple result
734 // not needing a full list.
735 class Pat<dag pattern, dag result> : Pattern<pattern, [result]>;
737 //===----------------------------------------------------------------------===//
738 // Complex pattern definitions.
740 // Complex patterns, e.g. X86 addressing mode, requires pattern matching code
741 // in C++. NumOperands is the number of operands returned by the select function;
742 // SelectFunc is the name of the function used to pattern match the max. pattern;
743 // RootNodes are the list of possible root nodes of the sub-dags to match.
744 // e.g. X86 addressing mode - def addr : ComplexPattern<4, "SelectAddr", [add]>;
746 class ComplexPattern<ValueType ty, int numops, string fn,
747 list<SDNode> roots = [], list<SDNodeProperty> props = []> {
749 int NumOperands = numops;
750 string SelectFunc = fn;
751 list<SDNode> RootNodes = roots;
752 list<SDNodeProperty> Properties = props;
755 //===----------------------------------------------------------------------===//
758 def SDT_dwarf_loc : SDTypeProfile<0, 3,
759 [SDTCisInt<0>, SDTCisInt<1>, SDTCisInt<2>]>;
760 def dwarf_loc : SDNode<"ISD::DEBUG_LOC", SDT_dwarf_loc,[SDNPHasChain]>;