1 //===- TargetSelectionDAG.td - Common code for DAG isels ---*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the target-independent interfaces used by SelectionDAG
11 // instruction selection generators.
13 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
16 // Selection DAG Type Constraint definitions.
18 // Note that the semantics of these constraints are hard coded into tblgen. To
19 // modify or add constraints, you have to hack tblgen.
22 class SDTypeConstraint<int opnum> {
23 int OperandNum = opnum;
26 // SDTCisVT - The specified operand has exactly this VT.
27 class SDTCisVT<int OpNum, ValueType vt> : SDTypeConstraint<OpNum> {
31 class SDTCisPtrTy<int OpNum> : SDTypeConstraint<OpNum>;
33 // SDTCisInt - The specified operand is has integer type.
34 class SDTCisInt<int OpNum> : SDTypeConstraint<OpNum>;
36 // SDTCisFP - The specified operand is has floating point type.
37 class SDTCisFP<int OpNum> : SDTypeConstraint<OpNum>;
39 // SDTCisSameAs - The two specified operands have identical types.
40 class SDTCisSameAs<int OpNum, int OtherOp> : SDTypeConstraint<OpNum> {
41 int OtherOperandNum = OtherOp;
44 // SDTCisVTSmallerThanOp - The specified operand is a VT SDNode, and its type is
45 // smaller than the 'Other' operand.
46 class SDTCisVTSmallerThanOp<int OpNum, int OtherOp> : SDTypeConstraint<OpNum> {
47 int OtherOperandNum = OtherOp;
50 class SDTCisOpSmallerThanOp<int SmallOp, int BigOp> : SDTypeConstraint<SmallOp>{
51 int BigOperandNum = BigOp;
54 /// SDTCisIntVectorOfSameSize - This indicates that ThisOp and OtherOp are
55 /// vector types, and that ThisOp is the result of
56 /// MVT::getIntVectorWithNumElements with the number of elements that ThisOp
58 class SDTCisIntVectorOfSameSize<int ThisOp, int OtherOp>
59 : SDTypeConstraint<ThisOp> {
60 int OtherOpNum = OtherOp;
63 //===----------------------------------------------------------------------===//
64 // Selection DAG Type Profile definitions.
66 // These use the constraints defined above to describe the type requirements of
67 // the various nodes. These are not hard coded into tblgen, allowing targets to
68 // add their own if needed.
71 // SDTypeProfile - This profile describes the type requirements of a Selection
73 class SDTypeProfile<int numresults, int numoperands,
74 list<SDTypeConstraint> constraints> {
75 int NumResults = numresults;
76 int NumOperands = numoperands;
77 list<SDTypeConstraint> Constraints = constraints;
81 def SDTIntLeaf: SDTypeProfile<1, 0, [SDTCisInt<0>]>; // for 'imm'.
82 def SDTFPLeaf : SDTypeProfile<1, 0, [SDTCisFP<0>]>; // for 'fpimm'.
83 def SDTPtrLeaf: SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>; // for '&g'.
84 def SDTOther : SDTypeProfile<1, 0, [SDTCisVT<0, OtherVT>]>; // for 'vt'.
85 def SDTUNDEF : SDTypeProfile<1, 0, []>; // for 'undef'.
86 def SDTUnaryOp : SDTypeProfile<1, 1, []>; // bitconvert
88 def SDTIntBinOp : SDTypeProfile<1, 2, [ // add, and, or, xor, udiv, etc.
89 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<0>
91 def SDTIntShiftOp : SDTypeProfile<1, 2, [ // shl, sra, srl
92 SDTCisSameAs<0, 1>, SDTCisInt<0>, SDTCisInt<2>
94 def SDTFPBinOp : SDTypeProfile<1, 2, [ // fadd, fmul, etc.
95 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisFP<0>
97 def SDTFPSignOp : SDTypeProfile<1, 2, [ // fcopysign.
98 SDTCisSameAs<0, 1>, SDTCisFP<0>, SDTCisFP<2>
100 def SDTFPTernaryOp : SDTypeProfile<1, 3, [ // fmadd, fnmsub, etc.
101 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>, SDTCisFP<0>
103 def SDTIntUnaryOp : SDTypeProfile<1, 1, [ // ctlz
104 SDTCisSameAs<0, 1>, SDTCisInt<0>
106 def SDTIntExtendOp : SDTypeProfile<1, 1, [ // sext, zext, anyext
107 SDTCisInt<0>, SDTCisInt<1>, SDTCisOpSmallerThanOp<1, 0>
109 def SDTIntTruncOp : SDTypeProfile<1, 1, [ // trunc
110 SDTCisInt<0>, SDTCisInt<1>, SDTCisOpSmallerThanOp<0, 1>
112 def SDTFPUnaryOp : SDTypeProfile<1, 1, [ // fneg, fsqrt, etc
113 SDTCisSameAs<0, 1>, SDTCisFP<0>
115 def SDTFPRoundOp : SDTypeProfile<1, 1, [ // fround
116 SDTCisFP<0>, SDTCisFP<1>, SDTCisOpSmallerThanOp<0, 1>
118 def SDTFPExtendOp : SDTypeProfile<1, 1, [ // fextend
119 SDTCisFP<0>, SDTCisFP<1>, SDTCisOpSmallerThanOp<1, 0>
121 def SDTIntToFPOp : SDTypeProfile<1, 1, [ // [su]int_to_fp
122 SDTCisFP<0>, SDTCisInt<1>
124 def SDTFPToIntOp : SDTypeProfile<1, 1, [ // fp_to_[su]int
125 SDTCisInt<0>, SDTCisFP<1>
127 def SDTExtInreg : SDTypeProfile<1, 2, [ // sext_inreg
128 SDTCisSameAs<0, 1>, SDTCisInt<0>, SDTCisVT<2, OtherVT>,
129 SDTCisVTSmallerThanOp<2, 1>
132 def SDTSetCC : SDTypeProfile<1, 3, [ // setcc
133 SDTCisInt<0>, SDTCisSameAs<1, 2>, SDTCisVT<3, OtherVT>
136 def SDTSelect : SDTypeProfile<1, 3, [ // select
137 SDTCisInt<1>, SDTCisSameAs<0, 2>, SDTCisSameAs<2, 3>
140 def SDTSelectCC : SDTypeProfile<1, 5, [ // select_cc
141 SDTCisSameAs<1, 2>, SDTCisSameAs<3, 4>, SDTCisSameAs<0, 3>,
145 def SDTBr : SDTypeProfile<0, 1, [ // br
149 def SDTBrcond : SDTypeProfile<0, 2, [ // brcond
150 SDTCisInt<0>, SDTCisVT<1, OtherVT>
153 def SDTBrind : SDTypeProfile<0, 1, [ // brind
157 def SDTRet : SDTypeProfile<0, 0, []>; // ret
159 def SDTLoad : SDTypeProfile<1, 1, [ // load
163 def SDTStore : SDTypeProfile<0, 2, [ // store
167 def SDTIStore : SDTypeProfile<1, 3, [ // indexed store
168 SDTCisSameAs<0, 2>, SDTCisPtrTy<0>, SDTCisPtrTy<3>
171 def SDTVecShuffle : SDTypeProfile<1, 3, [
172 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisIntVectorOfSameSize<3, 0>
175 class SDCallSeqStart<list<SDTypeConstraint> constraints> :
176 SDTypeProfile<0, 1, constraints>;
177 class SDCallSeqEnd<list<SDTypeConstraint> constraints> :
178 SDTypeProfile<0, 2, constraints>;
180 //===----------------------------------------------------------------------===//
181 // Selection DAG Node Properties.
183 // Note: These are hard coded into tblgen.
185 class SDNodeProperty;
186 def SDNPCommutative : SDNodeProperty; // X op Y == Y op X
187 def SDNPAssociative : SDNodeProperty; // (X op Y) op Z == X op (Y op Z)
188 def SDNPHasChain : SDNodeProperty; // R/W chain operand and result
189 def SDNPOutFlag : SDNodeProperty; // Write a flag result
190 def SDNPInFlag : SDNodeProperty; // Read a flag operand
191 def SDNPOptInFlag : SDNodeProperty; // Optionally read a flag operand
192 def SDNPMayStore : SDNodeProperty; // May write to memory, sets 'isStore'.
194 //===----------------------------------------------------------------------===//
195 // Selection DAG Node definitions.
197 class SDNode<string opcode, SDTypeProfile typeprof,
198 list<SDNodeProperty> props = [], string sdclass = "SDNode"> {
199 string Opcode = opcode;
200 string SDClass = sdclass;
201 list<SDNodeProperty> Properties = props;
202 SDTypeProfile TypeProfile = typeprof;
211 def imm : SDNode<"ISD::Constant" , SDTIntLeaf , [], "ConstantSDNode">;
212 def fpimm : SDNode<"ISD::TargetConstantFP",
213 SDTFPLeaf, [], "ConstantFPSDNode">;
214 def vt : SDNode<"ISD::VALUETYPE" , SDTOther , [], "VTSDNode">;
215 def bb : SDNode<"ISD::BasicBlock", SDTOther , [], "BasicBlockSDNode">;
216 def cond : SDNode<"ISD::CONDCODE" , SDTOther , [], "CondCodeSDNode">;
217 def undef : SDNode<"ISD::UNDEF" , SDTUNDEF , []>;
218 def globaladdr : SDNode<"ISD::GlobalAddress", SDTPtrLeaf, [],
219 "GlobalAddressSDNode">;
220 def tglobaladdr : SDNode<"ISD::TargetGlobalAddress", SDTPtrLeaf, [],
221 "GlobalAddressSDNode">;
222 def globaltlsaddr : SDNode<"ISD::GlobalTLSAddress", SDTPtrLeaf, [],
223 "GlobalAddressSDNode">;
224 def tglobaltlsaddr : SDNode<"ISD::TargetGlobalTLSAddress", SDTPtrLeaf, [],
225 "GlobalAddressSDNode">;
226 def constpool : SDNode<"ISD::ConstantPool", SDTPtrLeaf, [],
227 "ConstantPoolSDNode">;
228 def tconstpool : SDNode<"ISD::TargetConstantPool", SDTPtrLeaf, [],
229 "ConstantPoolSDNode">;
230 def jumptable : SDNode<"ISD::JumpTable", SDTPtrLeaf, [],
232 def tjumptable : SDNode<"ISD::TargetJumpTable", SDTPtrLeaf, [],
234 def frameindex : SDNode<"ISD::FrameIndex", SDTPtrLeaf, [],
236 def tframeindex : SDNode<"ISD::TargetFrameIndex", SDTPtrLeaf, [],
238 def externalsym : SDNode<"ISD::ExternalSymbol", SDTPtrLeaf, [],
239 "ExternalSymbolSDNode">;
240 def texternalsym: SDNode<"ISD::TargetExternalSymbol", SDTPtrLeaf, [],
241 "ExternalSymbolSDNode">;
243 def add : SDNode<"ISD::ADD" , SDTIntBinOp ,
244 [SDNPCommutative, SDNPAssociative]>;
245 def sub : SDNode<"ISD::SUB" , SDTIntBinOp>;
246 def mul : SDNode<"ISD::MUL" , SDTIntBinOp,
247 [SDNPCommutative, SDNPAssociative]>;
248 def mulhs : SDNode<"ISD::MULHS" , SDTIntBinOp, [SDNPCommutative]>;
249 def mulhu : SDNode<"ISD::MULHU" , SDTIntBinOp, [SDNPCommutative]>;
250 def sdiv : SDNode<"ISD::SDIV" , SDTIntBinOp>;
251 def udiv : SDNode<"ISD::UDIV" , SDTIntBinOp>;
252 def srem : SDNode<"ISD::SREM" , SDTIntBinOp>;
253 def urem : SDNode<"ISD::UREM" , SDTIntBinOp>;
254 def srl : SDNode<"ISD::SRL" , SDTIntShiftOp>;
255 def sra : SDNode<"ISD::SRA" , SDTIntShiftOp>;
256 def shl : SDNode<"ISD::SHL" , SDTIntShiftOp>;
257 def rotl : SDNode<"ISD::ROTL" , SDTIntShiftOp>;
258 def rotr : SDNode<"ISD::ROTR" , SDTIntShiftOp>;
259 def and : SDNode<"ISD::AND" , SDTIntBinOp,
260 [SDNPCommutative, SDNPAssociative]>;
261 def or : SDNode<"ISD::OR" , SDTIntBinOp,
262 [SDNPCommutative, SDNPAssociative]>;
263 def xor : SDNode<"ISD::XOR" , SDTIntBinOp,
264 [SDNPCommutative, SDNPAssociative]>;
265 def addc : SDNode<"ISD::ADDC" , SDTIntBinOp,
266 [SDNPCommutative, SDNPOutFlag]>;
267 def adde : SDNode<"ISD::ADDE" , SDTIntBinOp,
268 [SDNPCommutative, SDNPOutFlag, SDNPInFlag]>;
269 def subc : SDNode<"ISD::SUBC" , SDTIntBinOp,
271 def sube : SDNode<"ISD::SUBE" , SDTIntBinOp,
272 [SDNPOutFlag, SDNPInFlag]>;
274 def sext_inreg : SDNode<"ISD::SIGN_EXTEND_INREG", SDTExtInreg>;
275 def bswap : SDNode<"ISD::BSWAP" , SDTIntUnaryOp>;
276 def ctlz : SDNode<"ISD::CTLZ" , SDTIntUnaryOp>;
277 def cttz : SDNode<"ISD::CTTZ" , SDTIntUnaryOp>;
278 def ctpop : SDNode<"ISD::CTPOP" , SDTIntUnaryOp>;
279 def sext : SDNode<"ISD::SIGN_EXTEND", SDTIntExtendOp>;
280 def zext : SDNode<"ISD::ZERO_EXTEND", SDTIntExtendOp>;
281 def anyext : SDNode<"ISD::ANY_EXTEND" , SDTIntExtendOp>;
282 def trunc : SDNode<"ISD::TRUNCATE" , SDTIntTruncOp>;
283 def bitconvert : SDNode<"ISD::BIT_CONVERT", SDTUnaryOp>;
285 def fadd : SDNode<"ISD::FADD" , SDTFPBinOp, [SDNPCommutative]>;
286 def fsub : SDNode<"ISD::FSUB" , SDTFPBinOp>;
287 def fmul : SDNode<"ISD::FMUL" , SDTFPBinOp, [SDNPCommutative]>;
288 def fdiv : SDNode<"ISD::FDIV" , SDTFPBinOp>;
289 def frem : SDNode<"ISD::FREM" , SDTFPBinOp>;
290 def fabs : SDNode<"ISD::FABS" , SDTFPUnaryOp>;
291 def fneg : SDNode<"ISD::FNEG" , SDTFPUnaryOp>;
292 def fsqrt : SDNode<"ISD::FSQRT" , SDTFPUnaryOp>;
293 def fsin : SDNode<"ISD::FSIN" , SDTFPUnaryOp>;
294 def fcos : SDNode<"ISD::FCOS" , SDTFPUnaryOp>;
296 def fround : SDNode<"ISD::FP_ROUND" , SDTFPRoundOp>;
297 def fextend : SDNode<"ISD::FP_EXTEND" , SDTFPExtendOp>;
298 def fcopysign : SDNode<"ISD::FCOPYSIGN" , SDTFPSignOp>;
300 def sint_to_fp : SDNode<"ISD::SINT_TO_FP" , SDTIntToFPOp>;
301 def uint_to_fp : SDNode<"ISD::UINT_TO_FP" , SDTIntToFPOp>;
302 def fp_to_sint : SDNode<"ISD::FP_TO_SINT" , SDTFPToIntOp>;
303 def fp_to_uint : SDNode<"ISD::FP_TO_UINT" , SDTFPToIntOp>;
305 def setcc : SDNode<"ISD::SETCC" , SDTSetCC>;
306 def select : SDNode<"ISD::SELECT" , SDTSelect>;
307 def selectcc : SDNode<"ISD::SELECT_CC" , SDTSelectCC>;
309 def brcond : SDNode<"ISD::BRCOND" , SDTBrcond, [SDNPHasChain]>;
310 def brind : SDNode<"ISD::BRIND" , SDTBrind, [SDNPHasChain]>;
311 def br : SDNode<"ISD::BR" , SDTBr, [SDNPHasChain]>;
312 def ret : SDNode<"ISD::RET" , SDTRet, [SDNPHasChain]>;
314 // Do not use ld, st directly. Use load, extload, sextload, zextload, store,
315 // and truncst (see below).
316 def ld : SDNode<"ISD::LOAD" , SDTLoad, [SDNPHasChain]>;
317 def st : SDNode<"ISD::STORE" , SDTStore,
318 [SDNPHasChain, SDNPMayStore]>;
319 def ist : SDNode<"ISD::STORE" , SDTIStore,
320 [SDNPHasChain, SDNPMayStore]>;
322 def vector_shuffle : SDNode<"ISD::VECTOR_SHUFFLE", SDTVecShuffle, []>;
323 def build_vector : SDNode<"ISD::BUILD_VECTOR", SDTypeProfile<1, 0, []>, []>;
324 def scalar_to_vector : SDNode<"ISD::SCALAR_TO_VECTOR", SDTypeProfile<1, 1, []>,
326 def vector_extract : SDNode<"ISD::EXTRACT_VECTOR_ELT",
327 SDTypeProfile<1, 2, [SDTCisPtrTy<2>]>, []>;
328 def vector_insert : SDNode<"ISD::INSERT_VECTOR_ELT",
329 SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisPtrTy<3>]>, []>;
331 def extract_subreg : SDNode<"ISD::EXTRACT_SUBREG",
332 SDTypeProfile<1, 2, []>>;
333 def insert_subreg : SDNode<"ISD::INSERT_SUBREG",
334 SDTypeProfile<1, 3, []>>;
336 // Nodes for intrinsics, you should use the intrinsic itself and let tblgen use
337 // these internally. Don't reference these directly.
338 def intrinsic_void : SDNode<"ISD::INTRINSIC_VOID",
339 SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>,
341 def intrinsic_w_chain : SDNode<"ISD::INTRINSIC_W_CHAIN",
342 SDTypeProfile<1, -1, [SDTCisPtrTy<1>]>,
344 def intrinsic_wo_chain : SDNode<"ISD::INTRINSIC_WO_CHAIN",
345 SDTypeProfile<1, -1, [SDTCisPtrTy<1>]>, []>;
348 //===----------------------------------------------------------------------===//
349 // Selection DAG Condition Codes
351 class CondCode; // ISD::CondCode enums
352 def SETOEQ : CondCode; def SETOGT : CondCode;
353 def SETOGE : CondCode; def SETOLT : CondCode; def SETOLE : CondCode;
354 def SETONE : CondCode; def SETO : CondCode; def SETUO : CondCode;
355 def SETUEQ : CondCode; def SETUGT : CondCode; def SETUGE : CondCode;
356 def SETULT : CondCode; def SETULE : CondCode; def SETUNE : CondCode;
358 def SETEQ : CondCode; def SETGT : CondCode; def SETGE : CondCode;
359 def SETLT : CondCode; def SETLE : CondCode; def SETNE : CondCode;
362 //===----------------------------------------------------------------------===//
363 // Selection DAG Node Transformation Functions.
365 // This mechanism allows targets to manipulate nodes in the output DAG once a
366 // match has been formed. This is typically used to manipulate immediate
369 class SDNodeXForm<SDNode opc, code xformFunction> {
371 code XFormFunction = xformFunction;
374 def NOOP_SDNodeXForm : SDNodeXForm<imm, [{}]>;
377 //===----------------------------------------------------------------------===//
378 // Selection DAG Pattern Fragments.
380 // Pattern fragments are reusable chunks of dags that match specific things.
381 // They can take arguments and have C++ predicates that control whether they
382 // match. They are intended to make the patterns for common instructions more
383 // compact and readable.
386 /// PatFrag - Represents a pattern fragment. This can match something on the
387 /// DAG, frame a single node to multiply nested other fragments.
389 class PatFrag<dag ops, dag frag, code pred = [{}],
390 SDNodeXForm xform = NOOP_SDNodeXForm> {
393 code Predicate = pred;
394 SDNodeXForm OperandTransform = xform;
397 // PatLeaf's are pattern fragments that have no operands. This is just a helper
398 // to define immediates and other common things concisely.
399 class PatLeaf<dag frag, code pred = [{}], SDNodeXForm xform = NOOP_SDNodeXForm>
400 : PatFrag<(ops), frag, pred, xform>;
404 def vtInt : PatLeaf<(vt), [{ return MVT::isInteger(N->getVT()); }]>;
405 def vtFP : PatLeaf<(vt), [{ return MVT::isFloatingPoint(N->getVT()); }]>;
407 def immAllOnes : PatLeaf<(imm), [{ return N->isAllOnesValue(); }]>;
408 def immAllOnesV: PatLeaf<(build_vector), [{
409 return ISD::isBuildVectorAllOnes(N);
411 def immAllOnesV_bc: PatLeaf<(bitconvert), [{
412 return ISD::isBuildVectorAllOnes(N);
414 def immAllZerosV: PatLeaf<(build_vector), [{
415 return ISD::isBuildVectorAllZeros(N);
417 def immAllZerosV_bc: PatLeaf<(bitconvert), [{
418 return ISD::isBuildVectorAllZeros(N);
423 // Other helper fragments.
424 def not : PatFrag<(ops node:$in), (xor node:$in, immAllOnes)>;
425 def vnot : PatFrag<(ops node:$in), (xor node:$in, immAllOnesV)>;
426 def vnot_conv : PatFrag<(ops node:$in), (xor node:$in, immAllOnesV_bc)>;
427 def ineg : PatFrag<(ops node:$in), (sub 0, node:$in)>;
430 def load : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
431 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
432 return LD->getExtensionType() == ISD::NON_EXTLOAD &&
433 LD->getAddressingMode() == ISD::UNINDEXED;
437 // extending load fragments.
438 def extloadi1 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
439 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
440 return LD->getExtensionType() == ISD::EXTLOAD &&
441 LD->getAddressingMode() == ISD::UNINDEXED &&
442 LD->getLoadedVT() == MVT::i1;
445 def extloadi8 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
446 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
447 return LD->getExtensionType() == ISD::EXTLOAD &&
448 LD->getAddressingMode() == ISD::UNINDEXED &&
449 LD->getLoadedVT() == MVT::i8;
452 def extloadi16 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
453 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
454 return LD->getExtensionType() == ISD::EXTLOAD &&
455 LD->getAddressingMode() == ISD::UNINDEXED &&
456 LD->getLoadedVT() == MVT::i16;
459 def extloadi32 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
460 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
461 return LD->getExtensionType() == ISD::EXTLOAD &&
462 LD->getAddressingMode() == ISD::UNINDEXED &&
463 LD->getLoadedVT() == MVT::i32;
466 def extloadf32 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
467 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
468 return LD->getExtensionType() == ISD::EXTLOAD &&
469 LD->getAddressingMode() == ISD::UNINDEXED &&
470 LD->getLoadedVT() == MVT::f32;
473 def extloadf64 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
474 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
475 return LD->getExtensionType() == ISD::EXTLOAD &&
476 LD->getAddressingMode() == ISD::UNINDEXED &&
477 LD->getLoadedVT() == MVT::f64;
481 def sextloadi1 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
482 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
483 return LD->getExtensionType() == ISD::SEXTLOAD &&
484 LD->getAddressingMode() == ISD::UNINDEXED &&
485 LD->getLoadedVT() == MVT::i1;
488 def sextloadi8 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
489 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
490 return LD->getExtensionType() == ISD::SEXTLOAD &&
491 LD->getAddressingMode() == ISD::UNINDEXED &&
492 LD->getLoadedVT() == MVT::i8;
495 def sextloadi16 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
496 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
497 return LD->getExtensionType() == ISD::SEXTLOAD &&
498 LD->getAddressingMode() == ISD::UNINDEXED &&
499 LD->getLoadedVT() == MVT::i16;
502 def sextloadi32 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
503 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
504 return LD->getExtensionType() == ISD::SEXTLOAD &&
505 LD->getAddressingMode() == ISD::UNINDEXED &&
506 LD->getLoadedVT() == MVT::i32;
510 def zextloadi1 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
511 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
512 return LD->getExtensionType() == ISD::ZEXTLOAD &&
513 LD->getAddressingMode() == ISD::UNINDEXED &&
514 LD->getLoadedVT() == MVT::i1;
517 def zextloadi8 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
518 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
519 return LD->getExtensionType() == ISD::ZEXTLOAD &&
520 LD->getAddressingMode() == ISD::UNINDEXED &&
521 LD->getLoadedVT() == MVT::i8;
524 def zextloadi16 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
525 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
526 return LD->getExtensionType() == ISD::ZEXTLOAD &&
527 LD->getAddressingMode() == ISD::UNINDEXED &&
528 LD->getLoadedVT() == MVT::i16;
531 def zextloadi32 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
532 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
533 return LD->getExtensionType() == ISD::ZEXTLOAD &&
534 LD->getAddressingMode() == ISD::UNINDEXED &&
535 LD->getLoadedVT() == MVT::i32;
540 def store : PatFrag<(ops node:$val, node:$ptr),
541 (st node:$val, node:$ptr), [{
542 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
543 return !ST->isTruncatingStore() &&
544 ST->getAddressingMode() == ISD::UNINDEXED;
548 // truncstore fragments.
549 def truncstorei1 : PatFrag<(ops node:$val, node:$ptr),
550 (st node:$val, node:$ptr), [{
551 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
552 return ST->isTruncatingStore() && ST->getStoredVT() == MVT::i1 &&
553 ST->getAddressingMode() == ISD::UNINDEXED;
556 def truncstorei8 : PatFrag<(ops node:$val, node:$ptr),
557 (st node:$val, node:$ptr), [{
558 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
559 return ST->isTruncatingStore() && ST->getStoredVT() == MVT::i8 &&
560 ST->getAddressingMode() == ISD::UNINDEXED;
563 def truncstorei16 : PatFrag<(ops node:$val, node:$ptr),
564 (st node:$val, node:$ptr), [{
565 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
566 return ST->isTruncatingStore() && ST->getStoredVT() == MVT::i16 &&
567 ST->getAddressingMode() == ISD::UNINDEXED;
570 def truncstorei32 : PatFrag<(ops node:$val, node:$ptr),
571 (st node:$val, node:$ptr), [{
572 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
573 return ST->isTruncatingStore() && ST->getStoredVT() == MVT::i32 &&
574 ST->getAddressingMode() == ISD::UNINDEXED;
577 def truncstoref32 : PatFrag<(ops node:$val, node:$ptr),
578 (st node:$val, node:$ptr), [{
579 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
580 return ST->isTruncatingStore() && ST->getStoredVT() == MVT::f32 &&
581 ST->getAddressingMode() == ISD::UNINDEXED;
584 def truncstoref64 : PatFrag<(ops node:$val, node:$ptr),
585 (st node:$val, node:$ptr), [{
586 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
587 return ST->isTruncatingStore() && ST->getStoredVT() == MVT::f64 &&
588 ST->getAddressingMode() == ISD::UNINDEXED;
592 // indexed store fragments.
593 def pre_store : PatFrag<(ops node:$val, node:$base, node:$offset),
594 (ist node:$val, node:$base, node:$offset), [{
595 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
596 ISD::MemIndexedMode AM = ST->getAddressingMode();
597 return (AM == ISD::PRE_INC || AM == ISD::PRE_DEC) &&
598 !ST->isTruncatingStore();
603 def pre_truncsti1 : PatFrag<(ops node:$val, node:$base, node:$offset),
604 (ist node:$val, node:$base, node:$offset), [{
605 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
606 ISD::MemIndexedMode AM = ST->getAddressingMode();
607 return (AM == ISD::PRE_INC || AM == ISD::PRE_DEC) &&
608 ST->isTruncatingStore() && ST->getStoredVT() == MVT::i1;
612 def pre_truncsti8 : PatFrag<(ops node:$val, node:$base, node:$offset),
613 (ist node:$val, node:$base, node:$offset), [{
614 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
615 ISD::MemIndexedMode AM = ST->getAddressingMode();
616 return (AM == ISD::PRE_INC || AM == ISD::PRE_DEC) &&
617 ST->isTruncatingStore() && ST->getStoredVT() == MVT::i8;
621 def pre_truncsti16 : PatFrag<(ops node:$val, node:$base, node:$offset),
622 (ist node:$val, node:$base, node:$offset), [{
623 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
624 ISD::MemIndexedMode AM = ST->getAddressingMode();
625 return (AM == ISD::PRE_INC || AM == ISD::PRE_DEC) &&
626 ST->isTruncatingStore() && ST->getStoredVT() == MVT::i16;
630 def pre_truncsti32 : PatFrag<(ops node:$val, node:$base, node:$offset),
631 (ist node:$val, node:$base, node:$offset), [{
632 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
633 ISD::MemIndexedMode AM = ST->getAddressingMode();
634 return (AM == ISD::PRE_INC || AM == ISD::PRE_DEC) &&
635 ST->isTruncatingStore() && ST->getStoredVT() == MVT::i32;
639 def pre_truncstf32 : PatFrag<(ops node:$val, node:$base, node:$offset),
640 (ist node:$val, node:$base, node:$offset), [{
641 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
642 ISD::MemIndexedMode AM = ST->getAddressingMode();
643 return (AM == ISD::PRE_INC || AM == ISD::PRE_DEC) &&
644 ST->isTruncatingStore() && ST->getStoredVT() == MVT::f32;
649 def post_store : PatFrag<(ops node:$val, node:$ptr, node:$offset),
650 (ist node:$val, node:$ptr, node:$offset), [{
651 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
652 ISD::MemIndexedMode AM = ST->getAddressingMode();
653 return !ST->isTruncatingStore() &&
654 (AM == ISD::POST_INC || AM == ISD::POST_DEC);
659 def post_truncsti1 : PatFrag<(ops node:$val, node:$base, node:$offset),
660 (ist node:$val, node:$base, node:$offset), [{
661 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
662 ISD::MemIndexedMode AM = ST->getAddressingMode();
663 return (AM == ISD::POST_INC || AM == ISD::POST_DEC) &&
664 ST->isTruncatingStore() && ST->getStoredVT() == MVT::i1;
668 def post_truncsti8 : PatFrag<(ops node:$val, node:$base, node:$offset),
669 (ist node:$val, node:$base, node:$offset), [{
670 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
671 ISD::MemIndexedMode AM = ST->getAddressingMode();
672 return (AM == ISD::POST_INC || AM == ISD::POST_DEC) &&
673 ST->isTruncatingStore() && ST->getStoredVT() == MVT::i8;
677 def post_truncsti16 : PatFrag<(ops node:$val, node:$base, node:$offset),
678 (ist node:$val, node:$base, node:$offset), [{
679 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
680 ISD::MemIndexedMode AM = ST->getAddressingMode();
681 return (AM == ISD::POST_INC || AM == ISD::POST_DEC) &&
682 ST->isTruncatingStore() && ST->getStoredVT() == MVT::i16;
686 def post_truncsti32 : PatFrag<(ops node:$val, node:$base, node:$offset),
687 (ist node:$val, node:$base, node:$offset), [{
688 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
689 ISD::MemIndexedMode AM = ST->getAddressingMode();
690 return (AM == ISD::POST_INC || AM == ISD::POST_DEC) &&
691 ST->isTruncatingStore() && ST->getStoredVT() == MVT::i32;
695 def post_truncstf32 : PatFrag<(ops node:$val, node:$base, node:$offset),
696 (ist node:$val, node:$base, node:$offset), [{
697 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
698 ISD::MemIndexedMode AM = ST->getAddressingMode();
699 return (AM == ISD::POST_INC || AM == ISD::POST_DEC) &&
700 ST->isTruncatingStore() && ST->getStoredVT() == MVT::f32;
705 // setcc convenience fragments.
706 def setoeq : PatFrag<(ops node:$lhs, node:$rhs),
707 (setcc node:$lhs, node:$rhs, SETOEQ)>;
708 def setogt : PatFrag<(ops node:$lhs, node:$rhs),
709 (setcc node:$lhs, node:$rhs, SETOGT)>;
710 def setoge : PatFrag<(ops node:$lhs, node:$rhs),
711 (setcc node:$lhs, node:$rhs, SETOGE)>;
712 def setolt : PatFrag<(ops node:$lhs, node:$rhs),
713 (setcc node:$lhs, node:$rhs, SETOLT)>;
714 def setole : PatFrag<(ops node:$lhs, node:$rhs),
715 (setcc node:$lhs, node:$rhs, SETOLE)>;
716 def setone : PatFrag<(ops node:$lhs, node:$rhs),
717 (setcc node:$lhs, node:$rhs, SETONE)>;
718 def seto : PatFrag<(ops node:$lhs, node:$rhs),
719 (setcc node:$lhs, node:$rhs, SETO)>;
720 def setuo : PatFrag<(ops node:$lhs, node:$rhs),
721 (setcc node:$lhs, node:$rhs, SETUO)>;
722 def setueq : PatFrag<(ops node:$lhs, node:$rhs),
723 (setcc node:$lhs, node:$rhs, SETUEQ)>;
724 def setugt : PatFrag<(ops node:$lhs, node:$rhs),
725 (setcc node:$lhs, node:$rhs, SETUGT)>;
726 def setuge : PatFrag<(ops node:$lhs, node:$rhs),
727 (setcc node:$lhs, node:$rhs, SETUGE)>;
728 def setult : PatFrag<(ops node:$lhs, node:$rhs),
729 (setcc node:$lhs, node:$rhs, SETULT)>;
730 def setule : PatFrag<(ops node:$lhs, node:$rhs),
731 (setcc node:$lhs, node:$rhs, SETULE)>;
732 def setune : PatFrag<(ops node:$lhs, node:$rhs),
733 (setcc node:$lhs, node:$rhs, SETUNE)>;
734 def seteq : PatFrag<(ops node:$lhs, node:$rhs),
735 (setcc node:$lhs, node:$rhs, SETEQ)>;
736 def setgt : PatFrag<(ops node:$lhs, node:$rhs),
737 (setcc node:$lhs, node:$rhs, SETGT)>;
738 def setge : PatFrag<(ops node:$lhs, node:$rhs),
739 (setcc node:$lhs, node:$rhs, SETGE)>;
740 def setlt : PatFrag<(ops node:$lhs, node:$rhs),
741 (setcc node:$lhs, node:$rhs, SETLT)>;
742 def setle : PatFrag<(ops node:$lhs, node:$rhs),
743 (setcc node:$lhs, node:$rhs, SETLE)>;
744 def setne : PatFrag<(ops node:$lhs, node:$rhs),
745 (setcc node:$lhs, node:$rhs, SETNE)>;
747 //===----------------------------------------------------------------------===//
748 // Selection DAG Pattern Support.
750 // Patterns are what are actually matched against the target-flavored
751 // instruction selection DAG. Instructions defined by the target implicitly
752 // define patterns in most cases, but patterns can also be explicitly added when
753 // an operation is defined by a sequence of instructions (e.g. loading a large
754 // immediate value on RISC targets that do not support immediates as large as
758 class Pattern<dag patternToMatch, list<dag> resultInstrs> {
759 dag PatternToMatch = patternToMatch;
760 list<dag> ResultInstrs = resultInstrs;
761 list<Predicate> Predicates = []; // See class Instruction in Target.td.
762 int AddedComplexity = 0; // See class Instruction in Target.td.
765 // Pat - A simple (but common) form of a pattern, which produces a simple result
766 // not needing a full list.
767 class Pat<dag pattern, dag result> : Pattern<pattern, [result]>;
769 //===----------------------------------------------------------------------===//
770 // Complex pattern definitions.
772 // Complex patterns, e.g. X86 addressing mode, requires pattern matching code
773 // in C++. NumOperands is the number of operands returned by the select function;
774 // SelectFunc is the name of the function used to pattern match the max. pattern;
775 // RootNodes are the list of possible root nodes of the sub-dags to match.
776 // e.g. X86 addressing mode - def addr : ComplexPattern<4, "SelectAddr", [add]>;
778 class ComplexPattern<ValueType ty, int numops, string fn,
779 list<SDNode> roots = [], list<SDNodeProperty> props = []> {
781 int NumOperands = numops;
782 string SelectFunc = fn;
783 list<SDNode> RootNodes = roots;
784 list<SDNodeProperty> Properties = props;
787 //===----------------------------------------------------------------------===//
790 def SDT_dwarf_loc : SDTypeProfile<0, 3,
791 [SDTCisInt<0>, SDTCisInt<1>, SDTCisInt<2>]>;
792 def dwarf_loc : SDNode<"ISD::DEBUG_LOC", SDT_dwarf_loc,[SDNPHasChain]>;