1 //===- TargetSelectionDAG.td - Common code for DAG isels ---*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the target-independent interfaces used by SelectionDAG
11 // instruction selection generators.
13 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
16 // Selection DAG Type Constraint definitions.
18 // Note that the semantics of these constraints are hard coded into tblgen. To
19 // modify or add constraints, you have to hack tblgen.
22 class SDTypeConstraint<int opnum> {
23 int OperandNum = opnum;
26 // SDTCisVT - The specified operand has exactly this VT.
27 class SDTCisVT<int OpNum, ValueType vt> : SDTypeConstraint<OpNum> {
31 class SDTCisPtrTy<int OpNum> : SDTypeConstraint<OpNum>;
33 // SDTCisInt - The specified operand is has integer type.
34 class SDTCisInt<int OpNum> : SDTypeConstraint<OpNum>;
36 // SDTCisFP - The specified operand is has floating point type.
37 class SDTCisFP<int OpNum> : SDTypeConstraint<OpNum>;
39 // SDTCisSameAs - The two specified operands have identical types.
40 class SDTCisSameAs<int OpNum, int OtherOp> : SDTypeConstraint<OpNum> {
41 int OtherOperandNum = OtherOp;
44 // SDTCisVTSmallerThanOp - The specified operand is a VT SDNode, and its type is
45 // smaller than the 'Other' operand.
46 class SDTCisVTSmallerThanOp<int OpNum, int OtherOp> : SDTypeConstraint<OpNum> {
47 int OtherOperandNum = OtherOp;
50 class SDTCisOpSmallerThanOp<int SmallOp, int BigOp> : SDTypeConstraint<SmallOp>{
51 int BigOperandNum = BigOp;
54 /// SDTCisIntVectorOfSameSize - This indicates that ThisOp and OtherOp are
55 /// vector types, and that ThisOp is the result of
56 /// MVT::getIntVectorWithNumElements with the number of elements that ThisOp
58 class SDTCisIntVectorOfSameSize<int ThisOp, int OtherOp>
59 : SDTypeConstraint<ThisOp> {
60 int OtherOpNum = OtherOp;
63 /// SDTCisEltOfVec - This indicates that ThisOp is a scalar type of the same
64 /// type as the element type of OtherOp, which is a vector type.
65 class SDTCisEltOfVec<int ThisOp, int OtherOp>
66 : SDTypeConstraint<ThisOp> {
67 int OtherOpNum = OtherOp;
70 //===----------------------------------------------------------------------===//
71 // Selection DAG Type Profile definitions.
73 // These use the constraints defined above to describe the type requirements of
74 // the various nodes. These are not hard coded into tblgen, allowing targets to
75 // add their own if needed.
78 // SDTypeProfile - This profile describes the type requirements of a Selection
80 class SDTypeProfile<int numresults, int numoperands,
81 list<SDTypeConstraint> constraints> {
82 int NumResults = numresults;
83 int NumOperands = numoperands;
84 list<SDTypeConstraint> Constraints = constraints;
88 def SDTIntLeaf: SDTypeProfile<1, 0, [SDTCisInt<0>]>; // for 'imm'.
89 def SDTFPLeaf : SDTypeProfile<1, 0, [SDTCisFP<0>]>; // for 'fpimm'.
90 def SDTPtrLeaf: SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>; // for '&g'.
91 def SDTOther : SDTypeProfile<1, 0, [SDTCisVT<0, OtherVT>]>; // for 'vt'.
92 def SDTUNDEF : SDTypeProfile<1, 0, []>; // for 'undef'.
93 def SDTUnaryOp : SDTypeProfile<1, 1, []>; // bitconvert
95 def SDTIntBinOp : SDTypeProfile<1, 2, [ // add, and, or, xor, udiv, etc.
96 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<0>
98 def SDTIntShiftOp : SDTypeProfile<1, 2, [ // shl, sra, srl
99 SDTCisSameAs<0, 1>, SDTCisInt<0>, SDTCisInt<2>
101 def SDTFPBinOp : SDTypeProfile<1, 2, [ // fadd, fmul, etc.
102 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisFP<0>
104 def SDTFPSignOp : SDTypeProfile<1, 2, [ // fcopysign.
105 SDTCisSameAs<0, 1>, SDTCisFP<0>, SDTCisFP<2>
107 def SDTFPTernaryOp : SDTypeProfile<1, 3, [ // fmadd, fnmsub, etc.
108 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>, SDTCisFP<0>
110 def SDTIntUnaryOp : SDTypeProfile<1, 1, [ // ctlz
111 SDTCisSameAs<0, 1>, SDTCisInt<0>
113 def SDTIntExtendOp : SDTypeProfile<1, 1, [ // sext, zext, anyext
114 SDTCisInt<0>, SDTCisInt<1>, SDTCisOpSmallerThanOp<1, 0>
116 def SDTIntTruncOp : SDTypeProfile<1, 1, [ // trunc
117 SDTCisInt<0>, SDTCisInt<1>, SDTCisOpSmallerThanOp<0, 1>
119 def SDTFPUnaryOp : SDTypeProfile<1, 1, [ // fneg, fsqrt, etc
120 SDTCisSameAs<0, 1>, SDTCisFP<0>
122 def SDTFPRoundOp : SDTypeProfile<1, 1, [ // fround
123 SDTCisFP<0>, SDTCisFP<1>, SDTCisOpSmallerThanOp<0, 1>
125 def SDTFPExtendOp : SDTypeProfile<1, 1, [ // fextend
126 SDTCisFP<0>, SDTCisFP<1>, SDTCisOpSmallerThanOp<1, 0>
128 def SDTIntToFPOp : SDTypeProfile<1, 1, [ // [su]int_to_fp
129 SDTCisFP<0>, SDTCisInt<1>
131 def SDTFPToIntOp : SDTypeProfile<1, 1, [ // fp_to_[su]int
132 SDTCisInt<0>, SDTCisFP<1>
134 def SDTExtInreg : SDTypeProfile<1, 2, [ // sext_inreg
135 SDTCisSameAs<0, 1>, SDTCisInt<0>, SDTCisVT<2, OtherVT>,
136 SDTCisVTSmallerThanOp<2, 1>
139 def SDTSetCC : SDTypeProfile<1, 3, [ // setcc
140 SDTCisInt<0>, SDTCisSameAs<1, 2>, SDTCisVT<3, OtherVT>
143 def SDTSelect : SDTypeProfile<1, 3, [ // select
144 SDTCisInt<1>, SDTCisSameAs<0, 2>, SDTCisSameAs<2, 3>
147 def SDTSelectCC : SDTypeProfile<1, 5, [ // select_cc
148 SDTCisSameAs<1, 2>, SDTCisSameAs<3, 4>, SDTCisSameAs<0, 3>,
152 def SDTBr : SDTypeProfile<0, 1, [ // br
156 def SDTBrcond : SDTypeProfile<0, 2, [ // brcond
157 SDTCisInt<0>, SDTCisVT<1, OtherVT>
160 def SDTBrind : SDTypeProfile<0, 1, [ // brind
164 def SDTNone : SDTypeProfile<0, 0, []>; // ret, trap
166 def SDTLoad : SDTypeProfile<1, 1, [ // load
170 def SDTStore : SDTypeProfile<0, 2, [ // store
174 def SDTIStore : SDTypeProfile<1, 3, [ // indexed store
175 SDTCisSameAs<0, 2>, SDTCisPtrTy<0>, SDTCisPtrTy<3>
178 def SDTVecShuffle : SDTypeProfile<1, 3, [
179 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisIntVectorOfSameSize<3, 0>
181 def SDTVecExtract : SDTypeProfile<1, 2, [ // vector extract
182 SDTCisEltOfVec<0, 1>, SDTCisPtrTy<2>
184 def SDTVecInsert : SDTypeProfile<1, 3, [ // vector insert
185 SDTCisEltOfVec<2, 1>, SDTCisSameAs<0, 1>, SDTCisPtrTy<3>
188 class SDCallSeqStart<list<SDTypeConstraint> constraints> :
189 SDTypeProfile<0, 1, constraints>;
190 class SDCallSeqEnd<list<SDTypeConstraint> constraints> :
191 SDTypeProfile<0, 2, constraints>;
193 //===----------------------------------------------------------------------===//
194 // Selection DAG Node Properties.
196 // Note: These are hard coded into tblgen.
198 class SDNodeProperty;
199 def SDNPCommutative : SDNodeProperty; // X op Y == Y op X
200 def SDNPAssociative : SDNodeProperty; // (X op Y) op Z == X op (Y op Z)
201 def SDNPHasChain : SDNodeProperty; // R/W chain operand and result
202 def SDNPOutFlag : SDNodeProperty; // Write a flag result
203 def SDNPInFlag : SDNodeProperty; // Read a flag operand
204 def SDNPOptInFlag : SDNodeProperty; // Optionally read a flag operand
205 def SDNPMayStore : SDNodeProperty; // May write to memory, sets 'mayStore'.
206 def SDNPMayLoad : SDNodeProperty; // May read memory, sets 'mayLoad'.
207 def SDNPSideEffect : SDNodeProperty; // Sets 'HasUnmodelledSideEffects'.
209 //===----------------------------------------------------------------------===//
210 // Selection DAG Node definitions.
212 class SDNode<string opcode, SDTypeProfile typeprof,
213 list<SDNodeProperty> props = [], string sdclass = "SDNode"> {
214 string Opcode = opcode;
215 string SDClass = sdclass;
216 list<SDNodeProperty> Properties = props;
217 SDTypeProfile TypeProfile = typeprof;
226 def imm : SDNode<"ISD::Constant" , SDTIntLeaf , [], "ConstantSDNode">;
227 def fpimm : SDNode<"ISD::ConstantFP", SDTFPLeaf , [], "ConstantFPSDNode">;
228 def vt : SDNode<"ISD::VALUETYPE" , SDTOther , [], "VTSDNode">;
229 def bb : SDNode<"ISD::BasicBlock", SDTOther , [], "BasicBlockSDNode">;
230 def cond : SDNode<"ISD::CONDCODE" , SDTOther , [], "CondCodeSDNode">;
231 def undef : SDNode<"ISD::UNDEF" , SDTUNDEF , []>;
232 def globaladdr : SDNode<"ISD::GlobalAddress", SDTPtrLeaf, [],
233 "GlobalAddressSDNode">;
234 def tglobaladdr : SDNode<"ISD::TargetGlobalAddress", SDTPtrLeaf, [],
235 "GlobalAddressSDNode">;
236 def globaltlsaddr : SDNode<"ISD::GlobalTLSAddress", SDTPtrLeaf, [],
237 "GlobalAddressSDNode">;
238 def tglobaltlsaddr : SDNode<"ISD::TargetGlobalTLSAddress", SDTPtrLeaf, [],
239 "GlobalAddressSDNode">;
240 def constpool : SDNode<"ISD::ConstantPool", SDTPtrLeaf, [],
241 "ConstantPoolSDNode">;
242 def tconstpool : SDNode<"ISD::TargetConstantPool", SDTPtrLeaf, [],
243 "ConstantPoolSDNode">;
244 def jumptable : SDNode<"ISD::JumpTable", SDTPtrLeaf, [],
246 def tjumptable : SDNode<"ISD::TargetJumpTable", SDTPtrLeaf, [],
248 def frameindex : SDNode<"ISD::FrameIndex", SDTPtrLeaf, [],
250 def tframeindex : SDNode<"ISD::TargetFrameIndex", SDTPtrLeaf, [],
252 def externalsym : SDNode<"ISD::ExternalSymbol", SDTPtrLeaf, [],
253 "ExternalSymbolSDNode">;
254 def texternalsym: SDNode<"ISD::TargetExternalSymbol", SDTPtrLeaf, [],
255 "ExternalSymbolSDNode">;
257 def add : SDNode<"ISD::ADD" , SDTIntBinOp ,
258 [SDNPCommutative, SDNPAssociative]>;
259 def sub : SDNode<"ISD::SUB" , SDTIntBinOp>;
260 def mul : SDNode<"ISD::MUL" , SDTIntBinOp,
261 [SDNPCommutative, SDNPAssociative]>;
262 def mulhs : SDNode<"ISD::MULHS" , SDTIntBinOp, [SDNPCommutative]>;
263 def mulhu : SDNode<"ISD::MULHU" , SDTIntBinOp, [SDNPCommutative]>;
264 def sdiv : SDNode<"ISD::SDIV" , SDTIntBinOp>;
265 def udiv : SDNode<"ISD::UDIV" , SDTIntBinOp>;
266 def srem : SDNode<"ISD::SREM" , SDTIntBinOp>;
267 def urem : SDNode<"ISD::UREM" , SDTIntBinOp>;
268 def srl : SDNode<"ISD::SRL" , SDTIntShiftOp>;
269 def sra : SDNode<"ISD::SRA" , SDTIntShiftOp>;
270 def shl : SDNode<"ISD::SHL" , SDTIntShiftOp>;
271 def rotl : SDNode<"ISD::ROTL" , SDTIntShiftOp>;
272 def rotr : SDNode<"ISD::ROTR" , SDTIntShiftOp>;
273 def and : SDNode<"ISD::AND" , SDTIntBinOp,
274 [SDNPCommutative, SDNPAssociative]>;
275 def or : SDNode<"ISD::OR" , SDTIntBinOp,
276 [SDNPCommutative, SDNPAssociative]>;
277 def xor : SDNode<"ISD::XOR" , SDTIntBinOp,
278 [SDNPCommutative, SDNPAssociative]>;
279 def addc : SDNode<"ISD::ADDC" , SDTIntBinOp,
280 [SDNPCommutative, SDNPOutFlag]>;
281 def adde : SDNode<"ISD::ADDE" , SDTIntBinOp,
282 [SDNPCommutative, SDNPOutFlag, SDNPInFlag]>;
283 def subc : SDNode<"ISD::SUBC" , SDTIntBinOp,
285 def sube : SDNode<"ISD::SUBE" , SDTIntBinOp,
286 [SDNPOutFlag, SDNPInFlag]>;
288 def sext_inreg : SDNode<"ISD::SIGN_EXTEND_INREG", SDTExtInreg>;
289 def bswap : SDNode<"ISD::BSWAP" , SDTIntUnaryOp>;
290 def ctlz : SDNode<"ISD::CTLZ" , SDTIntUnaryOp>;
291 def cttz : SDNode<"ISD::CTTZ" , SDTIntUnaryOp>;
292 def ctpop : SDNode<"ISD::CTPOP" , SDTIntUnaryOp>;
293 def sext : SDNode<"ISD::SIGN_EXTEND", SDTIntExtendOp>;
294 def zext : SDNode<"ISD::ZERO_EXTEND", SDTIntExtendOp>;
295 def anyext : SDNode<"ISD::ANY_EXTEND" , SDTIntExtendOp>;
296 def trunc : SDNode<"ISD::TRUNCATE" , SDTIntTruncOp>;
297 def bitconvert : SDNode<"ISD::BIT_CONVERT", SDTUnaryOp>;
298 def extractelt : SDNode<"ISD::EXTRACT_VECTOR_ELT", SDTVecExtract>;
299 def insertelt : SDNode<"ISD::INSERT_VECTOR_ELT", SDTVecInsert>;
302 def fadd : SDNode<"ISD::FADD" , SDTFPBinOp, [SDNPCommutative]>;
303 def fsub : SDNode<"ISD::FSUB" , SDTFPBinOp>;
304 def fmul : SDNode<"ISD::FMUL" , SDTFPBinOp, [SDNPCommutative]>;
305 def fdiv : SDNode<"ISD::FDIV" , SDTFPBinOp>;
306 def frem : SDNode<"ISD::FREM" , SDTFPBinOp>;
307 def fabs : SDNode<"ISD::FABS" , SDTFPUnaryOp>;
308 def fneg : SDNode<"ISD::FNEG" , SDTFPUnaryOp>;
309 def fsqrt : SDNode<"ISD::FSQRT" , SDTFPUnaryOp>;
310 def fsin : SDNode<"ISD::FSIN" , SDTFPUnaryOp>;
311 def fcos : SDNode<"ISD::FCOS" , SDTFPUnaryOp>;
313 def fround : SDNode<"ISD::FP_ROUND" , SDTFPRoundOp>;
314 def fextend : SDNode<"ISD::FP_EXTEND" , SDTFPExtendOp>;
315 def fcopysign : SDNode<"ISD::FCOPYSIGN" , SDTFPSignOp>;
317 def sint_to_fp : SDNode<"ISD::SINT_TO_FP" , SDTIntToFPOp>;
318 def uint_to_fp : SDNode<"ISD::UINT_TO_FP" , SDTIntToFPOp>;
319 def fp_to_sint : SDNode<"ISD::FP_TO_SINT" , SDTFPToIntOp>;
320 def fp_to_uint : SDNode<"ISD::FP_TO_UINT" , SDTFPToIntOp>;
322 def setcc : SDNode<"ISD::SETCC" , SDTSetCC>;
323 def select : SDNode<"ISD::SELECT" , SDTSelect>;
324 def selectcc : SDNode<"ISD::SELECT_CC" , SDTSelectCC>;
326 def brcond : SDNode<"ISD::BRCOND" , SDTBrcond, [SDNPHasChain]>;
327 def brind : SDNode<"ISD::BRIND" , SDTBrind, [SDNPHasChain]>;
328 def br : SDNode<"ISD::BR" , SDTBr, [SDNPHasChain]>;
329 def ret : SDNode<"ISD::RET" , SDTNone, [SDNPHasChain]>;
330 def trap : SDNode<"ISD::TRAP" , SDTNone,
331 [SDNPHasChain, SDNPSideEffect]>;
333 // Do not use ld, st directly. Use load, extload, sextload, zextload, store,
334 // and truncst (see below).
335 def ld : SDNode<"ISD::LOAD" , SDTLoad,
336 [SDNPHasChain, SDNPMayLoad]>;
337 def st : SDNode<"ISD::STORE" , SDTStore,
338 [SDNPHasChain, SDNPMayStore]>;
339 def ist : SDNode<"ISD::STORE" , SDTIStore,
340 [SDNPHasChain, SDNPMayStore]>;
342 def vector_shuffle : SDNode<"ISD::VECTOR_SHUFFLE", SDTVecShuffle, []>;
343 def build_vector : SDNode<"ISD::BUILD_VECTOR", SDTypeProfile<1, 0, []>, []>;
344 def scalar_to_vector : SDNode<"ISD::SCALAR_TO_VECTOR", SDTypeProfile<1, 1, []>,
346 def vector_extract : SDNode<"ISD::EXTRACT_VECTOR_ELT",
347 SDTypeProfile<1, 2, [SDTCisPtrTy<2>]>, []>;
348 def vector_insert : SDNode<"ISD::INSERT_VECTOR_ELT",
349 SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisPtrTy<3>]>, []>;
351 def extract_subreg : SDNode<"ISD::EXTRACT_SUBREG",
352 SDTypeProfile<1, 2, []>>;
353 def insert_subreg : SDNode<"ISD::INSERT_SUBREG",
354 SDTypeProfile<1, 3, []>>;
356 // Nodes for intrinsics, you should use the intrinsic itself and let tblgen use
357 // these internally. Don't reference these directly.
358 def intrinsic_void : SDNode<"ISD::INTRINSIC_VOID",
359 SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>,
361 def intrinsic_w_chain : SDNode<"ISD::INTRINSIC_W_CHAIN",
362 SDTypeProfile<1, -1, [SDTCisPtrTy<1>]>,
364 def intrinsic_wo_chain : SDNode<"ISD::INTRINSIC_WO_CHAIN",
365 SDTypeProfile<1, -1, [SDTCisPtrTy<1>]>, []>;
368 //===----------------------------------------------------------------------===//
369 // Selection DAG Condition Codes
371 class CondCode; // ISD::CondCode enums
372 def SETOEQ : CondCode; def SETOGT : CondCode;
373 def SETOGE : CondCode; def SETOLT : CondCode; def SETOLE : CondCode;
374 def SETONE : CondCode; def SETO : CondCode; def SETUO : CondCode;
375 def SETUEQ : CondCode; def SETUGT : CondCode; def SETUGE : CondCode;
376 def SETULT : CondCode; def SETULE : CondCode; def SETUNE : CondCode;
378 def SETEQ : CondCode; def SETGT : CondCode; def SETGE : CondCode;
379 def SETLT : CondCode; def SETLE : CondCode; def SETNE : CondCode;
382 //===----------------------------------------------------------------------===//
383 // Selection DAG Node Transformation Functions.
385 // This mechanism allows targets to manipulate nodes in the output DAG once a
386 // match has been formed. This is typically used to manipulate immediate
389 class SDNodeXForm<SDNode opc, code xformFunction> {
391 code XFormFunction = xformFunction;
394 def NOOP_SDNodeXForm : SDNodeXForm<imm, [{}]>;
397 //===----------------------------------------------------------------------===//
398 // Selection DAG Pattern Fragments.
400 // Pattern fragments are reusable chunks of dags that match specific things.
401 // They can take arguments and have C++ predicates that control whether they
402 // match. They are intended to make the patterns for common instructions more
403 // compact and readable.
406 /// PatFrag - Represents a pattern fragment. This can match something on the
407 /// DAG, frame a single node to multiply nested other fragments.
409 class PatFrag<dag ops, dag frag, code pred = [{}],
410 SDNodeXForm xform = NOOP_SDNodeXForm> {
413 code Predicate = pred;
414 SDNodeXForm OperandTransform = xform;
417 // PatLeaf's are pattern fragments that have no operands. This is just a helper
418 // to define immediates and other common things concisely.
419 class PatLeaf<dag frag, code pred = [{}], SDNodeXForm xform = NOOP_SDNodeXForm>
420 : PatFrag<(ops), frag, pred, xform>;
424 def vtInt : PatLeaf<(vt), [{ return MVT::isInteger(N->getVT()); }]>;
425 def vtFP : PatLeaf<(vt), [{ return MVT::isFloatingPoint(N->getVT()); }]>;
427 def immAllOnes : PatLeaf<(imm), [{ return N->isAllOnesValue(); }]>;
428 def immAllOnesV: PatLeaf<(build_vector), [{
429 return ISD::isBuildVectorAllOnes(N);
431 def immAllOnesV_bc: PatLeaf<(bitconvert), [{
432 return ISD::isBuildVectorAllOnes(N);
434 def immAllZerosV: PatLeaf<(build_vector), [{
435 return ISD::isBuildVectorAllZeros(N);
437 def immAllZerosV_bc: PatLeaf<(bitconvert), [{
438 return ISD::isBuildVectorAllZeros(N);
443 // Other helper fragments.
444 def not : PatFrag<(ops node:$in), (xor node:$in, immAllOnes)>;
445 def vnot : PatFrag<(ops node:$in), (xor node:$in, immAllOnesV)>;
446 def vnot_conv : PatFrag<(ops node:$in), (xor node:$in, immAllOnesV_bc)>;
447 def ineg : PatFrag<(ops node:$in), (sub 0, node:$in)>;
450 def load : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
451 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
452 return LD->getExtensionType() == ISD::NON_EXTLOAD &&
453 LD->getAddressingMode() == ISD::UNINDEXED;
457 // extending load fragments.
458 def extloadi1 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
459 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
460 return LD->getExtensionType() == ISD::EXTLOAD &&
461 LD->getAddressingMode() == ISD::UNINDEXED &&
462 LD->getMemoryVT() == MVT::i1;
465 def extloadi8 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
466 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
467 return LD->getExtensionType() == ISD::EXTLOAD &&
468 LD->getAddressingMode() == ISD::UNINDEXED &&
469 LD->getMemoryVT() == MVT::i8;
472 def extloadi16 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
473 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
474 return LD->getExtensionType() == ISD::EXTLOAD &&
475 LD->getAddressingMode() == ISD::UNINDEXED &&
476 LD->getMemoryVT() == MVT::i16;
479 def extloadi32 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
480 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
481 return LD->getExtensionType() == ISD::EXTLOAD &&
482 LD->getAddressingMode() == ISD::UNINDEXED &&
483 LD->getMemoryVT() == MVT::i32;
486 def extloadf32 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
487 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
488 return LD->getExtensionType() == ISD::EXTLOAD &&
489 LD->getAddressingMode() == ISD::UNINDEXED &&
490 LD->getMemoryVT() == MVT::f32;
493 def extloadf64 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
494 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
495 return LD->getExtensionType() == ISD::EXTLOAD &&
496 LD->getAddressingMode() == ISD::UNINDEXED &&
497 LD->getMemoryVT() == MVT::f64;
501 def sextloadi1 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
502 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
503 return LD->getExtensionType() == ISD::SEXTLOAD &&
504 LD->getAddressingMode() == ISD::UNINDEXED &&
505 LD->getMemoryVT() == MVT::i1;
508 def sextloadi8 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
509 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
510 return LD->getExtensionType() == ISD::SEXTLOAD &&
511 LD->getAddressingMode() == ISD::UNINDEXED &&
512 LD->getMemoryVT() == MVT::i8;
515 def sextloadi16 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
516 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
517 return LD->getExtensionType() == ISD::SEXTLOAD &&
518 LD->getAddressingMode() == ISD::UNINDEXED &&
519 LD->getMemoryVT() == MVT::i16;
522 def sextloadi32 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
523 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
524 return LD->getExtensionType() == ISD::SEXTLOAD &&
525 LD->getAddressingMode() == ISD::UNINDEXED &&
526 LD->getMemoryVT() == MVT::i32;
530 def zextloadi1 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
531 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
532 return LD->getExtensionType() == ISD::ZEXTLOAD &&
533 LD->getAddressingMode() == ISD::UNINDEXED &&
534 LD->getMemoryVT() == MVT::i1;
537 def zextloadi8 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
538 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
539 return LD->getExtensionType() == ISD::ZEXTLOAD &&
540 LD->getAddressingMode() == ISD::UNINDEXED &&
541 LD->getMemoryVT() == MVT::i8;
544 def zextloadi16 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
545 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
546 return LD->getExtensionType() == ISD::ZEXTLOAD &&
547 LD->getAddressingMode() == ISD::UNINDEXED &&
548 LD->getMemoryVT() == MVT::i16;
551 def zextloadi32 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
552 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
553 return LD->getExtensionType() == ISD::ZEXTLOAD &&
554 LD->getAddressingMode() == ISD::UNINDEXED &&
555 LD->getMemoryVT() == MVT::i32;
560 def store : PatFrag<(ops node:$val, node:$ptr),
561 (st node:$val, node:$ptr), [{
562 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
563 return !ST->isTruncatingStore() &&
564 ST->getAddressingMode() == ISD::UNINDEXED;
568 // truncstore fragments.
569 def truncstorei8 : PatFrag<(ops node:$val, node:$ptr),
570 (st node:$val, node:$ptr), [{
571 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
572 return ST->isTruncatingStore() && ST->getMemoryVT() == MVT::i8 &&
573 ST->getAddressingMode() == ISD::UNINDEXED;
576 def truncstorei16 : PatFrag<(ops node:$val, node:$ptr),
577 (st node:$val, node:$ptr), [{
578 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
579 return ST->isTruncatingStore() && ST->getMemoryVT() == MVT::i16 &&
580 ST->getAddressingMode() == ISD::UNINDEXED;
583 def truncstorei32 : PatFrag<(ops node:$val, node:$ptr),
584 (st node:$val, node:$ptr), [{
585 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
586 return ST->isTruncatingStore() && ST->getMemoryVT() == MVT::i32 &&
587 ST->getAddressingMode() == ISD::UNINDEXED;
590 def truncstoref32 : PatFrag<(ops node:$val, node:$ptr),
591 (st node:$val, node:$ptr), [{
592 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
593 return ST->isTruncatingStore() && ST->getMemoryVT() == MVT::f32 &&
594 ST->getAddressingMode() == ISD::UNINDEXED;
597 def truncstoref64 : PatFrag<(ops node:$val, node:$ptr),
598 (st node:$val, node:$ptr), [{
599 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
600 return ST->isTruncatingStore() && ST->getMemoryVT() == MVT::f64 &&
601 ST->getAddressingMode() == ISD::UNINDEXED;
605 // indexed store fragments.
606 def pre_store : PatFrag<(ops node:$val, node:$base, node:$offset),
607 (ist node:$val, node:$base, node:$offset), [{
608 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
609 ISD::MemIndexedMode AM = ST->getAddressingMode();
610 return (AM == ISD::PRE_INC || AM == ISD::PRE_DEC) &&
611 !ST->isTruncatingStore();
616 def pre_truncsti1 : PatFrag<(ops node:$val, node:$base, node:$offset),
617 (ist node:$val, node:$base, node:$offset), [{
618 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
619 ISD::MemIndexedMode AM = ST->getAddressingMode();
620 return (AM == ISD::PRE_INC || AM == ISD::PRE_DEC) &&
621 ST->isTruncatingStore() && ST->getMemoryVT() == MVT::i1;
625 def pre_truncsti8 : PatFrag<(ops node:$val, node:$base, node:$offset),
626 (ist node:$val, node:$base, node:$offset), [{
627 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
628 ISD::MemIndexedMode AM = ST->getAddressingMode();
629 return (AM == ISD::PRE_INC || AM == ISD::PRE_DEC) &&
630 ST->isTruncatingStore() && ST->getMemoryVT() == MVT::i8;
634 def pre_truncsti16 : PatFrag<(ops node:$val, node:$base, node:$offset),
635 (ist node:$val, node:$base, node:$offset), [{
636 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
637 ISD::MemIndexedMode AM = ST->getAddressingMode();
638 return (AM == ISD::PRE_INC || AM == ISD::PRE_DEC) &&
639 ST->isTruncatingStore() && ST->getMemoryVT() == MVT::i16;
643 def pre_truncsti32 : PatFrag<(ops node:$val, node:$base, node:$offset),
644 (ist node:$val, node:$base, node:$offset), [{
645 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
646 ISD::MemIndexedMode AM = ST->getAddressingMode();
647 return (AM == ISD::PRE_INC || AM == ISD::PRE_DEC) &&
648 ST->isTruncatingStore() && ST->getMemoryVT() == MVT::i32;
652 def pre_truncstf32 : PatFrag<(ops node:$val, node:$base, node:$offset),
653 (ist node:$val, node:$base, node:$offset), [{
654 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
655 ISD::MemIndexedMode AM = ST->getAddressingMode();
656 return (AM == ISD::PRE_INC || AM == ISD::PRE_DEC) &&
657 ST->isTruncatingStore() && ST->getMemoryVT() == MVT::f32;
662 def post_store : PatFrag<(ops node:$val, node:$ptr, node:$offset),
663 (ist node:$val, node:$ptr, node:$offset), [{
664 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
665 ISD::MemIndexedMode AM = ST->getAddressingMode();
666 return !ST->isTruncatingStore() &&
667 (AM == ISD::POST_INC || AM == ISD::POST_DEC);
672 def post_truncsti1 : PatFrag<(ops node:$val, node:$base, node:$offset),
673 (ist node:$val, node:$base, node:$offset), [{
674 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
675 ISD::MemIndexedMode AM = ST->getAddressingMode();
676 return (AM == ISD::POST_INC || AM == ISD::POST_DEC) &&
677 ST->isTruncatingStore() && ST->getMemoryVT() == MVT::i1;
681 def post_truncsti8 : PatFrag<(ops node:$val, node:$base, node:$offset),
682 (ist node:$val, node:$base, node:$offset), [{
683 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
684 ISD::MemIndexedMode AM = ST->getAddressingMode();
685 return (AM == ISD::POST_INC || AM == ISD::POST_DEC) &&
686 ST->isTruncatingStore() && ST->getMemoryVT() == MVT::i8;
690 def post_truncsti16 : PatFrag<(ops node:$val, node:$base, node:$offset),
691 (ist node:$val, node:$base, node:$offset), [{
692 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
693 ISD::MemIndexedMode AM = ST->getAddressingMode();
694 return (AM == ISD::POST_INC || AM == ISD::POST_DEC) &&
695 ST->isTruncatingStore() && ST->getMemoryVT() == MVT::i16;
699 def post_truncsti32 : PatFrag<(ops node:$val, node:$base, node:$offset),
700 (ist node:$val, node:$base, node:$offset), [{
701 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
702 ISD::MemIndexedMode AM = ST->getAddressingMode();
703 return (AM == ISD::POST_INC || AM == ISD::POST_DEC) &&
704 ST->isTruncatingStore() && ST->getMemoryVT() == MVT::i32;
708 def post_truncstf32 : PatFrag<(ops node:$val, node:$base, node:$offset),
709 (ist node:$val, node:$base, node:$offset), [{
710 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
711 ISD::MemIndexedMode AM = ST->getAddressingMode();
712 return (AM == ISD::POST_INC || AM == ISD::POST_DEC) &&
713 ST->isTruncatingStore() && ST->getMemoryVT() == MVT::f32;
718 // setcc convenience fragments.
719 def setoeq : PatFrag<(ops node:$lhs, node:$rhs),
720 (setcc node:$lhs, node:$rhs, SETOEQ)>;
721 def setogt : PatFrag<(ops node:$lhs, node:$rhs),
722 (setcc node:$lhs, node:$rhs, SETOGT)>;
723 def setoge : PatFrag<(ops node:$lhs, node:$rhs),
724 (setcc node:$lhs, node:$rhs, SETOGE)>;
725 def setolt : PatFrag<(ops node:$lhs, node:$rhs),
726 (setcc node:$lhs, node:$rhs, SETOLT)>;
727 def setole : PatFrag<(ops node:$lhs, node:$rhs),
728 (setcc node:$lhs, node:$rhs, SETOLE)>;
729 def setone : PatFrag<(ops node:$lhs, node:$rhs),
730 (setcc node:$lhs, node:$rhs, SETONE)>;
731 def seto : PatFrag<(ops node:$lhs, node:$rhs),
732 (setcc node:$lhs, node:$rhs, SETO)>;
733 def setuo : PatFrag<(ops node:$lhs, node:$rhs),
734 (setcc node:$lhs, node:$rhs, SETUO)>;
735 def setueq : PatFrag<(ops node:$lhs, node:$rhs),
736 (setcc node:$lhs, node:$rhs, SETUEQ)>;
737 def setugt : PatFrag<(ops node:$lhs, node:$rhs),
738 (setcc node:$lhs, node:$rhs, SETUGT)>;
739 def setuge : PatFrag<(ops node:$lhs, node:$rhs),
740 (setcc node:$lhs, node:$rhs, SETUGE)>;
741 def setult : PatFrag<(ops node:$lhs, node:$rhs),
742 (setcc node:$lhs, node:$rhs, SETULT)>;
743 def setule : PatFrag<(ops node:$lhs, node:$rhs),
744 (setcc node:$lhs, node:$rhs, SETULE)>;
745 def setune : PatFrag<(ops node:$lhs, node:$rhs),
746 (setcc node:$lhs, node:$rhs, SETUNE)>;
747 def seteq : PatFrag<(ops node:$lhs, node:$rhs),
748 (setcc node:$lhs, node:$rhs, SETEQ)>;
749 def setgt : PatFrag<(ops node:$lhs, node:$rhs),
750 (setcc node:$lhs, node:$rhs, SETGT)>;
751 def setge : PatFrag<(ops node:$lhs, node:$rhs),
752 (setcc node:$lhs, node:$rhs, SETGE)>;
753 def setlt : PatFrag<(ops node:$lhs, node:$rhs),
754 (setcc node:$lhs, node:$rhs, SETLT)>;
755 def setle : PatFrag<(ops node:$lhs, node:$rhs),
756 (setcc node:$lhs, node:$rhs, SETLE)>;
757 def setne : PatFrag<(ops node:$lhs, node:$rhs),
758 (setcc node:$lhs, node:$rhs, SETNE)>;
760 //===----------------------------------------------------------------------===//
761 // Selection DAG Pattern Support.
763 // Patterns are what are actually matched against the target-flavored
764 // instruction selection DAG. Instructions defined by the target implicitly
765 // define patterns in most cases, but patterns can also be explicitly added when
766 // an operation is defined by a sequence of instructions (e.g. loading a large
767 // immediate value on RISC targets that do not support immediates as large as
771 class Pattern<dag patternToMatch, list<dag> resultInstrs> {
772 dag PatternToMatch = patternToMatch;
773 list<dag> ResultInstrs = resultInstrs;
774 list<Predicate> Predicates = []; // See class Instruction in Target.td.
775 int AddedComplexity = 0; // See class Instruction in Target.td.
778 // Pat - A simple (but common) form of a pattern, which produces a simple result
779 // not needing a full list.
780 class Pat<dag pattern, dag result> : Pattern<pattern, [result]>;
782 //===----------------------------------------------------------------------===//
783 // Complex pattern definitions.
787 // Pass the parent Operand as root to CP function rather
788 // than the root of the sub-DAG
789 def CPAttrParentAsRoot : CPAttribute;
791 // Complex patterns, e.g. X86 addressing mode, requires pattern matching code
792 // in C++. NumOperands is the number of operands returned by the select function;
793 // SelectFunc is the name of the function used to pattern match the max. pattern;
794 // RootNodes are the list of possible root nodes of the sub-dags to match.
795 // e.g. X86 addressing mode - def addr : ComplexPattern<4, "SelectAddr", [add]>;
797 class ComplexPattern<ValueType ty, int numops, string fn,
798 list<SDNode> roots = [], list<SDNodeProperty> props = [],
799 list<CPAttribute> attrs = []> {
801 int NumOperands = numops;
802 string SelectFunc = fn;
803 list<SDNode> RootNodes = roots;
804 list<SDNodeProperty> Properties = props;
805 list<CPAttribute> Attributes = attrs;
808 //===----------------------------------------------------------------------===//
811 def SDT_dwarf_loc : SDTypeProfile<0, 3,
812 [SDTCisInt<0>, SDTCisInt<1>, SDTCisInt<2>]>;
813 def dwarf_loc : SDNode<"ISD::DEBUG_LOC", SDT_dwarf_loc,[SDNPHasChain]>;