1 //===- TargetSelectionDAG.td - Common code for DAG isels ---*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the target-independent interfaces used by SelectionDAG
11 // instruction selection generators.
13 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
16 // Selection DAG Type Constraint definitions.
18 // Note that the semantics of these constraints are hard coded into tblgen. To
19 // modify or add constraints, you have to hack tblgen.
22 class SDTypeConstraint<int opnum> {
23 int OperandNum = opnum;
26 // SDTCisVT - The specified operand has exactly this VT.
27 class SDTCisVT<int OpNum, ValueType vt> : SDTypeConstraint<OpNum> {
31 class SDTCisPtrTy<int OpNum> : SDTypeConstraint<OpNum>;
33 // SDTCisInt - The specified operand is has integer type.
34 class SDTCisInt<int OpNum> : SDTypeConstraint<OpNum>;
36 // SDTCisFP - The specified operand is has floating point type.
37 class SDTCisFP<int OpNum> : SDTypeConstraint<OpNum>;
39 // SDTCisSameAs - The two specified operands have identical types.
40 class SDTCisSameAs<int OpNum, int OtherOp> : SDTypeConstraint<OpNum> {
41 int OtherOperandNum = OtherOp;
44 // SDTCisVTSmallerThanOp - The specified operand is a VT SDNode, and its type is
45 // smaller than the 'Other' operand.
46 class SDTCisVTSmallerThanOp<int OpNum, int OtherOp> : SDTypeConstraint<OpNum> {
47 int OtherOperandNum = OtherOp;
50 class SDTCisOpSmallerThanOp<int SmallOp, int BigOp> : SDTypeConstraint<SmallOp>{
51 int BigOperandNum = BigOp;
54 /// SDTCisIntVectorOfSameSize - This indicates that ThisOp and OtherOp are
55 /// packed vector types, and that ThisOp is the result of
56 /// MVT::getIntVectorWithNumElements with the number of elements that ThisOp
58 class SDTCisIntVectorOfSameSize<int ThisOp, int OtherOp>
59 : SDTypeConstraint<ThisOp> {
60 int OtherOpNum = OtherOp;
63 //===----------------------------------------------------------------------===//
64 // Selection DAG Type Profile definitions.
66 // These use the constraints defined above to describe the type requirements of
67 // the various nodes. These are not hard coded into tblgen, allowing targets to
68 // add their own if needed.
71 // SDTypeProfile - This profile describes the type requirements of a Selection
73 class SDTypeProfile<int numresults, int numoperands,
74 list<SDTypeConstraint> constraints> {
75 int NumResults = numresults;
76 int NumOperands = numoperands;
77 list<SDTypeConstraint> Constraints = constraints;
81 def SDTIntLeaf: SDTypeProfile<1, 0, [SDTCisInt<0>]>; // for 'imm'.
82 def SDTFPLeaf : SDTypeProfile<1, 0, [SDTCisFP<0>]>; // for 'fpimm'.
83 def SDTPtrLeaf: SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>; // for '&g'.
84 def SDTOther : SDTypeProfile<1, 0, [SDTCisVT<0, OtherVT>]>; // for 'vt'.
85 def SDTUNDEF : SDTypeProfile<1, 0, []>; // for 'undef'.
86 def SDTUnaryOp : SDTypeProfile<1, 1, []>; // bitconvert
88 def SDTIntBinOp : SDTypeProfile<1, 2, [ // add, and, or, xor, udiv, etc.
89 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<0>
91 def SDTIntShiftOp : SDTypeProfile<1, 2, [ // shl, sra, srl
92 SDTCisSameAs<0, 1>, SDTCisInt<0>, SDTCisInt<2>
94 def SDTFPBinOp : SDTypeProfile<1, 2, [ // fadd, fmul, etc.
95 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisFP<0>
97 def SDTFPSignOp : SDTypeProfile<1, 2, [ // fcopysign.
98 SDTCisSameAs<0, 1>, SDTCisFP<0>, SDTCisFP<2>
100 def SDTFPTernaryOp : SDTypeProfile<1, 3, [ // fmadd, fnmsub, etc.
101 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>, SDTCisFP<0>
103 def SDTIntUnaryOp : SDTypeProfile<1, 1, [ // ctlz
104 SDTCisSameAs<0, 1>, SDTCisInt<0>
106 def SDTIntExtendOp : SDTypeProfile<1, 1, [ // sext, zext, anyext
107 SDTCisInt<0>, SDTCisInt<1>, SDTCisOpSmallerThanOp<1, 0>
109 def SDTIntTruncOp : SDTypeProfile<1, 1, [ // trunc
110 SDTCisInt<0>, SDTCisInt<1>, SDTCisOpSmallerThanOp<0, 1>
112 def SDTFPUnaryOp : SDTypeProfile<1, 1, [ // fneg, fsqrt, etc
113 SDTCisSameAs<0, 1>, SDTCisFP<0>
115 def SDTFPRoundOp : SDTypeProfile<1, 1, [ // fround
116 SDTCisFP<0>, SDTCisFP<1>, SDTCisOpSmallerThanOp<0, 1>
118 def SDTFPExtendOp : SDTypeProfile<1, 1, [ // fextend
119 SDTCisFP<0>, SDTCisFP<1>, SDTCisOpSmallerThanOp<1, 0>
121 def SDTIntToFPOp : SDTypeProfile<1, 1, [ // [su]int_to_fp
122 SDTCisFP<0>, SDTCisInt<1>
124 def SDTFPToIntOp : SDTypeProfile<1, 1, [ // fp_to_[su]int
125 SDTCisInt<0>, SDTCisFP<1>
127 def SDTExtInreg : SDTypeProfile<1, 2, [ // sext_inreg
128 SDTCisSameAs<0, 1>, SDTCisInt<0>, SDTCisVT<2, OtherVT>,
129 SDTCisVTSmallerThanOp<2, 1>
132 def SDTSetCC : SDTypeProfile<1, 3, [ // setcc
133 SDTCisInt<0>, SDTCisSameAs<1, 2>, SDTCisVT<3, OtherVT>
136 def SDTSelect : SDTypeProfile<1, 3, [ // select
137 SDTCisInt<1>, SDTCisSameAs<0, 2>, SDTCisSameAs<2, 3>
140 def SDTSelectCC : SDTypeProfile<1, 5, [ // select_cc
141 SDTCisSameAs<1, 2>, SDTCisSameAs<3, 4>, SDTCisSameAs<0, 3>,
145 def SDTBr : SDTypeProfile<0, 1, [ // br
149 def SDTBrcond : SDTypeProfile<0, 2, [ // brcond
150 SDTCisInt<0>, SDTCisVT<1, OtherVT>
153 def SDTBrind : SDTypeProfile<0, 1, [ // brind
157 def SDTRet : SDTypeProfile<0, 0, []>; // ret
159 def SDTLoad : SDTypeProfile<1, 1, [ // load
163 def SDTStore : SDTypeProfile<0, 2, [ // store
167 def SDTIStore : SDTypeProfile<1, 3, [ // indexed store
168 SDTCisSameAs<0, 2>, SDTCisPtrTy<0>, SDTCisPtrTy<3>
171 def SDTVecShuffle : SDTypeProfile<1, 3, [
172 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisIntVectorOfSameSize<3, 0>
175 //===----------------------------------------------------------------------===//
176 // Selection DAG Node Properties.
178 // Note: These are hard coded into tblgen.
180 class SDNodeProperty;
181 def SDNPCommutative : SDNodeProperty; // X op Y == Y op X
182 def SDNPAssociative : SDNodeProperty; // (X op Y) op Z == X op (Y op Z)
183 def SDNPHasChain : SDNodeProperty; // R/W chain operand and result
184 def SDNPOutFlag : SDNodeProperty; // Write a flag result
185 def SDNPInFlag : SDNodeProperty; // Read a flag operand
186 def SDNPOptInFlag : SDNodeProperty; // Optionally read a flag operand
188 //===----------------------------------------------------------------------===//
189 // Selection DAG Node definitions.
191 class SDNode<string opcode, SDTypeProfile typeprof,
192 list<SDNodeProperty> props = [], string sdclass = "SDNode"> {
193 string Opcode = opcode;
194 string SDClass = sdclass;
195 list<SDNodeProperty> Properties = props;
196 SDTypeProfile TypeProfile = typeprof;
203 def imm : SDNode<"ISD::Constant" , SDTIntLeaf , [], "ConstantSDNode">;
204 def fpimm : SDNode<"ISD::TargetConstantFP",
205 SDTFPLeaf, [], "ConstantFPSDNode">;
206 def vt : SDNode<"ISD::VALUETYPE" , SDTOther , [], "VTSDNode">;
207 def bb : SDNode<"ISD::BasicBlock", SDTOther , [], "BasicBlockSDNode">;
208 def cond : SDNode<"ISD::CONDCODE" , SDTOther , [], "CondCodeSDNode">;
209 def undef : SDNode<"ISD::UNDEF" , SDTUNDEF , []>;
210 def globaladdr : SDNode<"ISD::GlobalAddress", SDTPtrLeaf, [],
211 "GlobalAddressSDNode">;
212 def tglobaladdr : SDNode<"ISD::TargetGlobalAddress", SDTPtrLeaf, [],
213 "GlobalAddressSDNode">;
214 def constpool : SDNode<"ISD::ConstantPool", SDTPtrLeaf, [],
215 "ConstantPoolSDNode">;
216 def tconstpool : SDNode<"ISD::TargetConstantPool", SDTPtrLeaf, [],
217 "ConstantPoolSDNode">;
218 def jumptable : SDNode<"ISD::JumpTable", SDTPtrLeaf, [],
220 def tjumptable : SDNode<"ISD::TargetJumpTable", SDTPtrLeaf, [],
222 def frameindex : SDNode<"ISD::FrameIndex", SDTPtrLeaf, [],
224 def tframeindex : SDNode<"ISD::TargetFrameIndex", SDTPtrLeaf, [],
226 def externalsym : SDNode<"ISD::ExternalSymbol", SDTPtrLeaf, [],
227 "ExternalSymbolSDNode">;
228 def texternalsym: SDNode<"ISD::TargetExternalSymbol", SDTPtrLeaf, [],
229 "ExternalSymbolSDNode">;
231 def add : SDNode<"ISD::ADD" , SDTIntBinOp ,
232 [SDNPCommutative, SDNPAssociative]>;
233 def sub : SDNode<"ISD::SUB" , SDTIntBinOp>;
234 def mul : SDNode<"ISD::MUL" , SDTIntBinOp,
235 [SDNPCommutative, SDNPAssociative]>;
236 def mulhs : SDNode<"ISD::MULHS" , SDTIntBinOp, [SDNPCommutative]>;
237 def mulhu : SDNode<"ISD::MULHU" , SDTIntBinOp, [SDNPCommutative]>;
238 def sdiv : SDNode<"ISD::SDIV" , SDTIntBinOp>;
239 def udiv : SDNode<"ISD::UDIV" , SDTIntBinOp>;
240 def srem : SDNode<"ISD::SREM" , SDTIntBinOp>;
241 def urem : SDNode<"ISD::UREM" , SDTIntBinOp>;
242 def srl : SDNode<"ISD::SRL" , SDTIntShiftOp>;
243 def sra : SDNode<"ISD::SRA" , SDTIntShiftOp>;
244 def shl : SDNode<"ISD::SHL" , SDTIntShiftOp>;
245 def rotl : SDNode<"ISD::ROTL" , SDTIntShiftOp>;
246 def rotr : SDNode<"ISD::ROTR" , SDTIntShiftOp>;
247 def and : SDNode<"ISD::AND" , SDTIntBinOp,
248 [SDNPCommutative, SDNPAssociative]>;
249 def or : SDNode<"ISD::OR" , SDTIntBinOp,
250 [SDNPCommutative, SDNPAssociative]>;
251 def xor : SDNode<"ISD::XOR" , SDTIntBinOp,
252 [SDNPCommutative, SDNPAssociative]>;
253 def addc : SDNode<"ISD::ADDC" , SDTIntBinOp,
254 [SDNPCommutative, SDNPOutFlag]>;
255 def adde : SDNode<"ISD::ADDE" , SDTIntBinOp,
256 [SDNPCommutative, SDNPOutFlag, SDNPInFlag]>;
257 def subc : SDNode<"ISD::SUBC" , SDTIntBinOp,
259 def sube : SDNode<"ISD::SUBE" , SDTIntBinOp,
260 [SDNPOutFlag, SDNPInFlag]>;
262 def sext_inreg : SDNode<"ISD::SIGN_EXTEND_INREG", SDTExtInreg>;
263 def bswap : SDNode<"ISD::BSWAP" , SDTIntUnaryOp>;
264 def ctlz : SDNode<"ISD::CTLZ" , SDTIntUnaryOp>;
265 def cttz : SDNode<"ISD::CTTZ" , SDTIntUnaryOp>;
266 def ctpop : SDNode<"ISD::CTPOP" , SDTIntUnaryOp>;
267 def sext : SDNode<"ISD::SIGN_EXTEND", SDTIntExtendOp>;
268 def zext : SDNode<"ISD::ZERO_EXTEND", SDTIntExtendOp>;
269 def anyext : SDNode<"ISD::ANY_EXTEND" , SDTIntExtendOp>;
270 def trunc : SDNode<"ISD::TRUNCATE" , SDTIntTruncOp>;
271 def bitconvert : SDNode<"ISD::BIT_CONVERT", SDTUnaryOp>;
273 def fadd : SDNode<"ISD::FADD" , SDTFPBinOp, [SDNPCommutative]>;
274 def fsub : SDNode<"ISD::FSUB" , SDTFPBinOp>;
275 def fmul : SDNode<"ISD::FMUL" , SDTFPBinOp, [SDNPCommutative]>;
276 def fdiv : SDNode<"ISD::FDIV" , SDTFPBinOp>;
277 def frem : SDNode<"ISD::FREM" , SDTFPBinOp>;
278 def fabs : SDNode<"ISD::FABS" , SDTFPUnaryOp>;
279 def fneg : SDNode<"ISD::FNEG" , SDTFPUnaryOp>;
280 def fsqrt : SDNode<"ISD::FSQRT" , SDTFPUnaryOp>;
281 def fsin : SDNode<"ISD::FSIN" , SDTFPUnaryOp>;
282 def fcos : SDNode<"ISD::FCOS" , SDTFPUnaryOp>;
284 def fround : SDNode<"ISD::FP_ROUND" , SDTFPRoundOp>;
285 def fextend : SDNode<"ISD::FP_EXTEND" , SDTFPExtendOp>;
286 def fcopysign : SDNode<"ISD::FCOPYSIGN" , SDTFPSignOp>;
288 def sint_to_fp : SDNode<"ISD::SINT_TO_FP" , SDTIntToFPOp>;
289 def uint_to_fp : SDNode<"ISD::UINT_TO_FP" , SDTIntToFPOp>;
290 def fp_to_sint : SDNode<"ISD::FP_TO_SINT" , SDTFPToIntOp>;
291 def fp_to_uint : SDNode<"ISD::FP_TO_UINT" , SDTFPToIntOp>;
293 def setcc : SDNode<"ISD::SETCC" , SDTSetCC>;
294 def select : SDNode<"ISD::SELECT" , SDTSelect>;
295 def selectcc : SDNode<"ISD::SELECT_CC" , SDTSelectCC>;
297 def brcond : SDNode<"ISD::BRCOND" , SDTBrcond, [SDNPHasChain]>;
298 def brind : SDNode<"ISD::BRIND" , SDTBrind, [SDNPHasChain]>;
299 def br : SDNode<"ISD::BR" , SDTBr, [SDNPHasChain]>;
300 def ret : SDNode<"ISD::RET" , SDTRet, [SDNPHasChain]>;
302 // Do not use ld, st directly. Use load, extload, sextload, zextload, store,
303 // and truncst (see below).
304 def ld : SDNode<"ISD::LOAD" , SDTLoad, [SDNPHasChain]>;
305 def st : SDNode<"ISD::STORE" , SDTStore, [SDNPHasChain]>;
306 def ist : SDNode<"ISD::STORE" , SDTIStore, [SDNPHasChain]>;
308 def vector_shuffle : SDNode<"ISD::VECTOR_SHUFFLE", SDTVecShuffle, []>;
309 def build_vector : SDNode<"ISD::BUILD_VECTOR", SDTypeProfile<1, 0, []>, []>;
310 def scalar_to_vector : SDNode<"ISD::SCALAR_TO_VECTOR", SDTypeProfile<1, 1, []>,
312 def vector_extract : SDNode<"ISD::EXTRACT_VECTOR_ELT",
313 SDTypeProfile<1, 2, [SDTCisPtrTy<2>]>, []>;
314 def vector_insert : SDNode<"ISD::INSERT_VECTOR_ELT",
315 SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisPtrTy<3>]>, []>;
317 // Nodes for intrinsics, you should use the intrinsic itself and let tblgen use
318 // these internally. Don't reference these directly.
319 def intrinsic_void : SDNode<"ISD::INTRINSIC_VOID",
320 SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>,
322 def intrinsic_w_chain : SDNode<"ISD::INTRINSIC_W_CHAIN",
323 SDTypeProfile<1, -1, [SDTCisPtrTy<1>]>,
325 def intrinsic_wo_chain : SDNode<"ISD::INTRINSIC_WO_CHAIN",
326 SDTypeProfile<1, -1, [SDTCisPtrTy<1>]>, []>;
329 //===----------------------------------------------------------------------===//
330 // Selection DAG Condition Codes
332 class CondCode; // ISD::CondCode enums
333 def SETOEQ : CondCode; def SETOGT : CondCode;
334 def SETOGE : CondCode; def SETOLT : CondCode; def SETOLE : CondCode;
335 def SETONE : CondCode; def SETO : CondCode; def SETUO : CondCode;
336 def SETUEQ : CondCode; def SETUGT : CondCode; def SETUGE : CondCode;
337 def SETULT : CondCode; def SETULE : CondCode; def SETUNE : CondCode;
339 def SETEQ : CondCode; def SETGT : CondCode; def SETGE : CondCode;
340 def SETLT : CondCode; def SETLE : CondCode; def SETNE : CondCode;
343 //===----------------------------------------------------------------------===//
344 // Selection DAG Node Transformation Functions.
346 // This mechanism allows targets to manipulate nodes in the output DAG once a
347 // match has been formed. This is typically used to manipulate immediate
350 class SDNodeXForm<SDNode opc, code xformFunction> {
352 code XFormFunction = xformFunction;
355 def NOOP_SDNodeXForm : SDNodeXForm<imm, [{}]>;
358 //===----------------------------------------------------------------------===//
359 // Selection DAG Pattern Fragments.
361 // Pattern fragments are reusable chunks of dags that match specific things.
362 // They can take arguments and have C++ predicates that control whether they
363 // match. They are intended to make the patterns for common instructions more
364 // compact and readable.
367 /// PatFrag - Represents a pattern fragment. This can match something on the
368 /// DAG, frame a single node to multiply nested other fragments.
370 class PatFrag<dag ops, dag frag, code pred = [{}],
371 SDNodeXForm xform = NOOP_SDNodeXForm> {
374 code Predicate = pred;
375 SDNodeXForm OperandTransform = xform;
378 // PatLeaf's are pattern fragments that have no operands. This is just a helper
379 // to define immediates and other common things concisely.
380 class PatLeaf<dag frag, code pred = [{}], SDNodeXForm xform = NOOP_SDNodeXForm>
381 : PatFrag<(ops), frag, pred, xform>;
385 def vtInt : PatLeaf<(vt), [{ return MVT::isInteger(N->getVT()); }]>;
386 def vtFP : PatLeaf<(vt), [{ return MVT::isFloatingPoint(N->getVT()); }]>;
388 def immAllOnes : PatLeaf<(imm), [{ return N->isAllOnesValue(); }]>;
389 def immAllOnesV: PatLeaf<(build_vector), [{
390 return ISD::isBuildVectorAllOnes(N);
392 def immAllZerosV: PatLeaf<(build_vector), [{
393 return ISD::isBuildVectorAllZeros(N);
396 def immAllOnesV_bc: PatLeaf<(bitconvert), [{
397 return ISD::isBuildVectorAllOnes(N);
401 // Other helper fragments.
402 def not : PatFrag<(ops node:$in), (xor node:$in, immAllOnes)>;
403 def vnot : PatFrag<(ops node:$in), (xor node:$in, immAllOnesV)>;
404 def vnot_conv : PatFrag<(ops node:$in), (xor node:$in, immAllOnesV_bc)>;
405 def ineg : PatFrag<(ops node:$in), (sub 0, node:$in)>;
408 def load : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
409 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
410 return LD->getExtensionType() == ISD::NON_EXTLOAD &&
411 LD->getAddressingMode() == ISD::UNINDEXED;
415 // extending load fragments.
416 def extloadi1 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
417 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
418 return LD->getExtensionType() == ISD::EXTLOAD &&
419 LD->getAddressingMode() == ISD::UNINDEXED &&
420 LD->getLoadedVT() == MVT::i1;
423 def extloadi8 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
424 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
425 return LD->getExtensionType() == ISD::EXTLOAD &&
426 LD->getAddressingMode() == ISD::UNINDEXED &&
427 LD->getLoadedVT() == MVT::i8;
430 def extloadi16 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
431 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
432 return LD->getExtensionType() == ISD::EXTLOAD &&
433 LD->getAddressingMode() == ISD::UNINDEXED &&
434 LD->getLoadedVT() == MVT::i16;
437 def extloadi32 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
438 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
439 return LD->getExtensionType() == ISD::EXTLOAD &&
440 LD->getAddressingMode() == ISD::UNINDEXED &&
441 LD->getLoadedVT() == MVT::i32;
444 def extloadf32 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
445 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
446 return LD->getExtensionType() == ISD::EXTLOAD &&
447 LD->getAddressingMode() == ISD::UNINDEXED &&
448 LD->getLoadedVT() == MVT::f32;
452 def sextloadi1 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
453 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
454 return LD->getExtensionType() == ISD::SEXTLOAD &&
455 LD->getAddressingMode() == ISD::UNINDEXED &&
456 LD->getLoadedVT() == MVT::i1;
459 def sextloadi8 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
460 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
461 return LD->getExtensionType() == ISD::SEXTLOAD &&
462 LD->getAddressingMode() == ISD::UNINDEXED &&
463 LD->getLoadedVT() == MVT::i8;
466 def sextloadi16 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
467 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
468 return LD->getExtensionType() == ISD::SEXTLOAD &&
469 LD->getAddressingMode() == ISD::UNINDEXED &&
470 LD->getLoadedVT() == MVT::i16;
473 def sextloadi32 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
474 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
475 return LD->getExtensionType() == ISD::SEXTLOAD &&
476 LD->getAddressingMode() == ISD::UNINDEXED &&
477 LD->getLoadedVT() == MVT::i32;
481 def zextloadi1 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
482 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
483 return LD->getExtensionType() == ISD::ZEXTLOAD &&
484 LD->getAddressingMode() == ISD::UNINDEXED &&
485 LD->getLoadedVT() == MVT::i1;
488 def zextloadi8 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
489 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
490 return LD->getExtensionType() == ISD::ZEXTLOAD &&
491 LD->getAddressingMode() == ISD::UNINDEXED &&
492 LD->getLoadedVT() == MVT::i8;
495 def zextloadi16 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
496 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
497 return LD->getExtensionType() == ISD::ZEXTLOAD &&
498 LD->getAddressingMode() == ISD::UNINDEXED &&
499 LD->getLoadedVT() == MVT::i16;
502 def zextloadi32 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
503 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
504 return LD->getExtensionType() == ISD::ZEXTLOAD &&
505 LD->getAddressingMode() == ISD::UNINDEXED &&
506 LD->getLoadedVT() == MVT::i32;
511 def store : PatFrag<(ops node:$val, node:$ptr),
512 (st node:$val, node:$ptr), [{
513 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
514 return !ST->isTruncatingStore() &&
515 ST->getAddressingMode() == ISD::UNINDEXED;
519 // truncstore fragments.
520 def truncstorei1 : PatFrag<(ops node:$val, node:$ptr),
521 (st node:$val, node:$ptr), [{
522 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
523 return ST->isTruncatingStore() && ST->getStoredVT() == MVT::i1 &&
524 ST->getAddressingMode() == ISD::UNINDEXED;
527 def truncstorei8 : PatFrag<(ops node:$val, node:$ptr),
528 (st node:$val, node:$ptr), [{
529 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
530 return ST->isTruncatingStore() && ST->getStoredVT() == MVT::i8 &&
531 ST->getAddressingMode() == ISD::UNINDEXED;
534 def truncstorei16 : PatFrag<(ops node:$val, node:$ptr),
535 (st node:$val, node:$ptr), [{
536 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
537 return ST->isTruncatingStore() && ST->getStoredVT() == MVT::i16 &&
538 ST->getAddressingMode() == ISD::UNINDEXED;
541 def truncstorei32 : PatFrag<(ops node:$val, node:$ptr),
542 (st node:$val, node:$ptr), [{
543 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
544 return ST->isTruncatingStore() && ST->getStoredVT() == MVT::i32 &&
545 ST->getAddressingMode() == ISD::UNINDEXED;
548 def truncstoref32 : PatFrag<(ops node:$val, node:$ptr),
549 (st node:$val, node:$ptr), [{
550 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
551 return ST->isTruncatingStore() && ST->getStoredVT() == MVT::f32 &&
552 ST->getAddressingMode() == ISD::UNINDEXED;
556 // indexed store fragments.
557 def pre_store : PatFrag<(ops node:$val, node:$base, node:$offset),
558 (ist node:$val, node:$base, node:$offset), [{
559 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
560 ISD::MemIndexedMode AM = ST->getAddressingMode();
561 return (AM == ISD::PRE_INC || AM == ISD::PRE_DEC) &&
562 !ST->isTruncatingStore();
567 def pre_truncsti1 : PatFrag<(ops node:$val, node:$base, node:$offset),
568 (ist node:$val, node:$base, node:$offset), [{
569 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
570 ISD::MemIndexedMode AM = ST->getAddressingMode();
571 return (AM == ISD::PRE_INC || AM == ISD::PRE_DEC) &&
572 ST->isTruncatingStore() && ST->getStoredVT() == MVT::i1;
576 def pre_truncsti8 : PatFrag<(ops node:$val, node:$base, node:$offset),
577 (ist node:$val, node:$base, node:$offset), [{
578 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
579 ISD::MemIndexedMode AM = ST->getAddressingMode();
580 return (AM == ISD::PRE_INC || AM == ISD::PRE_DEC) &&
581 ST->isTruncatingStore() && ST->getStoredVT() == MVT::i8;
585 def pre_truncsti16 : PatFrag<(ops node:$val, node:$base, node:$offset),
586 (ist node:$val, node:$base, node:$offset), [{
587 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
588 ISD::MemIndexedMode AM = ST->getAddressingMode();
589 return (AM == ISD::PRE_INC || AM == ISD::PRE_DEC) &&
590 ST->isTruncatingStore() && ST->getStoredVT() == MVT::i16;
594 def pre_truncsti32 : PatFrag<(ops node:$val, node:$base, node:$offset),
595 (ist node:$val, node:$base, node:$offset), [{
596 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
597 ISD::MemIndexedMode AM = ST->getAddressingMode();
598 return (AM == ISD::PRE_INC || AM == ISD::PRE_DEC) &&
599 ST->isTruncatingStore() && ST->getStoredVT() == MVT::i32;
603 def pre_truncstf32 : PatFrag<(ops node:$val, node:$base, node:$offset),
604 (ist node:$val, node:$base, node:$offset), [{
605 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
606 ISD::MemIndexedMode AM = ST->getAddressingMode();
607 return (AM == ISD::PRE_INC || AM == ISD::PRE_DEC) &&
608 ST->isTruncatingStore() && ST->getStoredVT() == MVT::f32;
613 def post_store : PatFrag<(ops node:$val, node:$ptr, node:$offset),
614 (ist node:$val, node:$ptr, node:$offset), [{
615 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
616 ISD::MemIndexedMode AM = ST->getAddressingMode();
617 return !ST->isTruncatingStore() &&
618 (AM == ISD::POST_INC || AM == ISD::POST_DEC);
623 def post_truncsti1 : PatFrag<(ops node:$val, node:$base, node:$offset),
624 (ist node:$val, node:$base, node:$offset), [{
625 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
626 ISD::MemIndexedMode AM = ST->getAddressingMode();
627 return (AM == ISD::POST_INC || AM == ISD::POST_DEC) &&
628 ST->isTruncatingStore() && ST->getStoredVT() == MVT::i1;
632 def post_truncsti8 : PatFrag<(ops node:$val, node:$base, node:$offset),
633 (ist node:$val, node:$base, node:$offset), [{
634 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
635 ISD::MemIndexedMode AM = ST->getAddressingMode();
636 return (AM == ISD::POST_INC || AM == ISD::POST_DEC) &&
637 ST->isTruncatingStore() && ST->getStoredVT() == MVT::i8;
641 def post_truncsti16 : PatFrag<(ops node:$val, node:$base, node:$offset),
642 (ist node:$val, node:$base, node:$offset), [{
643 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
644 ISD::MemIndexedMode AM = ST->getAddressingMode();
645 return (AM == ISD::POST_INC || AM == ISD::POST_DEC) &&
646 ST->isTruncatingStore() && ST->getStoredVT() == MVT::i16;
650 def post_truncsti32 : PatFrag<(ops node:$val, node:$base, node:$offset),
651 (ist node:$val, node:$base, node:$offset), [{
652 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
653 ISD::MemIndexedMode AM = ST->getAddressingMode();
654 return (AM == ISD::POST_INC || AM == ISD::POST_DEC) &&
655 ST->isTruncatingStore() && ST->getStoredVT() == MVT::i32;
659 def post_truncstf32 : PatFrag<(ops node:$val, node:$base, node:$offset),
660 (ist node:$val, node:$base, node:$offset), [{
661 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
662 ISD::MemIndexedMode AM = ST->getAddressingMode();
663 return (AM == ISD::POST_INC || AM == ISD::POST_DEC) &&
664 ST->isTruncatingStore() && ST->getStoredVT() == MVT::f32;
669 // setcc convenience fragments.
670 def setoeq : PatFrag<(ops node:$lhs, node:$rhs),
671 (setcc node:$lhs, node:$rhs, SETOEQ)>;
672 def setogt : PatFrag<(ops node:$lhs, node:$rhs),
673 (setcc node:$lhs, node:$rhs, SETOGT)>;
674 def setoge : PatFrag<(ops node:$lhs, node:$rhs),
675 (setcc node:$lhs, node:$rhs, SETOGE)>;
676 def setolt : PatFrag<(ops node:$lhs, node:$rhs),
677 (setcc node:$lhs, node:$rhs, SETOLT)>;
678 def setole : PatFrag<(ops node:$lhs, node:$rhs),
679 (setcc node:$lhs, node:$rhs, SETOLE)>;
680 def setone : PatFrag<(ops node:$lhs, node:$rhs),
681 (setcc node:$lhs, node:$rhs, SETONE)>;
682 def seto : PatFrag<(ops node:$lhs, node:$rhs),
683 (setcc node:$lhs, node:$rhs, SETO)>;
684 def setuo : PatFrag<(ops node:$lhs, node:$rhs),
685 (setcc node:$lhs, node:$rhs, SETUO)>;
686 def setueq : PatFrag<(ops node:$lhs, node:$rhs),
687 (setcc node:$lhs, node:$rhs, SETUEQ)>;
688 def setugt : PatFrag<(ops node:$lhs, node:$rhs),
689 (setcc node:$lhs, node:$rhs, SETUGT)>;
690 def setuge : PatFrag<(ops node:$lhs, node:$rhs),
691 (setcc node:$lhs, node:$rhs, SETUGE)>;
692 def setult : PatFrag<(ops node:$lhs, node:$rhs),
693 (setcc node:$lhs, node:$rhs, SETULT)>;
694 def setule : PatFrag<(ops node:$lhs, node:$rhs),
695 (setcc node:$lhs, node:$rhs, SETULE)>;
696 def setune : PatFrag<(ops node:$lhs, node:$rhs),
697 (setcc node:$lhs, node:$rhs, SETUNE)>;
698 def seteq : PatFrag<(ops node:$lhs, node:$rhs),
699 (setcc node:$lhs, node:$rhs, SETEQ)>;
700 def setgt : PatFrag<(ops node:$lhs, node:$rhs),
701 (setcc node:$lhs, node:$rhs, SETGT)>;
702 def setge : PatFrag<(ops node:$lhs, node:$rhs),
703 (setcc node:$lhs, node:$rhs, SETGE)>;
704 def setlt : PatFrag<(ops node:$lhs, node:$rhs),
705 (setcc node:$lhs, node:$rhs, SETLT)>;
706 def setle : PatFrag<(ops node:$lhs, node:$rhs),
707 (setcc node:$lhs, node:$rhs, SETLE)>;
708 def setne : PatFrag<(ops node:$lhs, node:$rhs),
709 (setcc node:$lhs, node:$rhs, SETNE)>;
711 //===----------------------------------------------------------------------===//
712 // Selection DAG Pattern Support.
714 // Patterns are what are actually matched against the target-flavored
715 // instruction selection DAG. Instructions defined by the target implicitly
716 // define patterns in most cases, but patterns can also be explicitly added when
717 // an operation is defined by a sequence of instructions (e.g. loading a large
718 // immediate value on RISC targets that do not support immediates as large as
722 class Pattern<dag patternToMatch, list<dag> resultInstrs> {
723 dag PatternToMatch = patternToMatch;
724 list<dag> ResultInstrs = resultInstrs;
725 list<Predicate> Predicates = []; // See class Instruction in Target.td.
726 int AddedComplexity = 0; // See class Instruction in Target.td.
729 // Pat - A simple (but common) form of a pattern, which produces a simple result
730 // not needing a full list.
731 class Pat<dag pattern, dag result> : Pattern<pattern, [result]>;
733 //===----------------------------------------------------------------------===//
734 // Complex pattern definitions.
736 // Complex patterns, e.g. X86 addressing mode, requires pattern matching code
737 // in C++. NumOperands is the number of operands returned by the select function;
738 // SelectFunc is the name of the function used to pattern match the max. pattern;
739 // RootNodes are the list of possible root nodes of the sub-dags to match.
740 // e.g. X86 addressing mode - def addr : ComplexPattern<4, "SelectAddr", [add]>;
742 class ComplexPattern<ValueType ty, int numops, string fn,
743 list<SDNode> roots = [], list<SDNodeProperty> props = []> {
745 int NumOperands = numops;
746 string SelectFunc = fn;
747 list<SDNode> RootNodes = roots;
748 list<SDNodeProperty> Properties = props;
751 //===----------------------------------------------------------------------===//
754 def SDT_dwarf_loc : SDTypeProfile<0, 3,
755 [SDTCisInt<0>, SDTCisInt<1>, SDTCisInt<2>]>;
756 def dwarf_loc : SDNode<"ISD::DEBUG_LOC", SDT_dwarf_loc,[SDNPHasChain]>;
758 def SDT_dwarf_label : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
759 def dwarf_label : SDNode<"ISD::DEBUG_LABEL", SDT_dwarf_label,[SDNPHasChain]>;