1 //===-- TargetSubtargetInfo.cpp - General Target Information ---------------==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the general parts of a Subtarget.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/Support/CommandLine.h"
15 #include "llvm/Target/TargetSubtargetInfo.h"
16 #include "llvm/ADT/SmallVector.h"
19 //---------------------------------------------------------------------------
20 // TargetSubtargetInfo Class
22 TargetSubtargetInfo::TargetSubtargetInfo() {}
24 TargetSubtargetInfo::~TargetSubtargetInfo() {}
26 // Temporary option to compare overall performance change when moving from the
27 // SD scheduler to the MachineScheduler pass pipeline. It should be removed
28 // before 3.4. The normal way to enable/disable the MachineScheduling pass
29 // itself is by using -enable-misched. For targets that already use MI sched
30 // (via MySubTarget::enableMachineScheduler()) -misched-bench=false negates the
32 static cl::opt<bool> BenchMachineSched("misched-bench", cl::Hidden,
33 cl::desc("Migrate from the target's default SD scheduler to MI scheduler"));
35 bool TargetSubtargetInfo::useMachineScheduler() const {
36 if (BenchMachineSched.getNumOccurrences())
37 return BenchMachineSched;
38 return enableMachineScheduler();
41 bool TargetSubtargetInfo::enableMachineScheduler() const {
45 bool TargetSubtargetInfo::enablePostRAScheduler(
46 CodeGenOpt::Level OptLevel,
47 AntiDepBreakMode& Mode,
48 RegClassVector& CriticalPathRCs) const {
50 CriticalPathRCs.clear();
54 bool TargetSubtargetInfo::useAA() const {