1 //===-- TargetSubtargetInfo.cpp - General Target Information ---------------==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the general parts of a Subtarget.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/Support/CommandLine.h"
15 #include "llvm/ADT/SmallVector.h"
16 #include "llvm/Target/TargetSubtargetInfo.h"
19 //---------------------------------------------------------------------------
20 // TargetSubtargetInfo Class
22 TargetSubtargetInfo::TargetSubtargetInfo(
23 const Triple &TT, StringRef CPU, StringRef FS,
24 ArrayRef<SubtargetFeatureKV> PF, ArrayRef<SubtargetFeatureKV> PD,
25 const SubtargetInfoKV *ProcSched, const MCWriteProcResEntry *WPR,
26 const MCWriteLatencyEntry *WL, const MCReadAdvanceEntry *RA,
27 const InstrStage *IS, const unsigned *OC, const unsigned *FP)
28 : MCSubtargetInfo(TT, CPU, FS, PF, PD, ProcSched, WPR, WL, RA, IS, OC, FP) {
31 TargetSubtargetInfo::~TargetSubtargetInfo() {}
33 bool TargetSubtargetInfo::enableAtomicExpand() const {
37 bool TargetSubtargetInfo::enableMachineScheduler() const {
41 bool TargetSubtargetInfo::enableJoinGlobalCopies() const {
42 return enableMachineScheduler();
45 bool TargetSubtargetInfo::enableRALocalReassignment(
46 CodeGenOpt::Level OptLevel) const {
50 bool TargetSubtargetInfo::enablePostRAScheduler() const {
51 return getSchedModel().PostRAScheduler;
54 bool TargetSubtargetInfo::useAA() const {