1 // llvm/Target/TargetTransformImpl.cpp - Target Loop Trans Info ---*- C++ -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "llvm/Target/TargetTransformImpl.h"
11 #include "llvm/Target/TargetLowering.h"
16 //===----------------------------------------------------------------------===//
18 // Calls used by scalar transformations.
20 //===----------------------------------------------------------------------===//
22 bool ScalarTargetTransformImpl::isLegalAddImmediate(int64_t imm) const {
23 return TLI->isLegalAddImmediate(imm);
26 bool ScalarTargetTransformImpl::isLegalICmpImmediate(int64_t imm) const {
27 return TLI->isLegalICmpImmediate(imm);
30 bool ScalarTargetTransformImpl::isLegalAddressingMode(const AddrMode &AM,
32 return TLI->isLegalAddressingMode(AM, Ty);
35 bool ScalarTargetTransformImpl::isTruncateFree(Type *Ty1, Type *Ty2) const {
36 return TLI->isTruncateFree(Ty1, Ty2);
39 bool ScalarTargetTransformImpl::isTypeLegal(Type *Ty) const {
40 EVT T = TLI->getValueType(Ty);
41 return TLI->isTypeLegal(T);
44 unsigned ScalarTargetTransformImpl::getJumpBufAlignment() const {
45 return TLI->getJumpBufAlignment();
48 unsigned ScalarTargetTransformImpl::getJumpBufSize() const {
49 return TLI->getJumpBufSize();
52 //===----------------------------------------------------------------------===//
54 // Calls used by the vectorizers.
56 //===----------------------------------------------------------------------===//
57 static int InstructionOpcodeToISD(unsigned Opcode) {
58 enum InstructionOpcodes {
59 #define HANDLE_INST(NUM, OPCODE, CLASS) OPCODE = NUM,
60 #define LAST_OTHER_INST(NUM) InstructionOpcodesCount = NUM
61 #include "llvm/Instruction.def"
63 switch (static_cast<InstructionOpcodes>(Opcode)) {
66 case Switch: return 0;
67 case IndirectBr: return 0;
68 case Invoke: return 0;
69 case Resume: return 0;
70 case Unreachable: return 0;
71 case Add: return ISD::ADD;
72 case FAdd: return ISD::FADD;
73 case Sub: return ISD::SUB;
74 case FSub: return ISD::FSUB;
75 case Mul: return ISD::MUL;
76 case FMul: return ISD::FMUL;
77 case UDiv: return ISD::UDIV;
78 case SDiv: return ISD::UDIV;
79 case FDiv: return ISD::FDIV;
80 case URem: return ISD::UREM;
81 case SRem: return ISD::SREM;
82 case FRem: return ISD::FREM;
83 case Shl: return ISD::SHL;
84 case LShr: return ISD::SRL;
85 case AShr: return ISD::SRA;
86 case And: return ISD::AND;
87 case Or: return ISD::OR;
88 case Xor: return ISD::XOR;
89 case Alloca: return 0;
90 case Load: return ISD::LOAD;
91 case Store: return ISD::STORE;
92 case GetElementPtr: return 0;
94 case AtomicCmpXchg: return 0;
95 case AtomicRMW: return 0;
96 case Trunc: return ISD::TRUNCATE;
97 case ZExt: return ISD::ZERO_EXTEND;
98 case SExt: return ISD::SEXTLOAD;
99 case FPToUI: return ISD::FP_TO_UINT;
100 case FPToSI: return ISD::FP_TO_SINT;
101 case UIToFP: return ISD::UINT_TO_FP;
102 case SIToFP: return ISD::SINT_TO_FP;
103 case FPTrunc: return ISD::FP_ROUND;
104 case FPExt: return ISD::FP_EXTEND;
105 case PtrToInt: return ISD::BITCAST;
106 case IntToPtr: return ISD::BITCAST;
107 case BitCast: return ISD::BITCAST;
108 case ICmp: return ISD::SETCC;
109 case FCmp: return ISD::SETCC;
112 case Select: return ISD::SELECT;
113 case UserOp1: return 0;
114 case UserOp2: return 0;
115 case VAArg: return 0;
116 case ExtractElement: return ISD::EXTRACT_VECTOR_ELT;
117 case InsertElement: return ISD::INSERT_VECTOR_ELT;
118 case ShuffleVector: return ISD::VECTOR_SHUFFLE;
119 case ExtractValue: return ISD::MERGE_VALUES;
120 case InsertValue: return ISD::MERGE_VALUES;
121 case LandingPad: return 0;
124 llvm_unreachable("Unknown instruction type encountered!");
127 std::pair<unsigned, EVT>
128 VectorTargetTransformImpl::getTypeLegalizationCost(LLVMContext &C,
131 // We keep legalizing the type until we find a legal kind. We assume that
132 // the only operation that costs anything is the split. After splitting
133 // we need to handle two types.
135 TargetLowering::LegalizeKind LK = TLI->getTypeConversion(C, Ty);
137 if (LK.first == TargetLowering::TypeLegal)
138 return std::make_pair(Cost, LK.second);
140 if (LK.first == TargetLowering::TypeSplitVector)
143 // Keep legalizing the type.
149 VectorTargetTransformImpl::getInstrCost(unsigned Opcode, Type *Ty1,
151 // Check if any of the operands are vector operands.
152 int ISD = InstructionOpcodeToISD(Opcode);
154 // If we don't have any information about this instruction assume it costs 1.
158 // Selects on vectors are actually vector selects.
159 if (ISD == ISD::SELECT) {
160 assert(Ty2 && "Ty2 must hold the condition type");
161 if (Ty2->isVectorTy())
165 assert(Ty1 && "We need to have at least one type");
167 // From this stage we look at the legalized type.
168 std::pair<unsigned, EVT> LT =
169 getTypeLegalizationCost(Ty1->getContext(), TLI->getValueType(Ty1));
171 if (TLI->isOperationLegalOrCustom(ISD, LT.second)) {
172 // The operation is legal. Assume it costs 1. Multiply
173 // by the type-legalization overhead.
178 (LT.second.isVector() ? LT.second.getVectorNumElements() : 1);
180 // We will probably scalarize this instruction. Assume that the cost is the
181 // number of the vector elements.
182 return LT.first * NumElem * 1;
186 VectorTargetTransformImpl::getBroadcastCost(Type *Tp) const {
191 VectorTargetTransformImpl::getMemoryOpCost(unsigned Opcode, Type *Src,
193 unsigned AddressSpace) const {
194 // From this stage we look at the legalized type.
195 std::pair<unsigned, EVT> LT =
196 getTypeLegalizationCost(Src->getContext(), TLI->getValueType(Src));
197 // Assume that all loads of legal types cost 1.
202 VectorTargetTransformImpl::getNumberOfParts(Type *Tp) const {
203 std::pair<unsigned, EVT> LT =
204 getTypeLegalizationCost(Tp->getContext(), TLI->getValueType(Tp));