1 //- WebAssembly.td - Describe the WebAssembly Target Machine --*- tablegen -*-//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief This is a target description file for the WebAssembly architecture,
12 /// which is also known as "wasm".
14 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
17 // Target-independent interfaces which we are implementing
18 //===----------------------------------------------------------------------===//
20 include "llvm/Target/Target.td"
22 //===----------------------------------------------------------------------===//
23 // WebAssembly Subtarget features.
24 //===----------------------------------------------------------------------===//
26 def FeatureSIMD128 : SubtargetFeature<"simd128", "HasSIMD128", "false",
27 "Enable 128-bit SIMD">;
29 //===----------------------------------------------------------------------===//
31 //===----------------------------------------------------------------------===//
33 //===----------------------------------------------------------------------===//
34 // Register File Description
35 //===----------------------------------------------------------------------===//
37 include "WebAssemblyRegisterInfo.td"
39 //===----------------------------------------------------------------------===//
40 // Instruction Descriptions
41 //===----------------------------------------------------------------------===//
43 include "WebAssemblyInstrInfo.td"
45 def WebAssemblyInstrInfo : InstrInfo;
47 //===----------------------------------------------------------------------===//
48 // WebAssembly Processors supported.
49 //===----------------------------------------------------------------------===//
51 // Minimal Viable Product.
52 def : ProcessorModel<"mvp", NoSchedModel, []>;
54 // Generic processor: latest stable version.
55 def : ProcessorModel<"generic", NoSchedModel, []>;
57 // Latest and greatest experimental version of WebAssembly. Bugs included!
58 def : ProcessorModel<"bleeding-edge", NoSchedModel, [FeatureSIMD128]>;
60 //===----------------------------------------------------------------------===//
62 //===----------------------------------------------------------------------===//
64 def WebAssembly : Target {
65 let InstructionSet = WebAssemblyInstrInfo;