1 //- WebAssembly.td - Describe the WebAssembly Target Machine --*- tablegen -*-//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This is a target description file for the WebAssembly architecture, which is
11 // also known as "wasm".
13 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
16 // Target-independent interfaces which we are implementing
17 //===----------------------------------------------------------------------===//
19 include "llvm/Target/Target.td"
21 //===----------------------------------------------------------------------===//
22 // WebAssembly Subtarget features.
23 //===----------------------------------------------------------------------===//
25 def FeatureSIMD128 : SubtargetFeature<"simd128", "HasSIMD128", "false",
26 "Enable 128-bit SIMD">;
28 //===----------------------------------------------------------------------===//
30 //===----------------------------------------------------------------------===//
32 //===----------------------------------------------------------------------===//
33 // Register File Description
34 //===----------------------------------------------------------------------===//
36 include "WebAssemblyRegisterInfo.td"
38 //===----------------------------------------------------------------------===//
39 // Instruction Descriptions
40 //===----------------------------------------------------------------------===//
42 include "WebAssemblyInstrInfo.td"
44 def WebAssemblyInstrInfo : InstrInfo;
46 //===----------------------------------------------------------------------===//
47 // WebAssembly Processors supported.
48 //===----------------------------------------------------------------------===//
50 // Minimal Viable Product.
51 def : ProcessorModel<"mvp", NoSchedModel, []>;
53 // Latest and greatest experimental version of WebAssembly. Bugs included!
54 def : ProcessorModel<"bleeding-edge", NoSchedModel, [FeatureSIMD128]>;
56 //===----------------------------------------------------------------------===//
58 //===----------------------------------------------------------------------===//
60 def WebAssembly : Target {
61 let InstructionSet = WebAssemblyInstrInfo;