1 //=- WebAssemblyISelLowering.cpp - WebAssembly DAG Lowering Implementation -==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief This file implements the WebAssemblyTargetLowering class.
13 //===----------------------------------------------------------------------===//
15 #include "WebAssemblyISelLowering.h"
16 #include "MCTargetDesc/WebAssemblyMCTargetDesc.h"
17 #include "WebAssemblyMachineFunctionInfo.h"
18 #include "WebAssemblySubtarget.h"
19 #include "WebAssemblyTargetMachine.h"
20 #include "WebAssemblyTargetObjectFile.h"
21 #include "llvm/CodeGen/Analysis.h"
22 #include "llvm/CodeGen/CallingConvLower.h"
23 #include "llvm/CodeGen/MachineJumpTableInfo.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 #include "llvm/CodeGen/SelectionDAG.h"
26 #include "llvm/IR/DiagnosticInfo.h"
27 #include "llvm/IR/DiagnosticPrinter.h"
28 #include "llvm/IR/Function.h"
29 #include "llvm/IR/Intrinsics.h"
30 #include "llvm/Support/CommandLine.h"
31 #include "llvm/Support/Debug.h"
32 #include "llvm/Support/ErrorHandling.h"
33 #include "llvm/Support/raw_ostream.h"
34 #include "llvm/Target/TargetOptions.h"
37 #define DEBUG_TYPE "wasm-lower"
40 // Diagnostic information for unimplemented or unsupported feature reporting.
41 // TODO: This code is copied from BPF and AMDGPU; consider factoring it out
43 class DiagnosticInfoUnsupported final : public DiagnosticInfo {
45 // Debug location where this diagnostic is triggered.
47 const Twine &Description;
53 static int getKindID() {
55 KindID = llvm::getNextAvailablePluginDiagnosticKind();
60 DiagnosticInfoUnsupported(SDLoc DLoc, const Function &Fn, const Twine &Desc,
62 : DiagnosticInfo(getKindID(), DS_Error), DLoc(DLoc.getDebugLoc()),
63 Description(Desc), Fn(Fn), Value(Value) {}
65 void print(DiagnosticPrinter &DP) const override {
67 raw_string_ostream OS(Str);
70 auto DIL = DLoc.get();
71 StringRef Filename = DIL->getFilename();
72 unsigned Line = DIL->getLine();
73 unsigned Column = DIL->getColumn();
74 OS << Filename << ':' << Line << ':' << Column << ' ';
77 OS << "in function " << Fn.getName() << ' ' << *Fn.getFunctionType() << '\n'
86 static bool classof(const DiagnosticInfo *DI) {
87 return DI->getKind() == getKindID();
91 int DiagnosticInfoUnsupported::KindID = 0;
92 } // end anonymous namespace
94 WebAssemblyTargetLowering::WebAssemblyTargetLowering(
95 const TargetMachine &TM, const WebAssemblySubtarget &STI)
96 : TargetLowering(TM), Subtarget(&STI) {
97 auto MVTPtr = Subtarget->hasAddr64() ? MVT::i64 : MVT::i32;
99 // Booleans always contain 0 or 1.
100 setBooleanContents(ZeroOrOneBooleanContent);
101 // WebAssembly does not produce floating-point exceptions on normal floating
103 setHasFloatingPointExceptions(false);
104 // We don't know the microarchitecture here, so just reduce register pressure.
105 setSchedulingPreference(Sched::RegPressure);
106 // Tell ISel that we have a stack pointer.
107 setStackPointerRegisterToSaveRestore(
108 Subtarget->hasAddr64() ? WebAssembly::SP64 : WebAssembly::SP32);
109 // Set up the register classes.
110 addRegisterClass(MVT::i32, &WebAssembly::I32RegClass);
111 addRegisterClass(MVT::i64, &WebAssembly::I64RegClass);
112 addRegisterClass(MVT::f32, &WebAssembly::F32RegClass);
113 addRegisterClass(MVT::f64, &WebAssembly::F64RegClass);
114 // Compute derived properties from the register classes.
115 computeRegisterProperties(Subtarget->getRegisterInfo());
117 setOperationAction(ISD::GlobalAddress, MVTPtr, Custom);
118 setOperationAction(ISD::ExternalSymbol, MVTPtr, Custom);
119 setOperationAction(ISD::JumpTable, MVTPtr, Custom);
121 // Take the default expansion for va_arg, va_copy, and va_end. There is no
122 // default action for va_start, so we do that custom.
123 setOperationAction(ISD::VASTART, MVT::Other, Custom);
124 setOperationAction(ISD::VAARG, MVT::Other, Expand);
125 setOperationAction(ISD::VACOPY, MVT::Other, Expand);
126 setOperationAction(ISD::VAEND, MVT::Other, Expand);
128 for (auto T : {MVT::f32, MVT::f64}) {
129 // Don't expand the floating-point types to constant pools.
130 setOperationAction(ISD::ConstantFP, T, Legal);
131 // Expand floating-point comparisons.
132 for (auto CC : {ISD::SETO, ISD::SETUO, ISD::SETUEQ, ISD::SETONE,
133 ISD::SETULT, ISD::SETULE, ISD::SETUGT, ISD::SETUGE})
134 setCondCodeAction(CC, T, Expand);
135 // Expand floating-point library function operators.
136 for (auto Op : {ISD::FSIN, ISD::FCOS, ISD::FSINCOS, ISD::FPOWI, ISD::FPOW,
137 ISD::FREM, ISD::FMA})
138 setOperationAction(Op, T, Expand);
139 // Note supported floating-point library function operators that otherwise
140 // default to expand.
142 {ISD::FCEIL, ISD::FFLOOR, ISD::FTRUNC, ISD::FNEARBYINT, ISD::FRINT})
143 setOperationAction(Op, T, Legal);
144 // Support minnan and maxnan, which otherwise default to expand.
145 setOperationAction(ISD::FMINNAN, T, Legal);
146 setOperationAction(ISD::FMAXNAN, T, Legal);
149 for (auto T : {MVT::i32, MVT::i64}) {
150 // Expand unavailable integer operations.
152 {ISD::BSWAP, ISD::ROTL, ISD::ROTR, ISD::SMUL_LOHI, ISD::UMUL_LOHI,
153 ISD::MULHS, ISD::MULHU, ISD::SDIVREM, ISD::UDIVREM, ISD::SHL_PARTS,
154 ISD::SRA_PARTS, ISD::SRL_PARTS, ISD::ADDC, ISD::ADDE, ISD::SUBC,
156 setOperationAction(Op, T, Expand);
160 // As a special case, these operators use the type to mean the type to
162 for (auto T : {MVT::i1, MVT::i8, MVT::i16, MVT::i32})
163 setOperationAction(ISD::SIGN_EXTEND_INREG, T, Expand);
165 // Dynamic stack allocation: use the default expansion.
166 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
167 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
168 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVTPtr, Expand);
170 // Expand these forms; we pattern-match the forms that we can handle in isel.
171 for (auto T : {MVT::i32, MVT::i64, MVT::f32, MVT::f64})
172 for (auto Op : {ISD::BR_CC, ISD::SELECT_CC})
173 setOperationAction(Op, T, Expand);
175 // We have custom switch handling.
176 setOperationAction(ISD::BR_JT, MVT::Other, Custom);
178 // WebAssembly doesn't have:
179 // - Floating-point extending loads.
180 // - Floating-point truncating stores.
181 // - i1 extending loads.
182 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f32, Expand);
183 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
184 for (auto T : MVT::integer_valuetypes())
185 for (auto Ext : {ISD::EXTLOAD, ISD::ZEXTLOAD, ISD::SEXTLOAD})
186 setLoadExtAction(Ext, T, MVT::i1, Promote);
188 // Trap lowers to wasm unreachable
189 setOperationAction(ISD::TRAP, MVT::Other, Legal);
192 FastISel *WebAssemblyTargetLowering::createFastISel(
193 FunctionLoweringInfo &FuncInfo, const TargetLibraryInfo *LibInfo) const {
194 return WebAssembly::createFastISel(FuncInfo, LibInfo);
197 bool WebAssemblyTargetLowering::isOffsetFoldingLegal(
198 const GlobalAddressSDNode * /*GA*/) const {
199 // All offsets can be folded.
203 MVT WebAssemblyTargetLowering::getScalarShiftAmountTy(const DataLayout & /*DL*/,
205 unsigned BitWidth = NextPowerOf2(VT.getSizeInBits() - 1);
206 if (BitWidth > 1 && BitWidth < 8)
208 MVT Result = MVT::getIntegerVT(BitWidth);
209 assert(Result != MVT::INVALID_SIMPLE_VALUE_TYPE &&
210 "Unable to represent scalar shift amount type");
215 WebAssemblyTargetLowering::getTargetNodeName(unsigned Opcode) const {
216 switch (static_cast<WebAssemblyISD::NodeType>(Opcode)) {
217 case WebAssemblyISD::FIRST_NUMBER:
219 #define HANDLE_NODETYPE(NODE) \
220 case WebAssemblyISD::NODE: \
221 return "WebAssemblyISD::" #NODE;
222 #include "WebAssemblyISD.def"
223 #undef HANDLE_NODETYPE
228 std::pair<unsigned, const TargetRegisterClass *>
229 WebAssemblyTargetLowering::getRegForInlineAsmConstraint(
230 const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const {
231 // First, see if this is a constraint that directly corresponds to a
232 // WebAssembly register class.
233 if (Constraint.size() == 1) {
234 switch (Constraint[0]) {
236 assert(VT != MVT::iPTR && "Pointer MVT not expected here");
237 if (VT.isInteger() && !VT.isVector()) {
238 if (VT.getSizeInBits() <= 32)
239 return std::make_pair(0U, &WebAssembly::I32RegClass);
240 if (VT.getSizeInBits() <= 64)
241 return std::make_pair(0U, &WebAssembly::I64RegClass);
249 return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
252 bool WebAssemblyTargetLowering::isCheapToSpeculateCttz() const {
253 // Assume ctz is a relatively cheap operation.
257 bool WebAssemblyTargetLowering::isCheapToSpeculateCtlz() const {
258 // Assume clz is a relatively cheap operation.
262 //===----------------------------------------------------------------------===//
263 // WebAssembly Lowering private implementation.
264 //===----------------------------------------------------------------------===//
266 //===----------------------------------------------------------------------===//
268 //===----------------------------------------------------------------------===//
270 static void fail(SDLoc DL, SelectionDAG &DAG, const char *msg) {
271 MachineFunction &MF = DAG.getMachineFunction();
272 DAG.getContext()->diagnose(
273 DiagnosticInfoUnsupported(DL, *MF.getFunction(), msg, SDValue()));
276 // Test whether the given calling convention is supported.
277 static bool CallingConvSupported(CallingConv::ID CallConv) {
278 // We currently support the language-independent target-independent
279 // conventions. We don't yet have a way to annotate calls with properties like
280 // "cold", and we don't have any call-clobbered registers, so these are mostly
281 // all handled the same.
282 return CallConv == CallingConv::C || CallConv == CallingConv::Fast ||
283 CallConv == CallingConv::Cold ||
284 CallConv == CallingConv::PreserveMost ||
285 CallConv == CallingConv::PreserveAll ||
286 CallConv == CallingConv::CXX_FAST_TLS;
290 WebAssemblyTargetLowering::LowerCall(CallLoweringInfo &CLI,
291 SmallVectorImpl<SDValue> &InVals) const {
292 SelectionDAG &DAG = CLI.DAG;
294 SDValue Chain = CLI.Chain;
295 SDValue Callee = CLI.Callee;
296 MachineFunction &MF = DAG.getMachineFunction();
298 CallingConv::ID CallConv = CLI.CallConv;
299 if (!CallingConvSupported(CallConv))
301 "WebAssembly doesn't support language-specific or target-specific "
302 "calling conventions yet");
303 if (CLI.IsPatchPoint)
304 fail(DL, DAG, "WebAssembly doesn't support patch point yet");
306 // WebAssembly doesn't currently support explicit tail calls. If they are
307 // required, fail. Otherwise, just disable them.
308 if ((CallConv == CallingConv::Fast && CLI.IsTailCall &&
309 MF.getTarget().Options.GuaranteedTailCallOpt) ||
310 (CLI.CS && CLI.CS->isMustTailCall()))
311 fail(DL, DAG, "WebAssembly doesn't support tail call yet");
312 CLI.IsTailCall = false;
314 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
316 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
318 fail(DL, DAG, "WebAssembly doesn't support more than 1 returned value yet");
320 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
321 for (const ISD::OutputArg &Out : Outs) {
322 if (Out.Flags.isByVal())
323 fail(DL, DAG, "WebAssembly hasn't implemented byval arguments");
324 if (Out.Flags.isNest())
325 fail(DL, DAG, "WebAssembly hasn't implemented nest arguments");
326 if (Out.Flags.isInAlloca())
327 fail(DL, DAG, "WebAssembly hasn't implemented inalloca arguments");
328 if (Out.Flags.isInConsecutiveRegs())
329 fail(DL, DAG, "WebAssembly hasn't implemented cons regs arguments");
330 if (Out.Flags.isInConsecutiveRegsLast())
331 fail(DL, DAG, "WebAssembly hasn't implemented cons regs last arguments");
334 bool IsVarArg = CLI.IsVarArg;
335 unsigned NumFixedArgs = CLI.NumFixedArgs;
336 auto PtrVT = getPointerTy(MF.getDataLayout());
338 // Analyze operands of the call, assigning locations to each operand.
339 SmallVector<CCValAssign, 16> ArgLocs;
340 CCState CCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext());
343 // Outgoing non-fixed arguments are placed at the top of the stack. First
344 // compute their offsets and the total amount of argument stack space
347 make_range(OutVals.begin() + NumFixedArgs, OutVals.end())) {
348 EVT VT = Arg.getValueType();
349 assert(VT != MVT::iPTR && "Legalized args should be concrete");
350 Type *Ty = VT.getTypeForEVT(*DAG.getContext());
352 CCInfo.AllocateStack(MF.getDataLayout().getTypeAllocSize(Ty),
353 MF.getDataLayout().getABITypeAlignment(Ty));
354 CCInfo.addLoc(CCValAssign::getMem(ArgLocs.size(), VT.getSimpleVT(),
355 Offset, VT.getSimpleVT(),
360 unsigned NumBytes = CCInfo.getAlignedCallFrameSize();
362 auto NB = DAG.getConstant(NumBytes, DL, PtrVT, true);
363 Chain = DAG.getCALLSEQ_START(Chain, NB, DL);
366 // For non-fixed arguments, next emit stores to store the argument values
367 // to the stack at the offsets computed above.
368 SDValue SP = DAG.getCopyFromReg(
369 Chain, DL, getStackPointerRegisterToSaveRestore(), PtrVT);
371 SmallVector<SDValue, 8> Chains;
373 make_range(OutVals.begin() + NumFixedArgs, OutVals.end())) {
374 assert(ArgLocs[ValNo].getValNo() == ValNo &&
375 "ArgLocs should remain in order and only hold varargs args");
376 unsigned Offset = ArgLocs[ValNo++].getLocMemOffset();
377 SDValue Add = DAG.getNode(ISD::ADD, DL, PtrVT, SP,
378 DAG.getConstant(Offset, DL, PtrVT));
379 Chains.push_back(DAG.getStore(Chain, DL, Arg, Add,
380 MachinePointerInfo::getStack(MF, Offset),
384 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Chains);
387 // Compute the operands for the CALLn node.
388 SmallVector<SDValue, 16> Ops;
389 Ops.push_back(Chain);
390 Ops.push_back(Callee);
392 // Add all fixed arguments. Note that for non-varargs calls, NumFixedArgs
394 Ops.append(OutVals.begin(),
395 IsVarArg ? OutVals.begin() + NumFixedArgs : OutVals.end());
397 SmallVector<EVT, 8> Tys;
398 for (const auto &In : Ins) {
399 assert(!In.Flags.isByVal() && "byval is not valid for return values");
400 assert(!In.Flags.isNest() && "nest is not valid for return values");
401 if (In.Flags.isInAlloca())
402 fail(DL, DAG, "WebAssembly hasn't implemented inalloca return values");
403 if (In.Flags.isInConsecutiveRegs())
404 fail(DL, DAG, "WebAssembly hasn't implemented cons regs return values");
405 if (In.Flags.isInConsecutiveRegsLast())
406 fail(DL, DAG, "WebAssembly hasn't implemented cons regs last return values");
407 // Ignore In.getOrigAlign() because all our arguments are passed in
409 Tys.push_back(In.VT);
411 Tys.push_back(MVT::Other);
412 SDVTList TyList = DAG.getVTList(Tys);
414 DAG.getNode(Ins.empty() ? WebAssemblyISD::CALL0 : WebAssemblyISD::CALL1,
419 InVals.push_back(Res);
420 Chain = Res.getValue(1);
423 SDValue Unused = DAG.getUNDEF(PtrVT);
424 Chain = DAG.getCALLSEQ_END(Chain, NB, Unused, SDValue(), DL);
429 bool WebAssemblyTargetLowering::CanLowerReturn(
430 CallingConv::ID /*CallConv*/, MachineFunction & /*MF*/, bool /*IsVarArg*/,
431 const SmallVectorImpl<ISD::OutputArg> &Outs,
432 LLVMContext & /*Context*/) const {
433 // WebAssembly can't currently handle returning tuples.
434 return Outs.size() <= 1;
437 SDValue WebAssemblyTargetLowering::LowerReturn(
438 SDValue Chain, CallingConv::ID CallConv, bool /*IsVarArg*/,
439 const SmallVectorImpl<ISD::OutputArg> &Outs,
440 const SmallVectorImpl<SDValue> &OutVals, SDLoc DL,
441 SelectionDAG &DAG) const {
442 assert(Outs.size() <= 1 && "WebAssembly can only return up to one value");
443 if (!CallingConvSupported(CallConv))
444 fail(DL, DAG, "WebAssembly doesn't support non-C calling conventions");
446 SmallVector<SDValue, 4> RetOps(1, Chain);
447 RetOps.append(OutVals.begin(), OutVals.end());
448 Chain = DAG.getNode(WebAssemblyISD::RETURN, DL, MVT::Other, RetOps);
450 // Record the number and types of the return values.
451 for (const ISD::OutputArg &Out : Outs) {
452 assert(!Out.Flags.isByVal() && "byval is not valid for return values");
453 assert(!Out.Flags.isNest() && "nest is not valid for return values");
454 assert(Out.IsFixed && "non-fixed return value is not valid");
455 if (Out.Flags.isInAlloca())
456 fail(DL, DAG, "WebAssembly hasn't implemented inalloca results");
457 if (Out.Flags.isInConsecutiveRegs())
458 fail(DL, DAG, "WebAssembly hasn't implemented cons regs results");
459 if (Out.Flags.isInConsecutiveRegsLast())
460 fail(DL, DAG, "WebAssembly hasn't implemented cons regs last results");
466 SDValue WebAssemblyTargetLowering::LowerFormalArguments(
467 SDValue Chain, CallingConv::ID CallConv, bool /*IsVarArg*/,
468 const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc DL, SelectionDAG &DAG,
469 SmallVectorImpl<SDValue> &InVals) const {
470 MachineFunction &MF = DAG.getMachineFunction();
472 if (!CallingConvSupported(CallConv))
473 fail(DL, DAG, "WebAssembly doesn't support non-C calling conventions");
475 // Set up the incoming ARGUMENTS value, which serves to represent the liveness
476 // of the incoming values before they're represented by virtual registers.
477 MF.getRegInfo().addLiveIn(WebAssembly::ARGUMENTS);
479 for (const ISD::InputArg &In : Ins) {
480 if (In.Flags.isByVal())
481 fail(DL, DAG, "WebAssembly hasn't implemented byval arguments");
482 if (In.Flags.isInAlloca())
483 fail(DL, DAG, "WebAssembly hasn't implemented inalloca arguments");
484 if (In.Flags.isNest())
485 fail(DL, DAG, "WebAssembly hasn't implemented nest arguments");
486 if (In.Flags.isInConsecutiveRegs())
487 fail(DL, DAG, "WebAssembly hasn't implemented cons regs arguments");
488 if (In.Flags.isInConsecutiveRegsLast())
489 fail(DL, DAG, "WebAssembly hasn't implemented cons regs last arguments");
490 // Ignore In.getOrigAlign() because all our arguments are passed in
494 ? DAG.getNode(WebAssemblyISD::ARGUMENT, DL, In.VT,
495 DAG.getTargetConstant(InVals.size(), DL, MVT::i32))
496 : DAG.getUNDEF(In.VT));
498 // Record the number and types of arguments.
499 MF.getInfo<WebAssemblyFunctionInfo>()->addParam(In.VT);
502 // Incoming varargs arguments are on the stack and will be accessed through
503 // va_arg, so we don't need to do anything for them here.
508 //===----------------------------------------------------------------------===//
509 // Custom lowering hooks.
510 //===----------------------------------------------------------------------===//
512 SDValue WebAssemblyTargetLowering::LowerOperation(SDValue Op,
513 SelectionDAG &DAG) const {
514 switch (Op.getOpcode()) {
516 llvm_unreachable("unimplemented operation lowering");
518 case ISD::GlobalAddress:
519 return LowerGlobalAddress(Op, DAG);
520 case ISD::ExternalSymbol:
521 return LowerExternalSymbol(Op, DAG);
523 return LowerJumpTable(Op, DAG);
525 return LowerBR_JT(Op, DAG);
527 return LowerVASTART(Op, DAG);
531 SDValue WebAssemblyTargetLowering::LowerGlobalAddress(SDValue Op,
532 SelectionDAG &DAG) const {
534 const auto *GA = cast<GlobalAddressSDNode>(Op);
535 EVT VT = Op.getValueType();
536 assert(GA->getTargetFlags() == 0 && "WebAssembly doesn't set target flags");
537 if (GA->getAddressSpace() != 0)
538 fail(DL, DAG, "WebAssembly only expects the 0 address space");
539 return DAG.getNode(WebAssemblyISD::Wrapper, DL, VT,
540 DAG.getTargetGlobalAddress(GA->getGlobal(), DL, VT,
545 WebAssemblyTargetLowering::LowerExternalSymbol(SDValue Op,
546 SelectionDAG &DAG) const {
548 const auto *ES = cast<ExternalSymbolSDNode>(Op);
549 EVT VT = Op.getValueType();
550 assert(ES->getTargetFlags() == 0 && "WebAssembly doesn't set target flags");
551 return DAG.getNode(WebAssemblyISD::Wrapper, DL, VT,
552 DAG.getTargetExternalSymbol(ES->getSymbol(), VT));
555 SDValue WebAssemblyTargetLowering::LowerJumpTable(SDValue Op,
556 SelectionDAG &DAG) const {
557 // There's no need for a Wrapper node because we always incorporate a jump
558 // table operand into a TABLESWITCH instruction, rather than ever
559 // materializing it in a register.
560 const JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
561 return DAG.getTargetJumpTable(JT->getIndex(), Op.getValueType(),
562 JT->getTargetFlags());
565 SDValue WebAssemblyTargetLowering::LowerBR_JT(SDValue Op,
566 SelectionDAG &DAG) const {
568 SDValue Chain = Op.getOperand(0);
569 const auto *JT = cast<JumpTableSDNode>(Op.getOperand(1));
570 SDValue Index = Op.getOperand(2);
571 assert(JT->getTargetFlags() == 0 && "WebAssembly doesn't set target flags");
573 SmallVector<SDValue, 8> Ops;
574 Ops.push_back(Chain);
575 Ops.push_back(Index);
577 MachineJumpTableInfo *MJTI = DAG.getMachineFunction().getJumpTableInfo();
578 const auto &MBBs = MJTI->getJumpTables()[JT->getIndex()].MBBs;
580 // TODO: For now, we just pick something arbitrary for a default case for now.
581 // We really want to sniff out the guard and put in the real default case (and
582 // delete the guard).
583 Ops.push_back(DAG.getBasicBlock(MBBs[0]));
585 // Add an operand for each case.
586 for (auto MBB : MBBs)
587 Ops.push_back(DAG.getBasicBlock(MBB));
589 return DAG.getNode(WebAssemblyISD::TABLESWITCH, DL, MVT::Other, Ops);
592 SDValue WebAssemblyTargetLowering::LowerVASTART(SDValue Op,
593 SelectionDAG &DAG) const {
595 EVT PtrVT = getPointerTy(DAG.getMachineFunction().getDataLayout());
597 // The incoming non-fixed arguments are placed on the top of the stack, with
598 // natural alignment, at the point of the call, so the base pointer is just
599 // the current frame pointer.
600 DAG.getMachineFunction().getFrameInfo()->setFrameAddressIsTaken(true);
602 Subtarget->getRegisterInfo()->getFrameRegister(DAG.getMachineFunction());
603 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), DL, FP, PtrVT);
604 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
605 return DAG.getStore(Op.getOperand(0), DL, FrameAddr, Op.getOperand(1),
606 MachinePointerInfo(SV), false, false, 0);
609 //===----------------------------------------------------------------------===//
610 // WebAssembly Optimization Hooks
611 //===----------------------------------------------------------------------===//
613 MCSection *WebAssemblyTargetObjectFile::SelectSectionForGlobal(
614 const GlobalValue *GV, SectionKind /*Kind*/, Mangler & /*Mang*/,
615 const TargetMachine & /*TM*/) const {
616 // TODO: Be more sophisticated than this.
617 return isa<Function>(GV) ? getTextSection() : getDataSection();