1 //=- WebAssemblyISelLowering.cpp - WebAssembly DAG Lowering Implementation -==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief This file implements the WebAssemblyTargetLowering class.
13 //===----------------------------------------------------------------------===//
15 #include "WebAssemblyISelLowering.h"
16 #include "MCTargetDesc/WebAssemblyMCTargetDesc.h"
17 #include "WebAssemblyMachineFunctionInfo.h"
18 #include "WebAssemblySubtarget.h"
19 #include "WebAssemblyTargetMachine.h"
20 #include "WebAssemblyTargetObjectFile.h"
21 #include "llvm/CodeGen/Analysis.h"
22 #include "llvm/CodeGen/CallingConvLower.h"
23 #include "llvm/CodeGen/MachineJumpTableInfo.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 #include "llvm/CodeGen/SelectionDAG.h"
26 #include "llvm/IR/DiagnosticInfo.h"
27 #include "llvm/IR/DiagnosticPrinter.h"
28 #include "llvm/IR/Function.h"
29 #include "llvm/IR/Intrinsics.h"
30 #include "llvm/Support/CommandLine.h"
31 #include "llvm/Support/Debug.h"
32 #include "llvm/Support/ErrorHandling.h"
33 #include "llvm/Support/raw_ostream.h"
34 #include "llvm/Target/TargetOptions.h"
38 #define DEBUG_TYPE "wasm-lower"
41 // Diagnostic information for unimplemented or unsupported feature reporting.
42 // FIXME copied from BPF and AMDGPU.
43 class DiagnosticInfoUnsupported : public DiagnosticInfo {
45 // Debug location where this diagnostic is triggered.
47 const Twine &Description;
53 static int getKindID() {
55 KindID = llvm::getNextAvailablePluginDiagnosticKind();
60 DiagnosticInfoUnsupported(SDLoc DLoc, const Function &Fn, const Twine &Desc,
62 : DiagnosticInfo(getKindID(), DS_Error), DLoc(DLoc.getDebugLoc()),
63 Description(Desc), Fn(Fn), Value(Value) {}
65 void print(DiagnosticPrinter &DP) const override {
67 raw_string_ostream OS(Str);
70 auto DIL = DLoc.get();
71 StringRef Filename = DIL->getFilename();
72 unsigned Line = DIL->getLine();
73 unsigned Column = DIL->getColumn();
74 OS << Filename << ':' << Line << ':' << Column << ' ';
77 OS << "in function " << Fn.getName() << ' ' << *Fn.getFunctionType() << '\n'
86 static bool classof(const DiagnosticInfo *DI) {
87 return DI->getKind() == getKindID();
91 int DiagnosticInfoUnsupported::KindID = 0;
92 } // end anonymous namespace
94 WebAssemblyTargetLowering::WebAssemblyTargetLowering(
95 const TargetMachine &TM, const WebAssemblySubtarget &STI)
96 : TargetLowering(TM), Subtarget(&STI) {
97 auto MVTPtr = Subtarget->hasAddr64() ? MVT::i64 : MVT::i32;
99 // Booleans always contain 0 or 1.
100 setBooleanContents(ZeroOrOneBooleanContent);
101 // WebAssembly does not produce floating-point exceptions on normal floating
103 setHasFloatingPointExceptions(false);
104 // We don't know the microarchitecture here, so just reduce register pressure.
105 setSchedulingPreference(Sched::RegPressure);
106 // Tell ISel that we have a stack pointer.
107 setStackPointerRegisterToSaveRestore(
108 Subtarget->hasAddr64() ? WebAssembly::SP64 : WebAssembly::SP32);
109 // Set up the register classes.
110 addRegisterClass(MVT::i32, &WebAssembly::I32RegClass);
111 addRegisterClass(MVT::i64, &WebAssembly::I64RegClass);
112 addRegisterClass(MVT::f32, &WebAssembly::F32RegClass);
113 addRegisterClass(MVT::f64, &WebAssembly::F64RegClass);
114 // Compute derived properties from the register classes.
115 computeRegisterProperties(Subtarget->getRegisterInfo());
117 setOperationAction(ISD::GlobalAddress, MVTPtr, Custom);
118 setOperationAction(ISD::JumpTable, MVTPtr, Custom);
120 for (auto T : {MVT::f32, MVT::f64}) {
121 // Don't expand the floating-point types to constant pools.
122 setOperationAction(ISD::ConstantFP, T, Legal);
123 // Expand floating-point comparisons.
124 for (auto CC : {ISD::SETO, ISD::SETUO, ISD::SETUEQ, ISD::SETONE,
125 ISD::SETULT, ISD::SETULE, ISD::SETUGT, ISD::SETUGE})
126 setCondCodeAction(CC, T, Expand);
127 // Expand floating-point library function operators.
128 for (auto Op : {ISD::FSIN, ISD::FCOS, ISD::FSINCOS, ISD::FPOWI, ISD::FPOW})
129 setOperationAction(Op, T, Expand);
130 // Note supported floating-point library function operators that otherwise
131 // default to expand.
132 for (auto Op : {ISD::FCEIL, ISD::FFLOOR, ISD::FTRUNC, ISD::FNEARBYINT,
134 setOperationAction(Op, T, Legal);
135 // Support minnan and maxnan, which otherwise default to expand.
136 setOperationAction(ISD::FMINNAN, T, Legal);
137 setOperationAction(ISD::FMAXNAN, T, Legal);
140 for (auto T : {MVT::i32, MVT::i64}) {
141 // Expand unavailable integer operations.
142 for (auto Op : {ISD::BSWAP, ISD::ROTL, ISD::ROTR,
143 ISD::SMUL_LOHI, ISD::UMUL_LOHI,
144 ISD::MULHS, ISD::MULHU, ISD::SDIVREM, ISD::UDIVREM,
145 ISD::SHL_PARTS, ISD::SRA_PARTS, ISD::SRL_PARTS,
146 ISD::ADDC, ISD::ADDE, ISD::SUBC, ISD::SUBE}) {
147 setOperationAction(Op, T, Expand);
151 // As a special case, these operators use the type to mean the type to
153 for (auto T : {MVT::i1, MVT::i8, MVT::i16})
154 setOperationAction(ISD::SIGN_EXTEND_INREG, T, Expand);
156 // Dynamic stack allocation: use the default expansion.
157 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
158 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
159 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVTPtr, Expand);
161 // Expand these forms; we pattern-match the forms that we can handle in isel.
162 for (auto T : {MVT::i32, MVT::i64, MVT::f32, MVT::f64})
163 for (auto Op : {ISD::BR_CC, ISD::SELECT_CC})
164 setOperationAction(Op, T, Expand);
166 // We have custom switch handling.
167 setOperationAction(ISD::BR_JT, MVT::Other, Custom);
169 // WebAssembly doesn't have:
170 // - Floating-point extending loads.
171 // - Floating-point truncating stores.
172 // - i1 extending loads.
173 setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f64, Expand);
174 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
175 for (auto T : MVT::integer_valuetypes())
176 for (auto Ext : {ISD::EXTLOAD, ISD::ZEXTLOAD, ISD::SEXTLOAD})
177 setLoadExtAction(Ext, T, MVT::i1, Promote);
179 // Trap lowers to wasm unreachable
180 setOperationAction(ISD::TRAP, MVT::Other, Legal);
183 FastISel *WebAssemblyTargetLowering::createFastISel(
184 FunctionLoweringInfo &FuncInfo, const TargetLibraryInfo *LibInfo) const {
185 return WebAssembly::createFastISel(FuncInfo, LibInfo);
188 bool WebAssemblyTargetLowering::isOffsetFoldingLegal(
189 const GlobalAddressSDNode *GA) const {
190 // The WebAssembly target doesn't support folding offsets into global
195 MVT WebAssemblyTargetLowering::getScalarShiftAmountTy(const DataLayout &DL,
197 return VT.getSimpleVT();
201 WebAssemblyTargetLowering::getTargetNodeName(unsigned Opcode) const {
202 switch (static_cast<WebAssemblyISD::NodeType>(Opcode)) {
203 case WebAssemblyISD::FIRST_NUMBER:
205 #define HANDLE_NODETYPE(NODE) \
206 case WebAssemblyISD::NODE: \
207 return "WebAssemblyISD::" #NODE;
208 #include "WebAssemblyISD.def"
209 #undef HANDLE_NODETYPE
214 //===----------------------------------------------------------------------===//
215 // WebAssembly Lowering private implementation.
216 //===----------------------------------------------------------------------===//
218 //===----------------------------------------------------------------------===//
220 //===----------------------------------------------------------------------===//
222 static void fail(SDLoc DL, SelectionDAG &DAG, const char *msg) {
223 MachineFunction &MF = DAG.getMachineFunction();
224 DAG.getContext()->diagnose(
225 DiagnosticInfoUnsupported(DL, *MF.getFunction(), msg, SDValue()));
229 WebAssemblyTargetLowering::LowerCall(CallLoweringInfo &CLI,
230 SmallVectorImpl<SDValue> &InVals) const {
231 SelectionDAG &DAG = CLI.DAG;
233 SDValue Chain = CLI.Chain;
234 SDValue Callee = CLI.Callee;
235 MachineFunction &MF = DAG.getMachineFunction();
237 CallingConv::ID CallConv = CLI.CallConv;
238 if (CallConv != CallingConv::C &&
239 CallConv != CallingConv::Fast &&
240 CallConv != CallingConv::Cold)
242 "WebAssembly doesn't support language-specific or target-specific "
243 "calling conventions yet");
244 if (CLI.IsPatchPoint)
245 fail(DL, DAG, "WebAssembly doesn't support patch point yet");
247 // WebAssembly doesn't currently support explicit tail calls. If they are
248 // required, fail. Otherwise, just disable them.
249 if ((CallConv == CallingConv::Fast && CLI.IsTailCall &&
250 MF.getTarget().Options.GuaranteedTailCallOpt) ||
251 (CLI.CS && CLI.CS->isMustTailCall()))
252 fail(DL, DAG, "WebAssembly doesn't support tail call yet");
253 CLI.IsTailCall = false;
255 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
257 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
259 fail(DL, DAG, "WebAssembly doesn't support more than 1 returned value yet");
261 bool IsVarArg = CLI.IsVarArg;
263 fail(DL, DAG, "WebAssembly doesn't support varargs yet");
265 // Analyze operands of the call, assigning locations to each operand.
266 SmallVector<CCValAssign, 16> ArgLocs;
267 CCState CCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext());
268 unsigned NumBytes = CCInfo.getNextStackOffset();
270 auto PtrVT = getPointerTy(MF.getDataLayout());
271 auto Zero = DAG.getConstant(0, DL, PtrVT, true);
272 auto NB = DAG.getConstant(NumBytes, DL, PtrVT, true);
273 Chain = DAG.getCALLSEQ_START(Chain, NB, DL);
275 SmallVector<SDValue, 16> Ops;
276 Ops.push_back(Chain);
277 Ops.push_back(Callee);
278 Ops.append(OutVals.begin(), OutVals.end());
280 SmallVector<EVT, 8> Tys;
281 for (const auto &In : Ins)
282 Tys.push_back(In.VT);
283 Tys.push_back(MVT::Other);
284 SDVTList TyList = DAG.getVTList(Tys);
286 DAG.getNode(Ins.empty() ? WebAssemblyISD::CALL0 : WebAssemblyISD::CALL1,
291 InVals.push_back(Res);
292 Chain = Res.getValue(1);
295 // FIXME: handle CLI.RetSExt and CLI.RetZExt?
297 Chain = DAG.getCALLSEQ_END(Chain, NB, Zero, SDValue(), DL);
302 bool WebAssemblyTargetLowering::CanLowerReturn(
303 CallingConv::ID CallConv, MachineFunction &MF, bool IsVarArg,
304 const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const {
305 // WebAssembly can't currently handle returning tuples.
306 return Outs.size() <= 1;
309 SDValue WebAssemblyTargetLowering::LowerReturn(
310 SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
311 const SmallVectorImpl<ISD::OutputArg> &Outs,
312 const SmallVectorImpl<SDValue> &OutVals, SDLoc DL,
313 SelectionDAG &DAG) const {
314 MachineFunction &MF = DAG.getMachineFunction();
316 assert(Outs.size() <= 1 && "WebAssembly can only return up to one value");
317 if (CallConv != CallingConv::C)
318 fail(DL, DAG, "WebAssembly doesn't support non-C calling conventions");
320 fail(DL, DAG, "WebAssembly doesn't support varargs yet");
322 SmallVector<SDValue, 4> RetOps(1, Chain);
323 RetOps.append(OutVals.begin(), OutVals.end());
324 Chain = DAG.getNode(WebAssemblyISD::RETURN, DL, MVT::Other, RetOps);
326 // Record the number and types of the return values.
327 for (const ISD::OutputArg &Out : Outs) {
328 if (Out.Flags.isZExt())
329 fail(DL, DAG, "WebAssembly hasn't implemented zext results");
330 if (Out.Flags.isSExt())
331 fail(DL, DAG, "WebAssembly hasn't implemented sext results");
332 if (Out.Flags.isInReg())
333 fail(DL, DAG, "WebAssembly hasn't implemented inreg results");
334 if (Out.Flags.isSRet())
335 fail(DL, DAG, "WebAssembly hasn't implemented sret results");
336 if (Out.Flags.isByVal())
337 fail(DL, DAG, "WebAssembly hasn't implemented byval results");
338 if (Out.Flags.isInAlloca())
339 fail(DL, DAG, "WebAssembly hasn't implemented inalloca results");
340 if (Out.Flags.isNest())
341 fail(DL, DAG, "WebAssembly hasn't implemented nest results");
342 if (Out.Flags.isReturned())
343 fail(DL, DAG, "WebAssembly hasn't implemented returned results");
344 if (Out.Flags.isInConsecutiveRegs())
345 fail(DL, DAG, "WebAssembly hasn't implemented cons regs results");
346 if (Out.Flags.isInConsecutiveRegsLast())
347 fail(DL, DAG, "WebAssembly hasn't implemented cons regs last results");
349 fail(DL, DAG, "WebAssembly doesn't support non-fixed results yet");
350 MF.getInfo<WebAssemblyFunctionInfo>()->addResult(Out.VT);
356 SDValue WebAssemblyTargetLowering::LowerFormalArguments(
357 SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
358 const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc DL, SelectionDAG &DAG,
359 SmallVectorImpl<SDValue> &InVals) const {
360 MachineFunction &MF = DAG.getMachineFunction();
362 if (CallConv != CallingConv::C)
363 fail(DL, DAG, "WebAssembly doesn't support non-C calling conventions");
365 fail(DL, DAG, "WebAssembly doesn't support varargs yet");
368 for (const ISD::InputArg &In : Ins) {
369 if (In.Flags.isZExt())
370 fail(DL, DAG, "WebAssembly hasn't implemented zext arguments");
371 if (In.Flags.isSExt())
372 fail(DL, DAG, "WebAssembly hasn't implemented sext arguments");
373 if (In.Flags.isInReg())
374 fail(DL, DAG, "WebAssembly hasn't implemented inreg arguments");
375 if (In.Flags.isSRet())
376 fail(DL, DAG, "WebAssembly hasn't implemented sret arguments");
377 if (In.Flags.isByVal())
378 fail(DL, DAG, "WebAssembly hasn't implemented byval arguments");
379 if (In.Flags.isInAlloca())
380 fail(DL, DAG, "WebAssembly hasn't implemented inalloca arguments");
381 if (In.Flags.isNest())
382 fail(DL, DAG, "WebAssembly hasn't implemented nest arguments");
383 if (In.Flags.isReturned())
384 fail(DL, DAG, "WebAssembly hasn't implemented returned arguments");
385 if (In.Flags.isInConsecutiveRegs())
386 fail(DL, DAG, "WebAssembly hasn't implemented cons regs arguments");
387 if (In.Flags.isInConsecutiveRegsLast())
388 fail(DL, DAG, "WebAssembly hasn't implemented cons regs last arguments");
389 // FIXME Do something with In.getOrigAlign()?
392 ? DAG.getNode(WebAssemblyISD::ARGUMENT, DL, In.VT,
393 DAG.getTargetConstant(ArgNo, DL, MVT::i32))
394 : DAG.getNode(ISD::UNDEF, DL, In.VT));
396 // Record the number and types of arguments.
397 MF.getInfo<WebAssemblyFunctionInfo>()->addParam(In.VT);
404 //===----------------------------------------------------------------------===//
405 // Custom lowering hooks.
406 //===----------------------------------------------------------------------===//
408 SDValue WebAssemblyTargetLowering::LowerOperation(SDValue Op,
409 SelectionDAG &DAG) const {
410 switch (Op.getOpcode()) {
412 llvm_unreachable("unimplemented operation lowering");
414 case ISD::GlobalAddress:
415 return LowerGlobalAddress(Op, DAG);
417 return LowerJumpTable(Op, DAG);
419 return LowerBR_JT(Op, DAG);
423 SDValue WebAssemblyTargetLowering::LowerGlobalAddress(SDValue Op,
424 SelectionDAG &DAG) const {
426 const auto *GA = cast<GlobalAddressSDNode>(Op);
427 EVT VT = Op.getValueType();
428 assert(GA->getOffset() == 0 &&
429 "offsets on global addresses are forbidden by isOffsetFoldingLegal");
430 assert(GA->getTargetFlags() == 0 && "WebAssembly doesn't set target flags");
431 if (GA->getAddressSpace() != 0)
432 fail(DL, DAG, "WebAssembly only expects the 0 address space");
433 return DAG.getNode(WebAssemblyISD::Wrapper, DL, VT,
434 DAG.getTargetGlobalAddress(GA->getGlobal(), DL, VT));
437 SDValue WebAssemblyTargetLowering::LowerJumpTable(SDValue Op,
438 SelectionDAG &DAG) const {
439 // There's no need for a Wrapper node because we always incorporate a jump
440 // table operand into a SWITCH instruction, rather than ever materializing
442 const JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
443 return DAG.getTargetJumpTable(JT->getIndex(), Op.getValueType(),
444 JT->getTargetFlags());
447 SDValue WebAssemblyTargetLowering::LowerBR_JT(SDValue Op,
448 SelectionDAG &DAG) const {
450 SDValue Chain = Op.getOperand(0);
451 const auto *JT = cast<JumpTableSDNode>(Op.getOperand(1));
452 SDValue Index = Op.getOperand(2);
453 assert(JT->getTargetFlags() == 0 && "WebAssembly doesn't set target flags");
455 SmallVector<SDValue, 8> Ops;
456 Ops.push_back(Chain);
457 Ops.push_back(Index);
459 MachineJumpTableInfo *MJTI = DAG.getMachineFunction().getJumpTableInfo();
460 const auto &MBBs = MJTI->getJumpTables()[JT->getIndex()].MBBs;
462 // TODO: For now, we just pick something arbitrary for a default case for now.
463 // We really want to sniff out the guard and put in the real default case (and
464 // delete the guard).
465 Ops.push_back(DAG.getBasicBlock(MBBs[0]));
467 // Add an operand for each case.
468 for (auto MBB : MBBs)
469 Ops.push_back(DAG.getBasicBlock(MBB));
471 return DAG.getNode(WebAssemblyISD::SWITCH, DL, MVT::Other, Ops);
474 //===----------------------------------------------------------------------===//
475 // WebAssembly Optimization Hooks
476 //===----------------------------------------------------------------------===//
478 MCSection *WebAssemblyTargetObjectFile::SelectSectionForGlobal(
479 const GlobalValue *GV, SectionKind Kind, Mangler &Mang,
480 const TargetMachine &TM) const {
481 // TODO: Be more sophisticated than this.
482 return isa<Function>(GV) ? getTextSection() : getDataSection();