1 //=- WebAssemblyISelLowering.cpp - WebAssembly DAG Lowering Implementation -==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief This file implements the WebAssemblyTargetLowering class.
13 //===----------------------------------------------------------------------===//
15 #include "WebAssemblyISelLowering.h"
16 #include "MCTargetDesc/WebAssemblyMCTargetDesc.h"
17 #include "WebAssemblyMachineFunctionInfo.h"
18 #include "WebAssemblySubtarget.h"
19 #include "WebAssemblyTargetMachine.h"
20 #include "WebAssemblyTargetObjectFile.h"
21 #include "llvm/CodeGen/Analysis.h"
22 #include "llvm/CodeGen/MachineRegisterInfo.h"
23 #include "llvm/CodeGen/SelectionDAG.h"
24 #include "llvm/IR/DiagnosticInfo.h"
25 #include "llvm/IR/DiagnosticPrinter.h"
26 #include "llvm/IR/Function.h"
27 #include "llvm/IR/Intrinsics.h"
28 #include "llvm/Support/CommandLine.h"
29 #include "llvm/Support/Debug.h"
30 #include "llvm/Support/ErrorHandling.h"
31 #include "llvm/Support/raw_ostream.h"
32 #include "llvm/Target/TargetOptions.h"
36 #define DEBUG_TYPE "wasm-lower"
39 // Diagnostic information for unimplemented or unsupported feature reporting.
40 // FIXME copied from BPF and AMDGPU.
41 class DiagnosticInfoUnsupported : public DiagnosticInfo {
43 // Debug location where this diagnostic is triggered.
45 const Twine &Description;
51 static int getKindID() {
53 KindID = llvm::getNextAvailablePluginDiagnosticKind();
58 DiagnosticInfoUnsupported(SDLoc DLoc, const Function &Fn, const Twine &Desc,
60 : DiagnosticInfo(getKindID(), DS_Error), DLoc(DLoc.getDebugLoc()),
61 Description(Desc), Fn(Fn), Value(Value) {}
63 void print(DiagnosticPrinter &DP) const override {
65 raw_string_ostream OS(Str);
68 auto DIL = DLoc.get();
69 StringRef Filename = DIL->getFilename();
70 unsigned Line = DIL->getLine();
71 unsigned Column = DIL->getColumn();
72 OS << Filename << ':' << Line << ':' << Column << ' ';
75 OS << "in function " << Fn.getName() << ' ' << *Fn.getFunctionType() << '\n'
84 static bool classof(const DiagnosticInfo *DI) {
85 return DI->getKind() == getKindID();
89 int DiagnosticInfoUnsupported::KindID = 0;
90 } // end anonymous namespace
92 WebAssemblyTargetLowering::WebAssemblyTargetLowering(
93 const TargetMachine &TM, const WebAssemblySubtarget &STI)
94 : TargetLowering(TM), Subtarget(&STI) {
95 // Booleans always contain 0 or 1.
96 setBooleanContents(ZeroOrOneBooleanContent);
97 // WebAssembly does not produce floating-point exceptions on normal floating
99 setHasFloatingPointExceptions(false);
100 // We don't know the microarchitecture here, so just reduce register pressure.
101 setSchedulingPreference(Sched::RegPressure);
102 // Tell ISel that we have a stack pointer.
103 setStackPointerRegisterToSaveRestore(
104 Subtarget->hasAddr64() ? WebAssembly::SP64 : WebAssembly::SP32);
105 // Set up the register classes.
106 addRegisterClass(MVT::i32, &WebAssembly::Int32RegClass);
107 addRegisterClass(MVT::i64, &WebAssembly::Int64RegClass);
108 addRegisterClass(MVT::f32, &WebAssembly::Float32RegClass);
109 addRegisterClass(MVT::f64, &WebAssembly::Float64RegClass);
110 // Compute derived properties from the register classes.
111 computeRegisterProperties(Subtarget->getRegisterInfo());
113 // FIXME: many setOperationAction are missing...
115 for (auto T : {MVT::f32, MVT::f64}) {
116 // Don't expand the floating-point types to constant pools.
117 setOperationAction(ISD::ConstantFP, T, Legal);
118 // Expand floating-point comparisons.
119 for (auto CC : {ISD::SETO, ISD::SETUO, ISD::SETUEQ, ISD::SETONE,
120 ISD::SETULT, ISD::SETULE, ISD::SETUGT, ISD::SETUGE})
121 setCondCodeAction(CC, T, Expand);
122 // Expand floating-point library function operators.
123 for (auto Op : {ISD::FSIN, ISD::FCOS, ISD::FSINCOS, ISD::FPOWI, ISD::FPOW})
124 setOperationAction(Op, T, Expand);
125 // Note supported floating-point library function operators that otherwise
126 // default to expand.
127 for (auto Op : {ISD::FCEIL, ISD::FFLOOR, ISD::FTRUNC, ISD::FNEARBYINT,
129 setOperationAction(Op, T, Legal);
132 for (auto T : {MVT::i32, MVT::i64}) {
133 // Expand unavailable integer operations.
134 for (auto Op : {ISD::BSWAP, ISD::ROTL, ISD::ROTR,
135 ISD::SMUL_LOHI, ISD::UMUL_LOHI,
136 ISD::MULHS, ISD::MULHU, ISD::SDIVREM, ISD::UDIVREM,
137 ISD::SHL_PARTS, ISD::SRA_PARTS, ISD::SRL_PARTS,
138 ISD::ADDC, ISD::ADDE, ISD::SUBC, ISD::SUBE}) {
139 setOperationAction(Op, T, Expand);
143 // As a special case, these operators use the type to mean the type to
145 for (auto T : {MVT::i1, MVT::i8, MVT::i16})
146 setOperationAction(ISD::SIGN_EXTEND_INREG, T, Expand);
148 // Dynamic stack allocation: use the default expansion.
149 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
150 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
151 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
154 FastISel *WebAssemblyTargetLowering::createFastISel(
155 FunctionLoweringInfo &FuncInfo, const TargetLibraryInfo *LibInfo) const {
156 return WebAssembly::createFastISel(FuncInfo, LibInfo);
159 MVT WebAssemblyTargetLowering::getScalarShiftAmountTy(const DataLayout &DL,
161 return VT.getSimpleVT();
165 WebAssemblyTargetLowering::getTargetNodeName(unsigned Opcode) const {
166 switch (static_cast<WebAssemblyISD::NodeType>(Opcode)) {
167 case WebAssemblyISD::FIRST_NUMBER: break;
168 case WebAssemblyISD::RETURN: return "WebAssemblyISD::RETURN";
169 case WebAssemblyISD::ARGUMENT: return "WebAssemblyISD::ARGUMENT";
174 //===----------------------------------------------------------------------===//
175 // WebAssembly Lowering private implementation.
176 //===----------------------------------------------------------------------===//
178 //===----------------------------------------------------------------------===//
180 //===----------------------------------------------------------------------===//
182 static void fail(SDLoc DL, SelectionDAG &DAG, const char *msg) {
183 MachineFunction &MF = DAG.getMachineFunction();
184 DAG.getContext()->diagnose(
185 DiagnosticInfoUnsupported(DL, *MF.getFunction(), msg, SDValue()));
188 bool WebAssemblyTargetLowering::CanLowerReturn(
189 CallingConv::ID CallConv, MachineFunction &MF, bool IsVarArg,
190 const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const {
191 // WebAssembly can't currently handle returning tuples.
192 return Outs.size() <= 1;
195 SDValue WebAssemblyTargetLowering::LowerReturn(
196 SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
197 const SmallVectorImpl<ISD::OutputArg> &Outs,
198 const SmallVectorImpl<SDValue> &OutVals, SDLoc DL,
199 SelectionDAG &DAG) const {
201 assert(Outs.size() <= 1 && "WebAssembly can only return up to one value");
202 if (CallConv != CallingConv::C)
203 fail(DL, DAG, "WebAssembly doesn't support non-C calling conventions");
205 fail(DL, DAG, "WebAssembly doesn't support varargs yet");
207 SmallVector<SDValue, 4> RetOps(1, Chain);
208 RetOps.append(OutVals.begin(), OutVals.end());
209 Chain = DAG.getNode(WebAssemblyISD::RETURN, DL, MVT::Other, RetOps);
214 SDValue WebAssemblyTargetLowering::LowerFormalArguments(
215 SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
216 const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc DL, SelectionDAG &DAG,
217 SmallVectorImpl<SDValue> &InVals) const {
218 MachineFunction &MF = DAG.getMachineFunction();
220 if (CallConv != CallingConv::C)
221 fail(DL, DAG, "WebAssembly doesn't support non-C calling conventions");
223 fail(DL, DAG, "WebAssembly doesn't support varargs yet");
224 if (MF.getFunction()->hasStructRetAttr())
225 fail(DL, DAG, "WebAssembly doesn't support struct return yet");
228 for (const ISD::InputArg &In : Ins) {
229 if (In.Flags.isZExt())
230 fail(DL, DAG, "WebAssembly hasn't implemented zext arguments");
231 if (In.Flags.isSExt())
232 fail(DL, DAG, "WebAssembly hasn't implemented sext arguments");
233 if (In.Flags.isInReg())
234 fail(DL, DAG, "WebAssembly hasn't implemented inreg arguments");
235 if (In.Flags.isSRet())
236 fail(DL, DAG, "WebAssembly hasn't implemented sret arguments");
237 if (In.Flags.isByVal())
238 fail(DL, DAG, "WebAssembly hasn't implemented byval arguments");
239 if (In.Flags.isInAlloca())
240 fail(DL, DAG, "WebAssembly hasn't implemented inalloca arguments");
241 if (In.Flags.isNest())
242 fail(DL, DAG, "WebAssembly hasn't implemented nest arguments");
243 if (In.Flags.isReturned())
244 fail(DL, DAG, "WebAssembly hasn't implemented returned arguments");
245 if (In.Flags.isInConsecutiveRegs())
246 fail(DL, DAG, "WebAssembly hasn't implemented cons regs arguments");
247 if (In.Flags.isInConsecutiveRegsLast())
248 fail(DL, DAG, "WebAssembly hasn't implemented cons regs last arguments");
249 if (In.Flags.isSplit())
250 fail(DL, DAG, "WebAssembly hasn't implemented split arguments");
251 // FIXME Do something with In.getOrigAlign()?
254 ? DAG.getNode(WebAssemblyISD::ARGUMENT, DL, In.VT,
255 DAG.getTargetConstant(ArgNo, DL, MVT::i32))
256 : DAG.getNode(ISD::UNDEF, DL, In.VT));
263 //===----------------------------------------------------------------------===//
264 // Other Lowering Code
265 //===----------------------------------------------------------------------===//
267 //===----------------------------------------------------------------------===//
268 // WebAssembly Optimization Hooks
269 //===----------------------------------------------------------------------===//
271 MCSection *WebAssemblyTargetObjectFile::SelectSectionForGlobal(
272 const GlobalValue *GV, SectionKind Kind, Mangler &Mang,
273 const TargetMachine &TM) const {
274 return getDataSection();