1 //===-- WebAssemblyInstrInfo.cpp - WebAssembly Instruction Information ----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief This file contains the WebAssembly implementation of the
12 /// TargetInstrInfo class.
14 //===----------------------------------------------------------------------===//
16 #include "WebAssemblyInstrInfo.h"
17 #include "MCTargetDesc/WebAssemblyMCTargetDesc.h"
18 #include "WebAssemblySubtarget.h"
19 #include "llvm/CodeGen/MachineFrameInfo.h"
20 #include "llvm/CodeGen/MachineInstrBuilder.h"
21 #include "llvm/CodeGen/MachineMemOperand.h"
22 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 #define DEBUG_TYPE "wasm-instr-info"
27 #define GET_INSTRINFO_CTOR_DTOR
28 #include "WebAssemblyGenInstrInfo.inc"
30 WebAssemblyInstrInfo::WebAssemblyInstrInfo(const WebAssemblySubtarget &STI)
31 : WebAssemblyGenInstrInfo(WebAssembly::ADJCALLSTACKDOWN,
32 WebAssembly::ADJCALLSTACKUP),
33 RI(STI.getTargetTriple()) {}
35 void WebAssemblyInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
36 MachineBasicBlock::iterator I,
37 DebugLoc DL, unsigned DestReg,
38 unsigned SrcReg, bool KillSrc) const {
39 const TargetRegisterClass *RC =
40 MBB.getParent()->getRegInfo().getRegClass(SrcReg);
42 unsigned CopyLocalOpcode;
43 if (RC == &WebAssembly::I32RegClass)
44 CopyLocalOpcode = WebAssembly::COPY_LOCAL_I32;
45 else if (RC == &WebAssembly::I64RegClass)
46 CopyLocalOpcode = WebAssembly::COPY_LOCAL_I64;
47 else if (RC == &WebAssembly::F32RegClass)
48 CopyLocalOpcode = WebAssembly::COPY_LOCAL_F32;
49 else if (RC == &WebAssembly::F64RegClass)
50 CopyLocalOpcode = WebAssembly::COPY_LOCAL_F64;
52 llvm_unreachable("Unexpected register class");
54 BuildMI(MBB, I, DL, get(CopyLocalOpcode), DestReg)
55 .addReg(SrcReg, KillSrc ? RegState::Kill : 0);
59 bool WebAssemblyInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
60 MachineBasicBlock *&TBB,
61 MachineBasicBlock *&FBB,
62 SmallVectorImpl<MachineOperand> &Cond,
63 bool /*AllowModify*/) const {
64 bool HaveCond = false;
65 for (MachineInstr &MI : iterator_range<MachineBasicBlock::instr_iterator>(
66 MBB.getFirstInstrTerminator(), MBB.instr_end())) {
67 switch (MI.getOpcode()) {
69 // Unhandled instruction; bail out.
71 case WebAssembly::BR_IF:
74 Cond.push_back(MachineOperand::CreateImm(true));
75 Cond.push_back(MI.getOperand(0));
76 TBB = MI.getOperand(1).getMBB();
79 case WebAssembly::BR_UNLESS:
82 Cond.push_back(MachineOperand::CreateImm(false));
83 Cond.push_back(MI.getOperand(0));
84 TBB = MI.getOperand(1).getMBB();
89 TBB = MI.getOperand(0).getMBB();
91 FBB = MI.getOperand(0).getMBB();
101 unsigned WebAssemblyInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
102 MachineBasicBlock::instr_iterator I = MBB.instr_end();
105 while (I != MBB.instr_begin()) {
107 if (I->isDebugValue())
109 if (!I->isTerminator())
111 // Remove the branch.
112 I->eraseFromParent();
120 unsigned WebAssemblyInstrInfo::InsertBranch(MachineBasicBlock &MBB,
121 MachineBasicBlock *TBB,
122 MachineBasicBlock *FBB,
123 ArrayRef<MachineOperand> Cond,
129 BuildMI(&MBB, DL, get(WebAssembly::BR)).addMBB(TBB);
133 assert(Cond.size() == 2 && "Expected a flag and a successor block");
135 if (Cond[0].getImm()) {
136 BuildMI(&MBB, DL, get(WebAssembly::BR_IF))
140 BuildMI(&MBB, DL, get(WebAssembly::BR_UNLESS))
147 BuildMI(&MBB, DL, get(WebAssembly::BR)).addMBB(FBB);
151 bool WebAssemblyInstrInfo::ReverseBranchCondition(
152 SmallVectorImpl<MachineOperand> &Cond) const {
153 assert(Cond.size() == 2 && "Expected a flag and a successor block");
154 Cond.front() = MachineOperand::CreateImm(!Cond.front().getImm());