1 //===-- WebAssemblyPeephole.cpp - WebAssembly Peephole Optimiztions -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief Late peephole optimizations for WebAssembly.
13 //===----------------------------------------------------------------------===//
15 #include "WebAssembly.h"
16 #include "MCTargetDesc/WebAssemblyMCTargetDesc.h"
17 #include "WebAssemblyMachineFunctionInfo.h"
18 #include "llvm/CodeGen/MachineFunctionPass.h"
21 #define DEBUG_TYPE "wasm-peephole"
24 class WebAssemblyPeephole final : public MachineFunctionPass {
25 const char *getPassName() const override {
26 return "WebAssembly late peephole optimizer";
29 void getAnalysisUsage(AnalysisUsage &AU) const override {
31 MachineFunctionPass::getAnalysisUsage(AU);
34 bool runOnMachineFunction(MachineFunction &MF) override;
38 WebAssemblyPeephole() : MachineFunctionPass(ID) {}
40 } // end anonymous namespace
42 char WebAssemblyPeephole::ID = 0;
43 FunctionPass *llvm::createWebAssemblyPeephole() {
44 return new WebAssemblyPeephole();
47 bool WebAssemblyPeephole::runOnMachineFunction(MachineFunction &MF) {
50 MachineRegisterInfo &MRI = MF.getRegInfo();
51 WebAssemblyFunctionInfo &MFI = *MF.getInfo<WebAssemblyFunctionInfo>();
55 switch (MI.getOpcode()) {
58 case WebAssembly::STORE8_I32:
59 case WebAssembly::STORE16_I32:
60 case WebAssembly::STORE8_I64:
61 case WebAssembly::STORE16_I64:
62 case WebAssembly::STORE32_I64:
63 case WebAssembly::STORE_F32:
64 case WebAssembly::STORE_F64:
65 case WebAssembly::STORE_I32:
66 case WebAssembly::STORE_I64: {
67 // Store instructions return their value operand. If we ended up using
68 // the same register for both, replace it with a dead def so that it
69 // can use $discard instead.
70 MachineOperand &MO = MI.getOperand(0);
71 unsigned OldReg = MO.getReg();
72 // TODO: Handle SP/physregs
73 if (OldReg == MI.getOperand(3).getReg()
74 && TargetRegisterInfo::isVirtualRegister(MI.getOperand(3).getReg())) {
76 unsigned NewReg = MRI.createVirtualRegister(MRI.getRegClass(OldReg));
79 MFI.stackifyVReg(NewReg);
80 MFI.addWAReg(NewReg, WebAssemblyFunctionInfo::UnusedReg);