1 //WebAssemblyRegisterInfo.td-Describe the WebAssembly Registers -*- tablegen -*-
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief This file describes the WebAssembly register classes and some nominal
12 /// physical registers.
14 //===----------------------------------------------------------------------===//
16 class WebAssemblyReg<string n> : Register<n> {
17 let Namespace = "WebAssembly";
20 class WebAssemblyRegClass<list<ValueType> regTypes, int alignment, dag regList>
21 : RegisterClass<"WebAssembly", regTypes, alignment, regList>;
23 //===----------------------------------------------------------------------===//
25 //===----------------------------------------------------------------------===//
27 // Special registers used as the frame and stack pointer.
29 // WebAssembly may someday supports mixed 32-bit and 64-bit heaps in the same
30 // application, which requires separate width FP and SP.
31 def FP32 : WebAssemblyReg<"%FP32">;
32 def FP64 : WebAssemblyReg<"%FP64">;
33 def SP32 : WebAssemblyReg<"%SP32">;
34 def SP64 : WebAssemblyReg<"%SP64">;
36 // TODO(jfb) The following comes from NVPTX. Is it really needed, or can we do
37 // away with it? Try deleting once the backend works.
38 // WebAssembly uses virtual registers, but the backend defines a few physical
39 // registers here to keep SDAG and the MachineInstr layers happy.
41 def I#i : WebAssemblyReg<"%i."#i>; // i32
42 def L#i : WebAssemblyReg<"%l."#i>; // i64
43 def F#i : WebAssemblyReg<"%f."#i>; // f32
44 def D#i : WebAssemblyReg<"%d."#i>; // f64
47 //===----------------------------------------------------------------------===//
49 //===----------------------------------------------------------------------===//
51 def I32 : WebAssemblyRegClass<[i32], 32, (add (sequence "I%u", 0, 4), SP32)>;
52 def I64 : WebAssemblyRegClass<[i64], 64, (add (sequence "L%u", 0, 4), SP64)>;
53 def F32 : WebAssemblyRegClass<[f32], 32, (add (sequence "F%u", 0, 4))>;
54 def F64 : WebAssemblyRegClass<[f64], 64, (add (sequence "D%u", 0, 4))>;