1 //===-- X86AsmInstrumentation.cpp - Instrument X86 inline assembly C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "MCTargetDesc/X86BaseInfo.h"
11 #include "X86AsmInstrumentation.h"
12 #include "X86Operand.h"
13 #include "llvm/ADT/StringExtras.h"
14 #include "llvm/ADT/Triple.h"
15 #include "llvm/IR/Function.h"
16 #include "llvm/MC/MCContext.h"
17 #include "llvm/MC/MCInst.h"
18 #include "llvm/MC/MCInstBuilder.h"
19 #include "llvm/MC/MCInstrInfo.h"
20 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
21 #include "llvm/MC/MCStreamer.h"
22 #include "llvm/MC/MCSubtargetInfo.h"
23 #include "llvm/MC/MCTargetAsmParser.h"
24 #include "llvm/MC/MCTargetOptions.h"
25 #include "llvm/Support/CommandLine.h"
30 static cl::opt<bool> ClAsanInstrumentAssembly(
31 "asan-instrument-assembly",
32 cl::desc("instrument assembly with AddressSanitizer checks"), cl::Hidden,
35 bool IsStackReg(unsigned Reg) {
36 return Reg == X86::RSP || Reg == X86::ESP || Reg == X86::SP;
39 std::string FuncName(unsigned AccessSize, bool IsWrite) {
40 return std::string("__asan_report_") + (IsWrite ? "store" : "load") +
44 class X86AddressSanitizer : public X86AsmInstrumentation {
46 X86AddressSanitizer(const MCSubtargetInfo &STI)
47 : X86AsmInstrumentation(STI), RepPrefix(false) {}
48 virtual ~X86AddressSanitizer() {}
50 // X86AsmInstrumentation implementation:
51 virtual void InstrumentAndEmitInstruction(const MCInst &Inst,
52 OperandVector &Operands,
54 const MCInstrInfo &MII,
55 MCStreamer &Out) override {
56 InstrumentMOVS(Inst, Operands, Ctx, MII, Out);
58 EmitInstruction(Out, MCInstBuilder(X86::REP_PREFIX));
60 InstrumentMOV(Inst, Operands, Ctx, MII, Out);
62 RepPrefix = (Inst.getOpcode() == X86::REP_PREFIX);
64 EmitInstruction(Out, Inst);
67 // Should be implemented differently in x86_32 and x86_64 subclasses.
68 virtual void InstrumentMemOperandSmallImpl(X86Operand &Op,
69 unsigned AccessSize, bool IsWrite,
72 virtual void InstrumentMemOperandLargeImpl(X86Operand &Op,
73 unsigned AccessSize, bool IsWrite,
76 virtual void InstrumentMOVSImpl(unsigned AccessSize, MCContext &Ctx,
79 void InstrumentMemOperand(MCParsedAsmOperand &Op, unsigned AccessSize,
80 bool IsWrite, MCContext &Ctx, MCStreamer &Out);
81 void InstrumentMOVSBase(unsigned DstReg, unsigned SrcReg, unsigned CntReg,
82 unsigned AccessSize, MCContext &Ctx, MCStreamer &Out);
83 void InstrumentMOVS(const MCInst &Inst, OperandVector &Operands,
84 MCContext &Ctx, const MCInstrInfo &MII, MCStreamer &Out);
85 void InstrumentMOV(const MCInst &Inst, OperandVector &Operands,
86 MCContext &Ctx, const MCInstrInfo &MII, MCStreamer &Out);
88 void EmitLabel(MCStreamer &Out, MCSymbol *Label) { Out.EmitLabel(Label); }
91 // True when previous instruction was actually REP prefix.
95 void X86AddressSanitizer::InstrumentMemOperand(MCParsedAsmOperand &Op,
97 bool IsWrite, MCContext &Ctx,
99 assert(Op.isMem() && "Op should be a memory operand.");
100 assert((AccessSize & (AccessSize - 1)) == 0 && AccessSize <= 16 &&
101 "AccessSize should be a power of two, less or equal than 16.");
103 X86Operand &MemOp = static_cast<X86Operand &>(Op);
104 // FIXME: get rid of this limitation.
105 if (IsStackReg(MemOp.getMemBaseReg()) || IsStackReg(MemOp.getMemIndexReg()))
108 // FIXME: take into account load/store alignment.
110 InstrumentMemOperandSmallImpl(MemOp, AccessSize, IsWrite, Ctx, Out);
112 InstrumentMemOperandLargeImpl(MemOp, AccessSize, IsWrite, Ctx, Out);
115 void X86AddressSanitizer::InstrumentMOVSBase(unsigned DstReg, unsigned SrcReg,
118 MCContext &Ctx, MCStreamer &Out) {
119 // FIXME: check whole ranges [DstReg .. DstReg + AccessSize * (CntReg - 1)]
120 // and [SrcReg .. SrcReg + AccessSize * (CntReg - 1)].
122 // FIXME: extract prolog and epilogue from InstrumentMemOperand()
123 // and optimize this sequence of InstrumentMemOperand() calls.
127 const MCExpr *Disp = MCConstantExpr::Create(0, Ctx);
128 std::unique_ptr<X86Operand> Op(X86Operand::CreateMem(
129 0, Disp, SrcReg, 0, AccessSize, SMLoc(), SMLoc()));
130 InstrumentMemOperand(*Op, AccessSize, false /* IsWrite */, Ctx, Out);
133 // Test -1(%SrcReg, %CntReg, AccessSize)
135 const MCExpr *Disp = MCConstantExpr::Create(-1, Ctx);
136 std::unique_ptr<X86Operand> Op(X86Operand::CreateMem(
137 0, Disp, SrcReg, CntReg, AccessSize, SMLoc(), SMLoc()));
138 InstrumentMemOperand(*Op, AccessSize, false /* IsWrite */, Ctx, Out);
143 const MCExpr *Disp = MCConstantExpr::Create(0, Ctx);
144 std::unique_ptr<X86Operand> Op(X86Operand::CreateMem(
145 0, Disp, DstReg, 0, AccessSize, SMLoc(), SMLoc()));
146 InstrumentMemOperand(*Op, AccessSize, true /* IsWrite */, Ctx, Out);
149 // Test -1(%DstReg, %CntReg, AccessSize)
151 const MCExpr *Disp = MCConstantExpr::Create(-1, Ctx);
152 std::unique_ptr<X86Operand> Op(X86Operand::CreateMem(
153 0, Disp, DstReg, CntReg, AccessSize, SMLoc(), SMLoc()));
154 InstrumentMemOperand(*Op, AccessSize, true /* IsWrite */, Ctx, Out);
158 void X86AddressSanitizer::InstrumentMOVS(const MCInst &Inst,
159 OperandVector &Operands,
160 MCContext &Ctx, const MCInstrInfo &MII,
162 // Access size in bytes.
163 unsigned AccessSize = 0;
165 switch (Inst.getOpcode()) {
182 InstrumentMOVSImpl(AccessSize, Ctx, Out);
185 void X86AddressSanitizer::InstrumentMOV(const MCInst &Inst,
186 OperandVector &Operands, MCContext &Ctx,
187 const MCInstrInfo &MII,
189 // Access size in bytes.
190 unsigned AccessSize = 0;
192 switch (Inst.getOpcode()) {
223 const bool IsWrite = MII.get(Inst.getOpcode()).mayStore();
224 for (unsigned Ix = 0; Ix < Operands.size(); ++Ix) {
225 assert(Operands[Ix]);
226 MCParsedAsmOperand &Op = *Operands[Ix];
228 InstrumentMemOperand(Op, AccessSize, IsWrite, Ctx, Out);
232 class X86AddressSanitizer32 : public X86AddressSanitizer {
234 static const long kShadowOffset = 0x20000000;
236 X86AddressSanitizer32(const MCSubtargetInfo &STI)
237 : X86AddressSanitizer(STI) {}
238 virtual ~X86AddressSanitizer32() {}
240 virtual void InstrumentMemOperandSmallImpl(X86Operand &Op,
241 unsigned AccessSize, bool IsWrite,
243 MCStreamer &Out) override;
244 virtual void InstrumentMemOperandLargeImpl(X86Operand &Op,
245 unsigned AccessSize, bool IsWrite,
247 MCStreamer &Out) override;
248 virtual void InstrumentMOVSImpl(unsigned AccessSize, MCContext &Ctx,
249 MCStreamer &Out) override;
252 void EmitCallAsanReport(MCContext &Ctx, MCStreamer &Out, unsigned AccessSize,
253 bool IsWrite, unsigned AddressReg) {
254 EmitInstruction(Out, MCInstBuilder(X86::CLD));
255 EmitInstruction(Out, MCInstBuilder(X86::MMX_EMMS));
257 EmitInstruction(Out, MCInstBuilder(X86::AND64ri8)
261 EmitInstruction(Out, MCInstBuilder(X86::PUSH32r).addReg(AddressReg));
263 const std::string &Fn = FuncName(AccessSize, IsWrite);
264 MCSymbol *FnSym = Ctx.GetOrCreateSymbol(StringRef(Fn));
265 const MCSymbolRefExpr *FnExpr =
266 MCSymbolRefExpr::Create(FnSym, MCSymbolRefExpr::VK_PLT, Ctx);
267 EmitInstruction(Out, MCInstBuilder(X86::CALLpcrel32).addExpr(FnExpr));
271 void X86AddressSanitizer32::InstrumentMemOperandSmallImpl(X86Operand &Op,
276 EmitInstruction(Out, MCInstBuilder(X86::PUSH32r).addReg(X86::EAX));
277 EmitInstruction(Out, MCInstBuilder(X86::PUSH32r).addReg(X86::ECX));
278 EmitInstruction(Out, MCInstBuilder(X86::PUSH32r).addReg(X86::EDX));
279 EmitInstruction(Out, MCInstBuilder(X86::PUSHF32));
283 Inst.setOpcode(X86::LEA32r);
284 Inst.addOperand(MCOperand::CreateReg(X86::EAX));
285 Op.addMemOperands(Inst, 5);
286 EmitInstruction(Out, Inst);
290 Out, MCInstBuilder(X86::MOV32rr).addReg(X86::ECX).addReg(X86::EAX));
293 MCInstBuilder(X86::SHR32ri).addReg(X86::ECX).addReg(X86::ECX).addImm(3));
297 Inst.setOpcode(X86::MOV8rm);
298 Inst.addOperand(MCOperand::CreateReg(X86::CL));
299 const MCExpr *Disp = MCConstantExpr::Create(kShadowOffset, Ctx);
300 std::unique_ptr<X86Operand> Op(
301 X86Operand::CreateMem(0, Disp, X86::ECX, 0, 1, SMLoc(), SMLoc()));
302 Op->addMemOperands(Inst, 5);
303 EmitInstruction(Out, Inst);
307 MCInstBuilder(X86::TEST8rr).addReg(X86::CL).addReg(X86::CL));
308 MCSymbol *DoneSym = Ctx.CreateTempSymbol();
309 const MCExpr *DoneExpr = MCSymbolRefExpr::Create(DoneSym, Ctx);
310 EmitInstruction(Out, MCInstBuilder(X86::JE_4).addExpr(DoneExpr));
313 Out, MCInstBuilder(X86::MOV32rr).addReg(X86::EDX).addReg(X86::EAX));
316 MCInstBuilder(X86::AND32ri).addReg(X86::EDX).addReg(X86::EDX).addImm(7));
318 switch (AccessSize) {
323 Inst.setOpcode(X86::LEA32r);
324 Inst.addOperand(MCOperand::CreateReg(X86::EDX));
326 const MCExpr *Disp = MCConstantExpr::Create(1, Ctx);
327 std::unique_ptr<X86Operand> Op(
328 X86Operand::CreateMem(0, Disp, X86::EDX, 0, 1, SMLoc(), SMLoc()));
329 Op->addMemOperands(Inst, 5);
330 EmitInstruction(Out, Inst);
334 EmitInstruction(Out, MCInstBuilder(X86::ADD32ri8)
340 assert(false && "Incorrect access size");
345 Out, MCInstBuilder(X86::MOVSX32rr8).addReg(X86::ECX).addReg(X86::CL));
347 Out, MCInstBuilder(X86::CMP32rr).addReg(X86::EDX).addReg(X86::ECX));
348 EmitInstruction(Out, MCInstBuilder(X86::JL_4).addExpr(DoneExpr));
350 EmitCallAsanReport(Ctx, Out, AccessSize, IsWrite, X86::EAX);
351 EmitLabel(Out, DoneSym);
353 EmitInstruction(Out, MCInstBuilder(X86::POPF32));
354 EmitInstruction(Out, MCInstBuilder(X86::POP32r).addReg(X86::EDX));
355 EmitInstruction(Out, MCInstBuilder(X86::POP32r).addReg(X86::ECX));
356 EmitInstruction(Out, MCInstBuilder(X86::POP32r).addReg(X86::EAX));
359 void X86AddressSanitizer32::InstrumentMemOperandLargeImpl(X86Operand &Op,
364 EmitInstruction(Out, MCInstBuilder(X86::PUSH32r).addReg(X86::EAX));
365 EmitInstruction(Out, MCInstBuilder(X86::PUSH32r).addReg(X86::ECX));
366 EmitInstruction(Out, MCInstBuilder(X86::PUSHF32));
370 Inst.setOpcode(X86::LEA32r);
371 Inst.addOperand(MCOperand::CreateReg(X86::EAX));
372 Op.addMemOperands(Inst, 5);
373 EmitInstruction(Out, Inst);
376 Out, MCInstBuilder(X86::MOV32rr).addReg(X86::ECX).addReg(X86::EAX));
379 MCInstBuilder(X86::SHR32ri).addReg(X86::ECX).addReg(X86::ECX).addImm(3));
382 switch (AccessSize) {
384 Inst.setOpcode(X86::CMP8mi);
387 Inst.setOpcode(X86::CMP16mi);
390 assert(false && "Incorrect access size");
393 const MCExpr *Disp = MCConstantExpr::Create(kShadowOffset, Ctx);
394 std::unique_ptr<X86Operand> Op(
395 X86Operand::CreateMem(0, Disp, X86::ECX, 0, 1, SMLoc(), SMLoc()));
396 Op->addMemOperands(Inst, 5);
397 Inst.addOperand(MCOperand::CreateImm(0));
398 EmitInstruction(Out, Inst);
400 MCSymbol *DoneSym = Ctx.CreateTempSymbol();
401 const MCExpr *DoneExpr = MCSymbolRefExpr::Create(DoneSym, Ctx);
402 EmitInstruction(Out, MCInstBuilder(X86::JE_4).addExpr(DoneExpr));
404 EmitCallAsanReport(Ctx, Out, AccessSize, IsWrite, X86::EAX);
405 EmitLabel(Out, DoneSym);
407 EmitInstruction(Out, MCInstBuilder(X86::POPF32));
408 EmitInstruction(Out, MCInstBuilder(X86::POP32r).addReg(X86::ECX));
409 EmitInstruction(Out, MCInstBuilder(X86::POP32r).addReg(X86::EAX));
412 void X86AddressSanitizer32::InstrumentMOVSImpl(unsigned AccessSize,
415 EmitInstruction(Out, MCInstBuilder(X86::PUSHF32));
417 // No need to test when ECX is equals to zero.
418 MCSymbol *DoneSym = Ctx.CreateTempSymbol();
419 const MCExpr *DoneExpr = MCSymbolRefExpr::Create(DoneSym, Ctx);
421 Out, MCInstBuilder(X86::TEST32rr).addReg(X86::ECX).addReg(X86::ECX));
422 EmitInstruction(Out, MCInstBuilder(X86::JE_4).addExpr(DoneExpr));
424 // Instrument first and last elements in src and dst range.
425 InstrumentMOVSBase(X86::EDI /* DstReg */, X86::ESI /* SrcReg */,
426 X86::ECX /* CntReg */, AccessSize, Ctx, Out);
428 EmitLabel(Out, DoneSym);
429 EmitInstruction(Out, MCInstBuilder(X86::POPF32));
432 class X86AddressSanitizer64 : public X86AddressSanitizer {
434 static const long kShadowOffset = 0x7fff8000;
436 X86AddressSanitizer64(const MCSubtargetInfo &STI)
437 : X86AddressSanitizer(STI) {}
438 virtual ~X86AddressSanitizer64() {}
440 virtual void InstrumentMemOperandSmallImpl(X86Operand &Op,
441 unsigned AccessSize, bool IsWrite,
443 MCStreamer &Out) override;
444 virtual void InstrumentMemOperandLargeImpl(X86Operand &Op,
445 unsigned AccessSize, bool IsWrite,
447 MCStreamer &Out) override;
448 virtual void InstrumentMOVSImpl(unsigned AccessSize, MCContext &Ctx,
449 MCStreamer &Out) override;
452 void EmitAdjustRSP(MCContext &Ctx, MCStreamer &Out, long Offset) {
454 Inst.setOpcode(X86::LEA64r);
455 Inst.addOperand(MCOperand::CreateReg(X86::RSP));
457 const MCExpr *Disp = MCConstantExpr::Create(Offset, Ctx);
458 std::unique_ptr<X86Operand> Op(
459 X86Operand::CreateMem(0, Disp, X86::RSP, 0, 1, SMLoc(), SMLoc()));
460 Op->addMemOperands(Inst, 5);
461 EmitInstruction(Out, Inst);
464 void EmitCallAsanReport(MCContext &Ctx, MCStreamer &Out, unsigned AccessSize,
466 EmitInstruction(Out, MCInstBuilder(X86::CLD));
467 EmitInstruction(Out, MCInstBuilder(X86::MMX_EMMS));
469 EmitInstruction(Out, MCInstBuilder(X86::AND64ri8)
474 const std::string &Fn = FuncName(AccessSize, IsWrite);
475 MCSymbol *FnSym = Ctx.GetOrCreateSymbol(StringRef(Fn));
476 const MCSymbolRefExpr *FnExpr =
477 MCSymbolRefExpr::Create(FnSym, MCSymbolRefExpr::VK_PLT, Ctx);
478 EmitInstruction(Out, MCInstBuilder(X86::CALL64pcrel32).addExpr(FnExpr));
482 void X86AddressSanitizer64::InstrumentMemOperandSmallImpl(X86Operand &Op,
487 EmitAdjustRSP(Ctx, Out, -128);
488 EmitInstruction(Out, MCInstBuilder(X86::PUSH64r).addReg(X86::RAX));
489 EmitInstruction(Out, MCInstBuilder(X86::PUSH64r).addReg(X86::RCX));
490 EmitInstruction(Out, MCInstBuilder(X86::PUSH64r).addReg(X86::RDI));
491 EmitInstruction(Out, MCInstBuilder(X86::PUSHF64));
494 Inst.setOpcode(X86::LEA64r);
495 Inst.addOperand(MCOperand::CreateReg(X86::RDI));
496 Op.addMemOperands(Inst, 5);
497 EmitInstruction(Out, Inst);
500 Out, MCInstBuilder(X86::MOV64rr).addReg(X86::RAX).addReg(X86::RDI));
503 MCInstBuilder(X86::SHR64ri).addReg(X86::RAX).addReg(X86::RAX).addImm(3));
506 Inst.setOpcode(X86::MOV8rm);
507 Inst.addOperand(MCOperand::CreateReg(X86::AL));
508 const MCExpr *Disp = MCConstantExpr::Create(kShadowOffset, Ctx);
509 std::unique_ptr<X86Operand> Op(
510 X86Operand::CreateMem(0, Disp, X86::RAX, 0, 1, SMLoc(), SMLoc()));
511 Op->addMemOperands(Inst, 5);
512 EmitInstruction(Out, Inst);
516 MCInstBuilder(X86::TEST8rr).addReg(X86::AL).addReg(X86::AL));
517 MCSymbol *DoneSym = Ctx.CreateTempSymbol();
518 const MCExpr *DoneExpr = MCSymbolRefExpr::Create(DoneSym, Ctx);
519 EmitInstruction(Out, MCInstBuilder(X86::JE_4).addExpr(DoneExpr));
522 Out, MCInstBuilder(X86::MOV32rr).addReg(X86::ECX).addReg(X86::EDI));
525 MCInstBuilder(X86::AND32ri).addReg(X86::ECX).addReg(X86::ECX).addImm(7));
527 switch (AccessSize) {
532 Inst.setOpcode(X86::LEA32r);
533 Inst.addOperand(MCOperand::CreateReg(X86::ECX));
535 const MCExpr *Disp = MCConstantExpr::Create(1, Ctx);
536 std::unique_ptr<X86Operand> Op(
537 X86Operand::CreateMem(0, Disp, X86::ECX, 0, 1, SMLoc(), SMLoc()));
538 Op->addMemOperands(Inst, 5);
539 EmitInstruction(Out, Inst);
543 EmitInstruction(Out, MCInstBuilder(X86::ADD32ri8)
549 assert(false && "Incorrect access size");
554 Out, MCInstBuilder(X86::MOVSX32rr8).addReg(X86::EAX).addReg(X86::AL));
556 Out, MCInstBuilder(X86::CMP32rr).addReg(X86::ECX).addReg(X86::EAX));
557 EmitInstruction(Out, MCInstBuilder(X86::JL_4).addExpr(DoneExpr));
559 EmitCallAsanReport(Ctx, Out, AccessSize, IsWrite);
560 EmitLabel(Out, DoneSym);
562 EmitInstruction(Out, MCInstBuilder(X86::POPF64));
563 EmitInstruction(Out, MCInstBuilder(X86::POP64r).addReg(X86::RDI));
564 EmitInstruction(Out, MCInstBuilder(X86::POP64r).addReg(X86::RCX));
565 EmitInstruction(Out, MCInstBuilder(X86::POP64r).addReg(X86::RAX));
566 EmitAdjustRSP(Ctx, Out, 128);
569 void X86AddressSanitizer64::InstrumentMemOperandLargeImpl(X86Operand &Op,
574 EmitAdjustRSP(Ctx, Out, -128);
575 EmitInstruction(Out, MCInstBuilder(X86::PUSH64r).addReg(X86::RAX));
576 EmitInstruction(Out, MCInstBuilder(X86::PUSHF64));
580 Inst.setOpcode(X86::LEA64r);
581 Inst.addOperand(MCOperand::CreateReg(X86::RAX));
582 Op.addMemOperands(Inst, 5);
583 EmitInstruction(Out, Inst);
587 MCInstBuilder(X86::SHR64ri).addReg(X86::RAX).addReg(X86::RAX).addImm(3));
590 switch (AccessSize) {
592 Inst.setOpcode(X86::CMP8mi);
595 Inst.setOpcode(X86::CMP16mi);
598 assert(false && "Incorrect access size");
601 const MCExpr *Disp = MCConstantExpr::Create(kShadowOffset, Ctx);
602 std::unique_ptr<X86Operand> Op(
603 X86Operand::CreateMem(0, Disp, X86::RAX, 0, 1, SMLoc(), SMLoc()));
604 Op->addMemOperands(Inst, 5);
605 Inst.addOperand(MCOperand::CreateImm(0));
606 EmitInstruction(Out, Inst);
609 MCSymbol *DoneSym = Ctx.CreateTempSymbol();
610 const MCExpr *DoneExpr = MCSymbolRefExpr::Create(DoneSym, Ctx);
611 EmitInstruction(Out, MCInstBuilder(X86::JE_4).addExpr(DoneExpr));
613 EmitCallAsanReport(Ctx, Out, AccessSize, IsWrite);
614 EmitLabel(Out, DoneSym);
616 EmitInstruction(Out, MCInstBuilder(X86::POPF64));
617 EmitInstruction(Out, MCInstBuilder(X86::POP64r).addReg(X86::RAX));
618 EmitAdjustRSP(Ctx, Out, 128);
621 void X86AddressSanitizer64::InstrumentMOVSImpl(unsigned AccessSize,
624 EmitInstruction(Out, MCInstBuilder(X86::PUSHF64));
626 // No need to test when RCX is equals to zero.
627 MCSymbol *DoneSym = Ctx.CreateTempSymbol();
628 const MCExpr *DoneExpr = MCSymbolRefExpr::Create(DoneSym, Ctx);
630 Out, MCInstBuilder(X86::TEST64rr).addReg(X86::RCX).addReg(X86::RCX));
631 EmitInstruction(Out, MCInstBuilder(X86::JE_4).addExpr(DoneExpr));
633 // Instrument first and last elements in src and dst range.
634 InstrumentMOVSBase(X86::RDI /* DstReg */, X86::RSI /* SrcReg */,
635 X86::RCX /* CntReg */, AccessSize, Ctx, Out);
637 EmitLabel(Out, DoneSym);
638 EmitInstruction(Out, MCInstBuilder(X86::POPF64));
641 } // End anonymous namespace
643 X86AsmInstrumentation::X86AsmInstrumentation(const MCSubtargetInfo &STI)
646 X86AsmInstrumentation::~X86AsmInstrumentation() {}
648 void X86AsmInstrumentation::InstrumentAndEmitInstruction(
649 const MCInst &Inst, OperandVector &Operands, MCContext &Ctx,
650 const MCInstrInfo &MII, MCStreamer &Out) {
651 EmitInstruction(Out, Inst);
654 void X86AsmInstrumentation::EmitInstruction(MCStreamer &Out,
655 const MCInst &Inst) {
656 Out.EmitInstruction(Inst, STI);
659 X86AsmInstrumentation *
660 CreateX86AsmInstrumentation(const MCTargetOptions &MCOptions,
661 const MCContext &Ctx, const MCSubtargetInfo &STI) {
662 Triple T(STI.getTargetTriple());
663 const bool hasCompilerRTSupport = T.isOSLinux();
664 if (ClAsanInstrumentAssembly && hasCompilerRTSupport &&
665 MCOptions.SanitizeAddress) {
666 if ((STI.getFeatureBits() & X86::Mode32Bit) != 0)
667 return new X86AddressSanitizer32(STI);
668 if ((STI.getFeatureBits() & X86::Mode64Bit) != 0)
669 return new X86AddressSanitizer64(STI);
671 return new X86AsmInstrumentation(STI);
674 } // End llvm namespace