1 //===-- X86AsmParser.cpp - Parse X86 assembly to MCInst instructions ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "llvm/Target/TargetAsmParser.h"
12 #include "X86Subtarget.h"
13 #include "llvm/ADT/SmallString.h"
14 #include "llvm/ADT/SmallVector.h"
15 #include "llvm/ADT/StringSwitch.h"
16 #include "llvm/ADT/Twine.h"
17 #include "llvm/MC/MCStreamer.h"
18 #include "llvm/MC/MCExpr.h"
19 #include "llvm/MC/MCInst.h"
20 #include "llvm/MC/MCParser/MCAsmLexer.h"
21 #include "llvm/MC/MCParser/MCAsmParser.h"
22 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
23 #include "llvm/Support/SourceMgr.h"
24 #include "llvm/Support/raw_ostream.h"
25 #include "llvm/Target/TargetRegistry.h"
26 #include "llvm/Target/TargetAsmParser.h"
32 class X86ATTAsmParser : public TargetAsmParser {
40 MCAsmParser &getParser() const { return Parser; }
42 MCAsmLexer &getLexer() const { return Parser.getLexer(); }
44 bool Error(SMLoc L, const Twine &Msg) { return Parser.Error(L, Msg); }
46 bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc);
48 X86Operand *ParseOperand();
49 X86Operand *ParseMemOperand(unsigned SegReg, SMLoc StartLoc);
51 bool ParseDirectiveWord(unsigned Size, SMLoc L);
53 bool MatchInstruction(SMLoc IDLoc,
54 const SmallVectorImpl<MCParsedAsmOperand*> &Operands,
57 /// @name Auto-generated Matcher Functions
60 unsigned ComputeAvailableFeatures(const X86Subtarget *Subtarget) const;
62 bool MatchInstructionImpl(
63 const SmallVectorImpl<MCParsedAsmOperand*> &Operands, MCInst &Inst);
68 X86ATTAsmParser(const Target &T, MCAsmParser &_Parser, TargetMachine &TM)
69 : TargetAsmParser(T), Parser(_Parser), TM(TM) {
71 // Initialize the set of available features.
72 setAvailableFeatures(ComputeAvailableFeatures(
73 &TM.getSubtarget<X86Subtarget>()));
76 virtual bool ParseInstruction(StringRef Name, SMLoc NameLoc,
77 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
79 virtual bool ParseDirective(AsmToken DirectiveID);
82 class X86_32ATTAsmParser : public X86ATTAsmParser {
84 X86_32ATTAsmParser(const Target &T, MCAsmParser &_Parser, TargetMachine &TM)
85 : X86ATTAsmParser(T, _Parser, TM) {
90 class X86_64ATTAsmParser : public X86ATTAsmParser {
92 X86_64ATTAsmParser(const Target &T, MCAsmParser &_Parser, TargetMachine &TM)
93 : X86ATTAsmParser(T, _Parser, TM) {
98 } // end anonymous namespace
100 /// @name Auto-generated Match Functions
103 static unsigned MatchRegisterName(StringRef Name);
109 /// X86Operand - Instances of this class represent a parsed X86 machine
111 struct X86Operand : public MCParsedAsmOperand {
119 SMLoc StartLoc, EndLoc;
144 X86Operand(KindTy K, SMLoc Start, SMLoc End)
145 : Kind(K), StartLoc(Start), EndLoc(End) {}
147 /// getStartLoc - Get the location of the first token of this operand.
148 SMLoc getStartLoc() const { return StartLoc; }
149 /// getEndLoc - Get the location of the last token of this operand.
150 SMLoc getEndLoc() const { return EndLoc; }
152 virtual void dump(raw_ostream &OS) const {}
154 StringRef getToken() const {
155 assert(Kind == Token && "Invalid access!");
156 return StringRef(Tok.Data, Tok.Length);
158 void setTokenValue(StringRef Value) {
159 assert(Kind == Token && "Invalid access!");
160 Tok.Data = Value.data();
161 Tok.Length = Value.size();
164 unsigned getReg() const {
165 assert(Kind == Register && "Invalid access!");
169 const MCExpr *getImm() const {
170 assert(Kind == Immediate && "Invalid access!");
174 const MCExpr *getMemDisp() const {
175 assert(Kind == Memory && "Invalid access!");
178 unsigned getMemSegReg() const {
179 assert(Kind == Memory && "Invalid access!");
182 unsigned getMemBaseReg() const {
183 assert(Kind == Memory && "Invalid access!");
186 unsigned getMemIndexReg() const {
187 assert(Kind == Memory && "Invalid access!");
190 unsigned getMemScale() const {
191 assert(Kind == Memory && "Invalid access!");
195 bool isToken() const {return Kind == Token; }
197 bool isImm() const { return Kind == Immediate; }
199 bool isImmSExti16i8() const {
203 // If this isn't a constant expr, just assume it fits and let relaxation
205 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
209 // Otherwise, check the value is in a range that makes sense for this
211 uint64_t Value = CE->getValue();
212 return (( Value <= 0x000000000000007FULL)||
213 (0x000000000000FF80ULL <= Value && Value <= 0x000000000000FFFFULL)||
214 (0xFFFFFFFFFFFFFF80ULL <= Value && Value <= 0xFFFFFFFFFFFFFFFFULL));
216 bool isImmSExti32i8() const {
220 // If this isn't a constant expr, just assume it fits and let relaxation
222 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
226 // Otherwise, check the value is in a range that makes sense for this
228 uint64_t Value = CE->getValue();
229 return (( Value <= 0x000000000000007FULL)||
230 (0x00000000FFFFFF80ULL <= Value && Value <= 0x00000000FFFFFFFFULL)||
231 (0xFFFFFFFFFFFFFF80ULL <= Value && Value <= 0xFFFFFFFFFFFFFFFFULL));
233 bool isImmSExti64i8() const {
237 // If this isn't a constant expr, just assume it fits and let relaxation
239 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
243 // Otherwise, check the value is in a range that makes sense for this
245 uint64_t Value = CE->getValue();
246 return (( Value <= 0x000000000000007FULL)||
247 (0xFFFFFFFFFFFFFF80ULL <= Value && Value <= 0xFFFFFFFFFFFFFFFFULL));
249 bool isImmSExti64i32() const {
253 // If this isn't a constant expr, just assume it fits and let relaxation
255 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
259 // Otherwise, check the value is in a range that makes sense for this
261 uint64_t Value = CE->getValue();
262 return (( Value <= 0x000000007FFFFFFFULL)||
263 (0xFFFFFFFF80000000ULL <= Value && Value <= 0xFFFFFFFFFFFFFFFFULL));
266 bool isMem() const { return Kind == Memory; }
268 bool isAbsMem() const {
269 return Kind == Memory && !getMemSegReg() && !getMemBaseReg() &&
270 !getMemIndexReg() && getMemScale() == 1;
273 bool isReg() const { return Kind == Register; }
275 void addExpr(MCInst &Inst, const MCExpr *Expr) const {
276 // Add as immediates when possible.
277 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
278 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
280 Inst.addOperand(MCOperand::CreateExpr(Expr));
283 void addRegOperands(MCInst &Inst, unsigned N) const {
284 assert(N == 1 && "Invalid number of operands!");
285 Inst.addOperand(MCOperand::CreateReg(getReg()));
288 void addImmOperands(MCInst &Inst, unsigned N) const {
289 assert(N == 1 && "Invalid number of operands!");
290 addExpr(Inst, getImm());
293 void addMemOperands(MCInst &Inst, unsigned N) const {
294 assert((N == 5) && "Invalid number of operands!");
295 Inst.addOperand(MCOperand::CreateReg(getMemBaseReg()));
296 Inst.addOperand(MCOperand::CreateImm(getMemScale()));
297 Inst.addOperand(MCOperand::CreateReg(getMemIndexReg()));
298 addExpr(Inst, getMemDisp());
299 Inst.addOperand(MCOperand::CreateReg(getMemSegReg()));
302 void addAbsMemOperands(MCInst &Inst, unsigned N) const {
303 assert((N == 1) && "Invalid number of operands!");
304 Inst.addOperand(MCOperand::CreateExpr(getMemDisp()));
307 static X86Operand *CreateToken(StringRef Str, SMLoc Loc) {
308 X86Operand *Res = new X86Operand(Token, Loc, Loc);
309 Res->Tok.Data = Str.data();
310 Res->Tok.Length = Str.size();
314 static X86Operand *CreateReg(unsigned RegNo, SMLoc StartLoc, SMLoc EndLoc) {
315 X86Operand *Res = new X86Operand(Register, StartLoc, EndLoc);
316 Res->Reg.RegNo = RegNo;
320 static X86Operand *CreateImm(const MCExpr *Val, SMLoc StartLoc, SMLoc EndLoc){
321 X86Operand *Res = new X86Operand(Immediate, StartLoc, EndLoc);
326 /// Create an absolute memory operand.
327 static X86Operand *CreateMem(const MCExpr *Disp, SMLoc StartLoc,
329 X86Operand *Res = new X86Operand(Memory, StartLoc, EndLoc);
331 Res->Mem.Disp = Disp;
332 Res->Mem.BaseReg = 0;
333 Res->Mem.IndexReg = 0;
338 /// Create a generalized memory operand.
339 static X86Operand *CreateMem(unsigned SegReg, const MCExpr *Disp,
340 unsigned BaseReg, unsigned IndexReg,
341 unsigned Scale, SMLoc StartLoc, SMLoc EndLoc) {
342 // We should never just have a displacement, that should be parsed as an
343 // absolute memory operand.
344 assert((SegReg || BaseReg || IndexReg) && "Invalid memory operand!");
346 // The scale should always be one of {1,2,4,8}.
347 assert(((Scale == 1 || Scale == 2 || Scale == 4 || Scale == 8)) &&
349 X86Operand *Res = new X86Operand(Memory, StartLoc, EndLoc);
350 Res->Mem.SegReg = SegReg;
351 Res->Mem.Disp = Disp;
352 Res->Mem.BaseReg = BaseReg;
353 Res->Mem.IndexReg = IndexReg;
354 Res->Mem.Scale = Scale;
359 } // end anonymous namespace.
362 bool X86ATTAsmParser::ParseRegister(unsigned &RegNo,
363 SMLoc &StartLoc, SMLoc &EndLoc) {
365 const AsmToken &TokPercent = Parser.getTok();
366 assert(TokPercent.is(AsmToken::Percent) && "Invalid token kind!");
367 StartLoc = TokPercent.getLoc();
368 Parser.Lex(); // Eat percent token.
370 const AsmToken &Tok = Parser.getTok();
371 if (Tok.isNot(AsmToken::Identifier))
372 return Error(Tok.getLoc(), "invalid register name");
374 // FIXME: Validate register for the current architecture; we have to do
375 // validation later, so maybe there is no need for this here.
376 RegNo = MatchRegisterName(Tok.getString());
378 // FIXME: This should be done using Requires<In32BitMode> and
379 // Requires<In64BitMode> so "eiz" usage in 64-bit instructions
380 // can be also checked.
381 if (RegNo == X86::RIZ && !Is64Bit)
382 return Error(Tok.getLoc(), "riz register in 64-bit mode only");
384 // Parse %st(1) and "%st" as "%st(0)"
385 if (RegNo == 0 && Tok.getString() == "st") {
387 EndLoc = Tok.getLoc();
388 Parser.Lex(); // Eat 'st'
390 // Check to see if we have '(4)' after %st.
391 if (getLexer().isNot(AsmToken::LParen))
396 const AsmToken &IntTok = Parser.getTok();
397 if (IntTok.isNot(AsmToken::Integer))
398 return Error(IntTok.getLoc(), "expected stack index");
399 switch (IntTok.getIntVal()) {
400 case 0: RegNo = X86::ST0; break;
401 case 1: RegNo = X86::ST1; break;
402 case 2: RegNo = X86::ST2; break;
403 case 3: RegNo = X86::ST3; break;
404 case 4: RegNo = X86::ST4; break;
405 case 5: RegNo = X86::ST5; break;
406 case 6: RegNo = X86::ST6; break;
407 case 7: RegNo = X86::ST7; break;
408 default: return Error(IntTok.getLoc(), "invalid stack index");
411 if (getParser().Lex().isNot(AsmToken::RParen))
412 return Error(Parser.getTok().getLoc(), "expected ')'");
414 EndLoc = Tok.getLoc();
415 Parser.Lex(); // Eat ')'
419 // If this is "db[0-7]", match it as an alias
421 if (RegNo == 0 && Tok.getString().size() == 3 &&
422 Tok.getString().startswith("db")) {
423 switch (Tok.getString()[2]) {
424 case '0': RegNo = X86::DR0; break;
425 case '1': RegNo = X86::DR1; break;
426 case '2': RegNo = X86::DR2; break;
427 case '3': RegNo = X86::DR3; break;
428 case '4': RegNo = X86::DR4; break;
429 case '5': RegNo = X86::DR5; break;
430 case '6': RegNo = X86::DR6; break;
431 case '7': RegNo = X86::DR7; break;
435 EndLoc = Tok.getLoc();
436 Parser.Lex(); // Eat it.
442 return Error(Tok.getLoc(), "invalid register name");
444 EndLoc = Tok.getLoc();
445 Parser.Lex(); // Eat identifier token.
449 X86Operand *X86ATTAsmParser::ParseOperand() {
450 switch (getLexer().getKind()) {
452 // Parse a memory operand with no segment register.
453 return ParseMemOperand(0, Parser.getTok().getLoc());
454 case AsmToken::Percent: {
455 // Read the register.
458 if (ParseRegister(RegNo, Start, End)) return 0;
459 if (RegNo == X86::EIZ || RegNo == X86::RIZ) {
460 Error(Start, "eiz and riz can only be used as index registers");
464 // If this is a segment register followed by a ':', then this is the start
465 // of a memory reference, otherwise this is a normal register reference.
466 if (getLexer().isNot(AsmToken::Colon))
467 return X86Operand::CreateReg(RegNo, Start, End);
470 getParser().Lex(); // Eat the colon.
471 return ParseMemOperand(RegNo, Start);
473 case AsmToken::Dollar: {
475 SMLoc Start = Parser.getTok().getLoc(), End;
478 if (getParser().ParseExpression(Val, End))
480 return X86Operand::CreateImm(Val, Start, End);
485 /// ParseMemOperand: segment: disp(basereg, indexreg, scale). The '%ds:' prefix
486 /// has already been parsed if present.
487 X86Operand *X86ATTAsmParser::ParseMemOperand(unsigned SegReg, SMLoc MemStart) {
489 // We have to disambiguate a parenthesized expression "(4+5)" from the start
490 // of a memory operand with a missing displacement "(%ebx)" or "(,%eax)". The
491 // only way to do this without lookahead is to eat the '(' and see what is
493 const MCExpr *Disp = MCConstantExpr::Create(0, getParser().getContext());
494 if (getLexer().isNot(AsmToken::LParen)) {
496 if (getParser().ParseExpression(Disp, ExprEnd)) return 0;
498 // After parsing the base expression we could either have a parenthesized
499 // memory address or not. If not, return now. If so, eat the (.
500 if (getLexer().isNot(AsmToken::LParen)) {
501 // Unless we have a segment register, treat this as an immediate.
503 return X86Operand::CreateMem(Disp, MemStart, ExprEnd);
504 return X86Operand::CreateMem(SegReg, Disp, 0, 0, 1, MemStart, ExprEnd);
510 // Okay, we have a '('. We don't know if this is an expression or not, but
511 // so we have to eat the ( to see beyond it.
512 SMLoc LParenLoc = Parser.getTok().getLoc();
513 Parser.Lex(); // Eat the '('.
515 if (getLexer().is(AsmToken::Percent) || getLexer().is(AsmToken::Comma)) {
516 // Nothing to do here, fall into the code below with the '(' part of the
517 // memory operand consumed.
521 // It must be an parenthesized expression, parse it now.
522 if (getParser().ParseParenExpression(Disp, ExprEnd))
525 // After parsing the base expression we could either have a parenthesized
526 // memory address or not. If not, return now. If so, eat the (.
527 if (getLexer().isNot(AsmToken::LParen)) {
528 // Unless we have a segment register, treat this as an immediate.
530 return X86Operand::CreateMem(Disp, LParenLoc, ExprEnd);
531 return X86Operand::CreateMem(SegReg, Disp, 0, 0, 1, MemStart, ExprEnd);
539 // If we reached here, then we just ate the ( of the memory operand. Process
540 // the rest of the memory operand.
541 unsigned BaseReg = 0, IndexReg = 0, Scale = 1;
543 if (getLexer().is(AsmToken::Percent)) {
545 if (ParseRegister(BaseReg, L, L)) return 0;
546 if (BaseReg == X86::EIZ || BaseReg == X86::RIZ) {
547 Error(L, "eiz and riz can only be used as index registers");
552 if (getLexer().is(AsmToken::Comma)) {
553 Parser.Lex(); // Eat the comma.
555 // Following the comma we should have either an index register, or a scale
556 // value. We don't support the later form, but we want to parse it
559 // Not that even though it would be completely consistent to support syntax
560 // like "1(%eax,,1)", the assembler doesn't. Use "eiz" or "riz" for this.
561 if (getLexer().is(AsmToken::Percent)) {
563 if (ParseRegister(IndexReg, L, L)) return 0;
565 if (getLexer().isNot(AsmToken::RParen)) {
566 // Parse the scale amount:
567 // ::= ',' [scale-expression]
568 if (getLexer().isNot(AsmToken::Comma)) {
569 Error(Parser.getTok().getLoc(),
570 "expected comma in scale expression");
573 Parser.Lex(); // Eat the comma.
575 if (getLexer().isNot(AsmToken::RParen)) {
576 SMLoc Loc = Parser.getTok().getLoc();
579 if (getParser().ParseAbsoluteExpression(ScaleVal))
582 // Validate the scale amount.
583 if (ScaleVal != 1 && ScaleVal != 2 && ScaleVal != 4 && ScaleVal != 8){
584 Error(Loc, "scale factor in address must be 1, 2, 4 or 8");
587 Scale = (unsigned)ScaleVal;
590 } else if (getLexer().isNot(AsmToken::RParen)) {
591 // A scale amount without an index is ignored.
593 SMLoc Loc = Parser.getTok().getLoc();
596 if (getParser().ParseAbsoluteExpression(Value))
600 Warning(Loc, "scale factor without index register is ignored");
605 // Ok, we've eaten the memory operand, verify we have a ')' and eat it too.
606 if (getLexer().isNot(AsmToken::RParen)) {
607 Error(Parser.getTok().getLoc(), "unexpected token in memory operand");
610 SMLoc MemEnd = Parser.getTok().getLoc();
611 Parser.Lex(); // Eat the ')'.
613 return X86Operand::CreateMem(SegReg, Disp, BaseReg, IndexReg, Scale,
617 bool X86ATTAsmParser::
618 ParseInstruction(StringRef Name, SMLoc NameLoc,
619 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
620 // The various flavors of pushf and popf use Requires<In32BitMode> and
621 // Requires<In64BitMode>, but the assembler doesn't yet implement that.
622 // For now, just do a manual check to prevent silent misencoding.
625 return Error(NameLoc, "popfl cannot be encoded in 64-bit mode");
626 else if (Name == "pushfl")
627 return Error(NameLoc, "pushfl cannot be encoded in 64-bit mode");
628 else if (Name == "pusha")
629 return Error(NameLoc, "pusha cannot be encoded in 64-bit mode");
632 return Error(NameLoc, "popfq cannot be encoded in 32-bit mode");
633 else if (Name == "pushfq")
634 return Error(NameLoc, "pushfq cannot be encoded in 32-bit mode");
637 // The "Jump if rCX Zero" form jcxz is not allowed in 64-bit mode and
638 // the form jrcxz is not allowed in 32-bit mode.
641 return Error(NameLoc, "jcxz cannot be encoded in 64-bit mode");
644 return Error(NameLoc, "jrcxz cannot be encoded in 32-bit mode");
647 // FIXME: Hack to recognize "sal..." and "rep..." for now. We need a way to
648 // represent alternative syntaxes in the .td file, without requiring
649 // instruction duplication.
650 StringRef PatchedName = StringSwitch<StringRef>(Name)
652 .Case("salb", "shlb")
653 .Case("sall", "shll")
654 .Case("salq", "shlq")
655 .Case("salw", "shlw")
658 .Case("repnz", "repne")
659 .Case("pushf", Is64Bit ? "pushfq" : "pushfl")
660 .Case("popf", Is64Bit ? "popfq" : "popfl")
661 .Case("retl", Is64Bit ? "retl" : "ret")
662 .Case("retq", Is64Bit ? "ret" : "retq")
663 .Case("setz", "sete")
664 .Case("setnz", "setne")
668 // FIXME: in 32-bit mode jcxz requires an AdSize prefix. In 64-bit mode
669 // jecxz requires an AdSize prefix but jecxz does not have a prefix in
671 .Case("jecxz", "jcxz")
672 .Case("jrcxz", "jcxz")
684 .Case("cmovcl", "cmovbl")
685 .Case("cmovcl", "cmovbl")
686 .Case("cmovnal", "cmovbel")
687 .Case("cmovnbl", "cmovael")
688 .Case("cmovnbel", "cmoval")
689 .Case("cmovncl", "cmovael")
690 .Case("cmovngl", "cmovlel")
691 .Case("cmovnl", "cmovgel")
692 .Case("cmovngl", "cmovlel")
693 .Case("cmovngel", "cmovll")
694 .Case("cmovnll", "cmovgel")
695 .Case("cmovnlel", "cmovgl")
696 .Case("cmovnzl", "cmovnel")
697 .Case("cmovzl", "cmovel")
698 .Case("fwait", "wait")
699 .Case("movzx", "movzb")
702 // FIXME: Hack to recognize cmp<comparison code>{ss,sd,ps,pd}.
703 const MCExpr *ExtraImmOp = 0;
704 if ((PatchedName.startswith("cmp") || PatchedName.startswith("vcmp")) &&
705 (PatchedName.endswith("ss") || PatchedName.endswith("sd") ||
706 PatchedName.endswith("ps") || PatchedName.endswith("pd"))) {
707 bool IsVCMP = PatchedName.startswith("vcmp");
708 unsigned SSECCIdx = IsVCMP ? 4 : 3;
709 unsigned SSEComparisonCode = StringSwitch<unsigned>(
710 PatchedName.slice(SSECCIdx, PatchedName.size() - 2))
723 .Case("neq_oq", 0x0C)
730 .Case("unord_s", 0x13)
731 .Case("neq_us", 0x14)
732 .Case("nlt_uq", 0x15)
733 .Case("nle_uq", 0x16)
736 .Case("nge_uq", 0x19)
737 .Case("ngt_uq", 0x1A)
738 .Case("false_os", 0x1B)
739 .Case("neq_os", 0x1C)
742 .Case("true_us", 0x1F)
744 if (SSEComparisonCode != ~0U) {
745 ExtraImmOp = MCConstantExpr::Create(SSEComparisonCode,
746 getParser().getContext());
747 if (PatchedName.endswith("ss")) {
748 PatchedName = IsVCMP ? "vcmpss" : "cmpss";
749 } else if (PatchedName.endswith("sd")) {
750 PatchedName = IsVCMP ? "vcmpsd" : "cmpsd";
751 } else if (PatchedName.endswith("ps")) {
752 PatchedName = IsVCMP ? "vcmpps" : "cmpps";
754 assert(PatchedName.endswith("pd") && "Unexpected mnemonic!");
755 PatchedName = IsVCMP ? "vcmppd" : "cmppd";
760 // FIXME: Hack to recognize vpclmul<src1_quadword, src2_quadword>dq
761 if (PatchedName.startswith("vpclmul")) {
762 unsigned CLMULQuadWordSelect = StringSwitch<unsigned>(
763 PatchedName.slice(7, PatchedName.size() - 2))
764 .Case("lqlq", 0x00) // src1[63:0], src2[63:0]
765 .Case("hqlq", 0x01) // src1[127:64], src2[63:0]
766 .Case("lqhq", 0x10) // src1[63:0], src2[127:64]
767 .Case("hqhq", 0x11) // src1[127:64], src2[127:64]
769 if (CLMULQuadWordSelect != ~0U) {
770 ExtraImmOp = MCConstantExpr::Create(CLMULQuadWordSelect,
771 getParser().getContext());
772 assert(PatchedName.endswith("dq") && "Unexpected mnemonic!");
773 PatchedName = "vpclmulqdq";
776 Operands.push_back(X86Operand::CreateToken(PatchedName, NameLoc));
779 Operands.push_back(X86Operand::CreateImm(ExtraImmOp, NameLoc, NameLoc));
781 if (getLexer().isNot(AsmToken::EndOfStatement)) {
783 // Parse '*' modifier.
784 if (getLexer().is(AsmToken::Star)) {
785 SMLoc Loc = Parser.getTok().getLoc();
786 Operands.push_back(X86Operand::CreateToken("*", Loc));
787 Parser.Lex(); // Eat the star.
790 // Read the first operand.
791 if (X86Operand *Op = ParseOperand())
792 Operands.push_back(Op);
796 while (getLexer().is(AsmToken::Comma)) {
797 Parser.Lex(); // Eat the comma.
799 // Parse and remember the operand.
800 if (X86Operand *Op = ParseOperand())
801 Operands.push_back(Op);
807 // FIXME: Hack to handle recognizing s{hr,ar,hl}? $1.
808 if ((Name.startswith("shr") || Name.startswith("sar") ||
809 Name.startswith("shl")) &&
810 Operands.size() == 3 &&
811 static_cast<X86Operand*>(Operands[1])->isImm() &&
812 isa<MCConstantExpr>(static_cast<X86Operand*>(Operands[1])->getImm()) &&
813 cast<MCConstantExpr>(static_cast<X86Operand*>(Operands[1])->getImm())->getValue() == 1) {
815 Operands.erase(Operands.begin() + 1);
818 // FIXME: Hack to handle "f{mul*,add*,sub*,div*} $op, st(0)" the same as
819 // "f{mul*,add*,sub*,div*} $op"
820 if ((Name.startswith("fmul") || Name.startswith("fadd") ||
821 Name.startswith("fsub") || Name.startswith("fdiv")) &&
822 Operands.size() == 3 &&
823 static_cast<X86Operand*>(Operands[2])->isReg() &&
824 static_cast<X86Operand*>(Operands[2])->getReg() == X86::ST0) {
826 Operands.erase(Operands.begin() + 2);
829 // FIXME: Hack to handle "imul A, B" which is an alias for "imul A, B, B".
830 if (Name.startswith("imul") && Operands.size() == 3 &&
831 static_cast<X86Operand*>(Operands.back())->isReg()) {
832 X86Operand *Op = static_cast<X86Operand*>(Operands.back());
833 Operands.push_back(X86Operand::CreateReg(Op->getReg(), Op->getStartLoc(),
840 bool X86ATTAsmParser::ParseDirective(AsmToken DirectiveID) {
841 StringRef IDVal = DirectiveID.getIdentifier();
842 if (IDVal == ".word")
843 return ParseDirectiveWord(2, DirectiveID.getLoc());
847 /// ParseDirectiveWord
848 /// ::= .word [ expression (, expression)* ]
849 bool X86ATTAsmParser::ParseDirectiveWord(unsigned Size, SMLoc L) {
850 if (getLexer().isNot(AsmToken::EndOfStatement)) {
853 if (getParser().ParseExpression(Value))
856 getParser().getStreamer().EmitValue(Value, Size, 0 /*addrspace*/);
858 if (getLexer().is(AsmToken::EndOfStatement))
861 // FIXME: Improve diagnostic.
862 if (getLexer().isNot(AsmToken::Comma))
863 return Error(L, "unexpected token in directive");
874 X86ATTAsmParser::MatchInstruction(SMLoc IDLoc,
875 const SmallVectorImpl<MCParsedAsmOperand*>
878 assert(!Operands.empty() && "Unexpect empty operand list!");
880 X86Operand *Op = static_cast<X86Operand*>(Operands[0]);
881 assert(Op->isToken() && "Leading operand should always be a mnemonic!");
883 // First, try a direct match.
884 if (!MatchInstructionImpl(Operands, Inst))
887 // FIXME: Ideally, we would only attempt suffix matches for things which are
888 // valid prefixes, and we could just infer the right unambiguous
889 // type. However, that requires substantially more matcher support than the
892 // Change the operand to point to a temporary token.
893 StringRef Base = Op->getToken();
897 Op->setTokenValue(Tmp.str());
899 // Check for the various suffix matches.
900 Tmp[Base.size()] = 'b';
901 bool MatchB = MatchInstructionImpl(Operands, Inst);
902 Tmp[Base.size()] = 'w';
903 bool MatchW = MatchInstructionImpl(Operands, Inst);
904 Tmp[Base.size()] = 'l';
905 bool MatchL = MatchInstructionImpl(Operands, Inst);
906 Tmp[Base.size()] = 'q';
907 bool MatchQ = MatchInstructionImpl(Operands, Inst);
909 // Restore the old token.
910 Op->setTokenValue(Base);
912 // If exactly one matched, then we treat that as a successful match (and the
913 // instruction will already have been filled in correctly, since the failing
914 // matches won't have modified it).
915 if (MatchB + MatchW + MatchL + MatchQ == 3)
918 // Otherwise, the match failed.
920 // If we had multiple suffix matches, then identify this as an ambiguous
922 if (MatchB + MatchW + MatchL + MatchQ != 4) {
924 unsigned NumMatches = 0;
926 MatchChars[NumMatches++] = 'b';
928 MatchChars[NumMatches++] = 'w';
930 MatchChars[NumMatches++] = 'l';
932 MatchChars[NumMatches++] = 'q';
934 SmallString<126> Msg;
935 raw_svector_ostream OS(Msg);
936 OS << "ambiguous instructions require an explicit suffix (could be ";
937 for (unsigned i = 0; i != NumMatches; ++i) {
940 if (i + 1 == NumMatches)
942 OS << "'" << Base << MatchChars[i] << "'";
945 Error(IDLoc, OS.str());
947 // FIXME: We should give nicer diagnostics about the exact failure.
948 Error(IDLoc, "unrecognized instruction");
955 extern "C" void LLVMInitializeX86AsmLexer();
957 // Force static initialization.
958 extern "C" void LLVMInitializeX86AsmParser() {
959 RegisterAsmParser<X86_32ATTAsmParser> X(TheX86_32Target);
960 RegisterAsmParser<X86_64ATTAsmParser> Y(TheX86_64Target);
961 LLVMInitializeX86AsmLexer();
964 #include "X86GenAsmMatcher.inc"