1 //===-- X86AsmParser.cpp - Parse X86 assembly to MCInst instructions ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "MCTargetDesc/X86BaseInfo.h"
11 #include "X86AsmParserCommon.h"
12 #include "X86Operand.h"
13 #include "llvm/ADT/APFloat.h"
14 #include "llvm/ADT/STLExtras.h"
15 #include "llvm/ADT/SmallString.h"
16 #include "llvm/ADT/SmallVector.h"
17 #include "llvm/ADT/StringSwitch.h"
18 #include "llvm/ADT/Twine.h"
19 #include "llvm/MC/MCContext.h"
20 #include "llvm/MC/MCExpr.h"
21 #include "llvm/MC/MCInst.h"
22 #include "llvm/MC/MCParser/MCAsmLexer.h"
23 #include "llvm/MC/MCParser/MCAsmParser.h"
24 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
25 #include "llvm/MC/MCRegisterInfo.h"
26 #include "llvm/MC/MCStreamer.h"
27 #include "llvm/MC/MCSubtargetInfo.h"
28 #include "llvm/MC/MCSymbol.h"
29 #include "llvm/MC/MCTargetAsmParser.h"
30 #include "llvm/Support/SourceMgr.h"
31 #include "llvm/Support/TargetRegistry.h"
32 #include "llvm/Support/raw_ostream.h"
38 static const char OpPrecedence[] = {
53 class X86AsmParser : public MCTargetAsmParser {
56 ParseInstructionInfo *InstInfo;
58 SMLoc consumeToken() {
59 SMLoc Result = Parser.getTok().getLoc();
64 enum InfixCalculatorTok {
79 class InfixCalculator {
80 typedef std::pair< InfixCalculatorTok, int64_t > ICToken;
81 SmallVector<InfixCalculatorTok, 4> InfixOperatorStack;
82 SmallVector<ICToken, 4> PostfixStack;
85 int64_t popOperand() {
86 assert (!PostfixStack.empty() && "Poped an empty stack!");
87 ICToken Op = PostfixStack.pop_back_val();
88 assert ((Op.first == IC_IMM || Op.first == IC_REGISTER)
89 && "Expected and immediate or register!");
92 void pushOperand(InfixCalculatorTok Op, int64_t Val = 0) {
93 assert ((Op == IC_IMM || Op == IC_REGISTER) &&
94 "Unexpected operand!");
95 PostfixStack.push_back(std::make_pair(Op, Val));
98 void popOperator() { InfixOperatorStack.pop_back(); }
99 void pushOperator(InfixCalculatorTok Op) {
100 // Push the new operator if the stack is empty.
101 if (InfixOperatorStack.empty()) {
102 InfixOperatorStack.push_back(Op);
106 // Push the new operator if it has a higher precedence than the operator
107 // on the top of the stack or the operator on the top of the stack is a
109 unsigned Idx = InfixOperatorStack.size() - 1;
110 InfixCalculatorTok StackOp = InfixOperatorStack[Idx];
111 if (OpPrecedence[Op] > OpPrecedence[StackOp] || StackOp == IC_LPAREN) {
112 InfixOperatorStack.push_back(Op);
116 // The operator on the top of the stack has higher precedence than the
118 unsigned ParenCount = 0;
120 // Nothing to process.
121 if (InfixOperatorStack.empty())
124 Idx = InfixOperatorStack.size() - 1;
125 StackOp = InfixOperatorStack[Idx];
126 if (!(OpPrecedence[StackOp] >= OpPrecedence[Op] || ParenCount))
129 // If we have an even parentheses count and we see a left parentheses,
130 // then stop processing.
131 if (!ParenCount && StackOp == IC_LPAREN)
134 if (StackOp == IC_RPAREN) {
136 InfixOperatorStack.pop_back();
137 } else if (StackOp == IC_LPAREN) {
139 InfixOperatorStack.pop_back();
141 InfixOperatorStack.pop_back();
142 PostfixStack.push_back(std::make_pair(StackOp, 0));
145 // Push the new operator.
146 InfixOperatorStack.push_back(Op);
149 // Push any remaining operators onto the postfix stack.
150 while (!InfixOperatorStack.empty()) {
151 InfixCalculatorTok StackOp = InfixOperatorStack.pop_back_val();
152 if (StackOp != IC_LPAREN && StackOp != IC_RPAREN)
153 PostfixStack.push_back(std::make_pair(StackOp, 0));
156 if (PostfixStack.empty())
159 SmallVector<ICToken, 16> OperandStack;
160 for (unsigned i = 0, e = PostfixStack.size(); i != e; ++i) {
161 ICToken Op = PostfixStack[i];
162 if (Op.first == IC_IMM || Op.first == IC_REGISTER) {
163 OperandStack.push_back(Op);
165 assert (OperandStack.size() > 1 && "Too few operands.");
167 ICToken Op2 = OperandStack.pop_back_val();
168 ICToken Op1 = OperandStack.pop_back_val();
171 report_fatal_error("Unexpected operator!");
174 Val = Op1.second + Op2.second;
175 OperandStack.push_back(std::make_pair(IC_IMM, Val));
178 Val = Op1.second - Op2.second;
179 OperandStack.push_back(std::make_pair(IC_IMM, Val));
182 assert (Op1.first == IC_IMM && Op2.first == IC_IMM &&
183 "Multiply operation with an immediate and a register!");
184 Val = Op1.second * Op2.second;
185 OperandStack.push_back(std::make_pair(IC_IMM, Val));
188 assert (Op1.first == IC_IMM && Op2.first == IC_IMM &&
189 "Divide operation with an immediate and a register!");
190 assert (Op2.second != 0 && "Division by zero!");
191 Val = Op1.second / Op2.second;
192 OperandStack.push_back(std::make_pair(IC_IMM, Val));
195 assert (Op1.first == IC_IMM && Op2.first == IC_IMM &&
196 "Or operation with an immediate and a register!");
197 Val = Op1.second | Op2.second;
198 OperandStack.push_back(std::make_pair(IC_IMM, Val));
201 assert (Op1.first == IC_IMM && Op2.first == IC_IMM &&
202 "And operation with an immediate and a register!");
203 Val = Op1.second & Op2.second;
204 OperandStack.push_back(std::make_pair(IC_IMM, Val));
207 assert (Op1.first == IC_IMM && Op2.first == IC_IMM &&
208 "Left shift operation with an immediate and a register!");
209 Val = Op1.second << Op2.second;
210 OperandStack.push_back(std::make_pair(IC_IMM, Val));
213 assert (Op1.first == IC_IMM && Op2.first == IC_IMM &&
214 "Right shift operation with an immediate and a register!");
215 Val = Op1.second >> Op2.second;
216 OperandStack.push_back(std::make_pair(IC_IMM, Val));
221 assert (OperandStack.size() == 1 && "Expected a single result.");
222 return OperandStack.pop_back_val().second;
226 enum IntelExprState {
245 class IntelExprStateMachine {
246 IntelExprState State, PrevState;
247 unsigned BaseReg, IndexReg, TmpReg, Scale;
251 bool StopOnLBrac, AddImmPrefix;
253 InlineAsmIdentifierInfo Info;
255 IntelExprStateMachine(int64_t imm, bool stoponlbrac, bool addimmprefix) :
256 State(IES_PLUS), PrevState(IES_ERROR), BaseReg(0), IndexReg(0), TmpReg(0),
257 Scale(1), Imm(imm), Sym(0), StopOnLBrac(stoponlbrac),
258 AddImmPrefix(addimmprefix) { Info.clear(); }
260 unsigned getBaseReg() { return BaseReg; }
261 unsigned getIndexReg() { return IndexReg; }
262 unsigned getScale() { return Scale; }
263 const MCExpr *getSym() { return Sym; }
264 StringRef getSymName() { return SymName; }
265 int64_t getImm() { return Imm + IC.execute(); }
266 bool isValidEndState() {
267 return State == IES_RBRAC || State == IES_INTEGER;
269 bool getStopOnLBrac() { return StopOnLBrac; }
270 bool getAddImmPrefix() { return AddImmPrefix; }
271 bool hadError() { return State == IES_ERROR; }
273 InlineAsmIdentifierInfo &getIdentifierInfo() {
278 IntelExprState CurrState = State;
287 IC.pushOperator(IC_OR);
290 PrevState = CurrState;
293 IntelExprState CurrState = State;
302 IC.pushOperator(IC_AND);
305 PrevState = CurrState;
308 IntelExprState CurrState = State;
317 IC.pushOperator(IC_LSHIFT);
320 PrevState = CurrState;
323 IntelExprState CurrState = State;
332 IC.pushOperator(IC_RSHIFT);
335 PrevState = CurrState;
338 IntelExprState CurrState = State;
347 IC.pushOperator(IC_PLUS);
348 if (CurrState == IES_REGISTER && PrevState != IES_MULTIPLY) {
349 // If we already have a BaseReg, then assume this is the IndexReg with
354 assert (!IndexReg && "BaseReg/IndexReg already set!");
361 PrevState = CurrState;
364 IntelExprState CurrState = State;
379 // Only push the minus operator if it is not a unary operator.
380 if (!(CurrState == IES_PLUS || CurrState == IES_MINUS ||
381 CurrState == IES_MULTIPLY || CurrState == IES_DIVIDE ||
382 CurrState == IES_LPAREN || CurrState == IES_LBRAC))
383 IC.pushOperator(IC_MINUS);
384 if (CurrState == IES_REGISTER && PrevState != IES_MULTIPLY) {
385 // If we already have a BaseReg, then assume this is the IndexReg with
390 assert (!IndexReg && "BaseReg/IndexReg already set!");
397 PrevState = CurrState;
399 void onRegister(unsigned Reg) {
400 IntelExprState CurrState = State;
407 State = IES_REGISTER;
409 IC.pushOperand(IC_REGISTER);
412 // Index Register - Scale * Register
413 if (PrevState == IES_INTEGER) {
414 assert (!IndexReg && "IndexReg already set!");
415 State = IES_REGISTER;
417 // Get the scale and replace the 'Scale * Register' with '0'.
418 Scale = IC.popOperand();
419 IC.pushOperand(IC_IMM);
426 PrevState = CurrState;
428 void onIdentifierExpr(const MCExpr *SymRef, StringRef SymRefName) {
438 SymName = SymRefName;
439 IC.pushOperand(IC_IMM);
443 bool onInteger(int64_t TmpInt, StringRef &ErrMsg) {
444 IntelExprState CurrState = State;
459 if (PrevState == IES_REGISTER && CurrState == IES_MULTIPLY) {
460 // Index Register - Register * Scale
461 assert (!IndexReg && "IndexReg already set!");
464 if(Scale != 1 && Scale != 2 && Scale != 4 && Scale != 8) {
465 ErrMsg = "scale factor in address must be 1, 2, 4 or 8";
468 // Get the scale and replace the 'Register * Scale' with '0'.
470 } else if ((PrevState == IES_PLUS || PrevState == IES_MINUS ||
471 PrevState == IES_OR || PrevState == IES_AND ||
472 PrevState == IES_LSHIFT || PrevState == IES_RSHIFT ||
473 PrevState == IES_MULTIPLY || PrevState == IES_DIVIDE ||
474 PrevState == IES_LPAREN || PrevState == IES_LBRAC) &&
475 CurrState == IES_MINUS) {
476 // Unary minus. No need to pop the minus operand because it was never
478 IC.pushOperand(IC_IMM, -TmpInt); // Push -Imm.
480 IC.pushOperand(IC_IMM, TmpInt);
484 PrevState = CurrState;
496 State = IES_MULTIPLY;
497 IC.pushOperator(IC_MULTIPLY);
510 IC.pushOperator(IC_DIVIDE);
522 IC.pushOperator(IC_PLUS);
527 IntelExprState CurrState = State;
536 if (CurrState == IES_REGISTER && PrevState != IES_MULTIPLY) {
537 // If we already have a BaseReg, then assume this is the IndexReg with
542 assert (!IndexReg && "BaseReg/IndexReg already set!");
549 PrevState = CurrState;
552 IntelExprState CurrState = State;
566 // FIXME: We don't handle this type of unary minus, yet.
567 if ((PrevState == IES_PLUS || PrevState == IES_MINUS ||
568 PrevState == IES_OR || PrevState == IES_AND ||
569 PrevState == IES_LSHIFT || PrevState == IES_RSHIFT ||
570 PrevState == IES_MULTIPLY || PrevState == IES_DIVIDE ||
571 PrevState == IES_LPAREN || PrevState == IES_LBRAC) &&
572 CurrState == IES_MINUS) {
577 IC.pushOperator(IC_LPAREN);
580 PrevState = CurrState;
592 IC.pushOperator(IC_RPAREN);
598 MCAsmParser &getParser() const { return Parser; }
600 MCAsmLexer &getLexer() const { return Parser.getLexer(); }
602 bool Error(SMLoc L, const Twine &Msg,
603 ArrayRef<SMRange> Ranges = None,
604 bool MatchingInlineAsm = false) {
605 if (MatchingInlineAsm) return true;
606 return Parser.Error(L, Msg, Ranges);
609 bool ErrorAndEatStatement(SMLoc L, const Twine &Msg,
610 ArrayRef<SMRange> Ranges = None,
611 bool MatchingInlineAsm = false) {
612 Parser.eatToEndOfStatement();
613 return Error(L, Msg, Ranges, MatchingInlineAsm);
616 X86Operand *ErrorOperand(SMLoc Loc, StringRef Msg) {
621 X86Operand *DefaultMemSIOperand(SMLoc Loc);
622 X86Operand *DefaultMemDIOperand(SMLoc Loc);
623 X86Operand *ParseOperand();
624 X86Operand *ParseATTOperand();
625 X86Operand *ParseIntelOperand();
626 X86Operand *ParseIntelOffsetOfOperator();
627 bool ParseIntelDotOperator(const MCExpr *Disp, const MCExpr *&NewDisp);
628 X86Operand *ParseIntelOperator(unsigned OpKind);
629 X86Operand *ParseIntelSegmentOverride(unsigned SegReg, SMLoc Start, unsigned Size);
630 X86Operand *ParseIntelMemOperand(int64_t ImmDisp, SMLoc StartLoc,
632 bool ParseIntelExpression(IntelExprStateMachine &SM, SMLoc &End);
633 X86Operand *ParseIntelBracExpression(unsigned SegReg, SMLoc Start,
634 int64_t ImmDisp, unsigned Size);
635 bool ParseIntelIdentifier(const MCExpr *&Val, StringRef &Identifier,
636 InlineAsmIdentifierInfo &Info,
637 bool IsUnevaluatedOperand, SMLoc &End);
639 X86Operand *ParseMemOperand(unsigned SegReg, SMLoc StartLoc);
641 X86Operand *CreateMemForInlineAsm(unsigned SegReg, const MCExpr *Disp,
642 unsigned BaseReg, unsigned IndexReg,
643 unsigned Scale, SMLoc Start, SMLoc End,
644 unsigned Size, StringRef Identifier,
645 InlineAsmIdentifierInfo &Info);
647 bool ParseDirectiveWord(unsigned Size, SMLoc L);
648 bool ParseDirectiveCode(StringRef IDVal, SMLoc L);
650 bool processInstruction(MCInst &Inst,
651 const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
653 bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
654 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
655 MCStreamer &Out, unsigned &ErrorInfo,
656 bool MatchingInlineAsm);
658 /// doSrcDstMatch - Returns true if operands are matching in their
659 /// word size (%si and %di, %esi and %edi, etc.). Order depends on
660 /// the parsing mode (Intel vs. AT&T).
661 bool doSrcDstMatch(X86Operand &Op1, X86Operand &Op2);
663 /// Parses AVX512 specific operand primitives: masked registers ({%k<NUM>}, {z})
664 /// and memory broadcasting ({1to<NUM>}) primitives, updating Operands vector if required.
665 /// \return \c true if no parsing errors occurred, \c false otherwise.
666 bool HandleAVX512Operand(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
667 const MCParsedAsmOperand &Op);
669 bool is64BitMode() const {
670 // FIXME: Can tablegen auto-generate this?
671 return (STI.getFeatureBits() & X86::Mode64Bit) != 0;
673 bool is32BitMode() const {
674 // FIXME: Can tablegen auto-generate this?
675 return (STI.getFeatureBits() & X86::Mode32Bit) != 0;
677 bool is16BitMode() const {
678 // FIXME: Can tablegen auto-generate this?
679 return (STI.getFeatureBits() & X86::Mode16Bit) != 0;
681 void SwitchMode(uint64_t mode) {
682 uint64_t oldMode = STI.getFeatureBits() &
683 (X86::Mode64Bit | X86::Mode32Bit | X86::Mode16Bit);
684 unsigned FB = ComputeAvailableFeatures(STI.ToggleFeature(oldMode | mode));
685 setAvailableFeatures(FB);
686 assert(mode == (STI.getFeatureBits() &
687 (X86::Mode64Bit | X86::Mode32Bit | X86::Mode16Bit)));
690 bool isParsingIntelSyntax() {
691 return getParser().getAssemblerDialect();
694 /// @name Auto-generated Matcher Functions
697 #define GET_ASSEMBLER_HEADER
698 #include "X86GenAsmMatcher.inc"
703 X86AsmParser(MCSubtargetInfo &sti, MCAsmParser &parser,
704 const MCInstrInfo &MII)
705 : MCTargetAsmParser(), STI(sti), Parser(parser), InstInfo(0) {
707 // Initialize the set of available features.
708 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
710 virtual bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc);
712 virtual bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
714 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
716 virtual bool ParseDirective(AsmToken DirectiveID);
718 } // end anonymous namespace
720 /// @name Auto-generated Match Functions
723 static unsigned MatchRegisterName(StringRef Name);
727 static bool CheckBaseRegAndIndexReg(unsigned BaseReg, unsigned IndexReg,
729 // If we have both a base register and an index register make sure they are
730 // both 64-bit or 32-bit registers.
731 // To support VSIB, IndexReg can be 128-bit or 256-bit registers.
732 if (BaseReg != 0 && IndexReg != 0) {
733 if (X86MCRegisterClasses[X86::GR64RegClassID].contains(BaseReg) &&
734 (X86MCRegisterClasses[X86::GR16RegClassID].contains(IndexReg) ||
735 X86MCRegisterClasses[X86::GR32RegClassID].contains(IndexReg)) &&
736 IndexReg != X86::RIZ) {
737 ErrMsg = "base register is 64-bit, but index register is not";
740 if (X86MCRegisterClasses[X86::GR32RegClassID].contains(BaseReg) &&
741 (X86MCRegisterClasses[X86::GR16RegClassID].contains(IndexReg) ||
742 X86MCRegisterClasses[X86::GR64RegClassID].contains(IndexReg)) &&
743 IndexReg != X86::EIZ){
744 ErrMsg = "base register is 32-bit, but index register is not";
747 if (X86MCRegisterClasses[X86::GR16RegClassID].contains(BaseReg)) {
748 if (X86MCRegisterClasses[X86::GR32RegClassID].contains(IndexReg) ||
749 X86MCRegisterClasses[X86::GR64RegClassID].contains(IndexReg)) {
750 ErrMsg = "base register is 16-bit, but index register is not";
753 if (((BaseReg == X86::BX || BaseReg == X86::BP) &&
754 IndexReg != X86::SI && IndexReg != X86::DI) ||
755 ((BaseReg == X86::SI || BaseReg == X86::DI) &&
756 IndexReg != X86::BX && IndexReg != X86::BP)) {
757 ErrMsg = "invalid 16-bit base/index register combination";
765 bool X86AsmParser::doSrcDstMatch(X86Operand &Op1, X86Operand &Op2)
767 // Return true and let a normal complaint about bogus operands happen.
768 if (!Op1.isMem() || !Op2.isMem())
771 // Actually these might be the other way round if Intel syntax is
772 // being used. It doesn't matter.
773 unsigned diReg = Op1.Mem.BaseReg;
774 unsigned siReg = Op2.Mem.BaseReg;
776 if (X86MCRegisterClasses[X86::GR16RegClassID].contains(siReg))
777 return X86MCRegisterClasses[X86::GR16RegClassID].contains(diReg);
778 if (X86MCRegisterClasses[X86::GR32RegClassID].contains(siReg))
779 return X86MCRegisterClasses[X86::GR32RegClassID].contains(diReg);
780 if (X86MCRegisterClasses[X86::GR64RegClassID].contains(siReg))
781 return X86MCRegisterClasses[X86::GR64RegClassID].contains(diReg);
782 // Again, return true and let another error happen.
786 bool X86AsmParser::ParseRegister(unsigned &RegNo,
787 SMLoc &StartLoc, SMLoc &EndLoc) {
789 const AsmToken &PercentTok = Parser.getTok();
790 StartLoc = PercentTok.getLoc();
792 // If we encounter a %, ignore it. This code handles registers with and
793 // without the prefix, unprefixed registers can occur in cfi directives.
794 if (!isParsingIntelSyntax() && PercentTok.is(AsmToken::Percent))
795 Parser.Lex(); // Eat percent token.
797 const AsmToken &Tok = Parser.getTok();
798 EndLoc = Tok.getEndLoc();
800 if (Tok.isNot(AsmToken::Identifier)) {
801 if (isParsingIntelSyntax()) return true;
802 return Error(StartLoc, "invalid register name",
803 SMRange(StartLoc, EndLoc));
806 RegNo = MatchRegisterName(Tok.getString());
808 // If the match failed, try the register name as lowercase.
810 RegNo = MatchRegisterName(Tok.getString().lower());
812 if (!is64BitMode()) {
813 // FIXME: This should be done using Requires<Not64BitMode> and
814 // Requires<In64BitMode> so "eiz" usage in 64-bit instructions can be also
816 // FIXME: Check AH, CH, DH, BH cannot be used in an instruction requiring a
818 if (RegNo == X86::RIZ ||
819 X86MCRegisterClasses[X86::GR64RegClassID].contains(RegNo) ||
820 X86II::isX86_64NonExtLowByteReg(RegNo) ||
821 X86II::isX86_64ExtendedReg(RegNo))
822 return Error(StartLoc, "register %"
823 + Tok.getString() + " is only available in 64-bit mode",
824 SMRange(StartLoc, EndLoc));
827 // Parse "%st" as "%st(0)" and "%st(1)", which is multiple tokens.
828 if (RegNo == 0 && (Tok.getString() == "st" || Tok.getString() == "ST")) {
830 Parser.Lex(); // Eat 'st'
832 // Check to see if we have '(4)' after %st.
833 if (getLexer().isNot(AsmToken::LParen))
838 const AsmToken &IntTok = Parser.getTok();
839 if (IntTok.isNot(AsmToken::Integer))
840 return Error(IntTok.getLoc(), "expected stack index");
841 switch (IntTok.getIntVal()) {
842 case 0: RegNo = X86::ST0; break;
843 case 1: RegNo = X86::ST1; break;
844 case 2: RegNo = X86::ST2; break;
845 case 3: RegNo = X86::ST3; break;
846 case 4: RegNo = X86::ST4; break;
847 case 5: RegNo = X86::ST5; break;
848 case 6: RegNo = X86::ST6; break;
849 case 7: RegNo = X86::ST7; break;
850 default: return Error(IntTok.getLoc(), "invalid stack index");
853 if (getParser().Lex().isNot(AsmToken::RParen))
854 return Error(Parser.getTok().getLoc(), "expected ')'");
856 EndLoc = Parser.getTok().getEndLoc();
857 Parser.Lex(); // Eat ')'
861 EndLoc = Parser.getTok().getEndLoc();
863 // If this is "db[0-7]", match it as an alias
865 if (RegNo == 0 && Tok.getString().size() == 3 &&
866 Tok.getString().startswith("db")) {
867 switch (Tok.getString()[2]) {
868 case '0': RegNo = X86::DR0; break;
869 case '1': RegNo = X86::DR1; break;
870 case '2': RegNo = X86::DR2; break;
871 case '3': RegNo = X86::DR3; break;
872 case '4': RegNo = X86::DR4; break;
873 case '5': RegNo = X86::DR5; break;
874 case '6': RegNo = X86::DR6; break;
875 case '7': RegNo = X86::DR7; break;
879 EndLoc = Parser.getTok().getEndLoc();
880 Parser.Lex(); // Eat it.
886 if (isParsingIntelSyntax()) return true;
887 return Error(StartLoc, "invalid register name",
888 SMRange(StartLoc, EndLoc));
891 Parser.Lex(); // Eat identifier token.
895 X86Operand *X86AsmParser::DefaultMemSIOperand(SMLoc Loc) {
897 is64BitMode() ? X86::RSI : (is32BitMode() ? X86::ESI : X86::SI);
898 const MCExpr *Disp = MCConstantExpr::Create(0, getContext());
899 return X86Operand::CreateMem(/*SegReg=*/0, Disp, /*BaseReg=*/basereg,
900 /*IndexReg=*/0, /*Scale=*/1, Loc, Loc, 0);
903 X86Operand *X86AsmParser::DefaultMemDIOperand(SMLoc Loc) {
905 is64BitMode() ? X86::RDI : (is32BitMode() ? X86::EDI : X86::DI);
906 const MCExpr *Disp = MCConstantExpr::Create(0, getContext());
907 return X86Operand::CreateMem(/*SegReg=*/0, Disp, /*BaseReg=*/basereg,
908 /*IndexReg=*/0, /*Scale=*/1, Loc, Loc, 0);
911 X86Operand *X86AsmParser::ParseOperand() {
912 if (isParsingIntelSyntax())
913 return ParseIntelOperand();
914 return ParseATTOperand();
917 /// getIntelMemOperandSize - Return intel memory operand size.
918 static unsigned getIntelMemOperandSize(StringRef OpStr) {
919 unsigned Size = StringSwitch<unsigned>(OpStr)
920 .Cases("BYTE", "byte", 8)
921 .Cases("WORD", "word", 16)
922 .Cases("DWORD", "dword", 32)
923 .Cases("QWORD", "qword", 64)
924 .Cases("XWORD", "xword", 80)
925 .Cases("XMMWORD", "xmmword", 128)
926 .Cases("YMMWORD", "ymmword", 256)
927 .Cases("ZMMWORD", "zmmword", 512)
928 .Cases("OPAQUE", "opaque", -1U) // needs to be non-zero, but doesn't matter
934 X86AsmParser::CreateMemForInlineAsm(unsigned SegReg, const MCExpr *Disp,
935 unsigned BaseReg, unsigned IndexReg,
936 unsigned Scale, SMLoc Start, SMLoc End,
937 unsigned Size, StringRef Identifier,
938 InlineAsmIdentifierInfo &Info){
939 // If this is not a VarDecl then assume it is a FuncDecl or some other label
940 // reference. We need an 'r' constraint here, so we need to create register
941 // operand to ensure proper matching. Just pick a GPR based on the size of
943 if (isa<MCSymbolRefExpr>(Disp) && !Info.IsVarDecl) {
945 is64BitMode() ? X86::RBX : (is32BitMode() ? X86::EBX : X86::BX);
946 return X86Operand::CreateReg(RegNo, Start, End, /*AddressOf=*/true,
947 SMLoc(), Identifier, Info.OpDecl);
950 // We either have a direct symbol reference, or an offset from a symbol. The
951 // parser always puts the symbol on the LHS, so look there for size
952 // calculation purposes.
953 const MCBinaryExpr *BinOp = dyn_cast<MCBinaryExpr>(Disp);
955 isa<MCSymbolRefExpr>(BinOp ? BinOp->getLHS() : Disp);
958 Size = Info.Type * 8; // Size is in terms of bits in this context.
960 InstInfo->AsmRewrites->push_back(AsmRewrite(AOK_SizeDirective, Start,
965 // When parsing inline assembly we set the base register to a non-zero value
966 // if we don't know the actual value at this time. This is necessary to
967 // get the matching correct in some cases.
968 BaseReg = BaseReg ? BaseReg : 1;
969 return X86Operand::CreateMem(SegReg, Disp, BaseReg, IndexReg, Scale, Start,
970 End, Size, Identifier, Info.OpDecl);
974 RewriteIntelBracExpression(SmallVectorImpl<AsmRewrite> *AsmRewrites,
975 StringRef SymName, int64_t ImmDisp,
976 int64_t FinalImmDisp, SMLoc &BracLoc,
977 SMLoc &StartInBrac, SMLoc &End) {
978 // Remove the '[' and ']' from the IR string.
979 AsmRewrites->push_back(AsmRewrite(AOK_Skip, BracLoc, 1));
980 AsmRewrites->push_back(AsmRewrite(AOK_Skip, End, 1));
982 // If ImmDisp is non-zero, then we parsed a displacement before the
983 // bracketed expression (i.e., ImmDisp [ BaseReg + Scale*IndexReg + Disp])
984 // If ImmDisp doesn't match the displacement computed by the state machine
985 // then we have an additional displacement in the bracketed expression.
986 if (ImmDisp != FinalImmDisp) {
988 // We have an immediate displacement before the bracketed expression.
989 // Adjust this to match the final immediate displacement.
991 for (SmallVectorImpl<AsmRewrite>::iterator I = AsmRewrites->begin(),
992 E = AsmRewrites->end(); I != E; ++I) {
993 if ((*I).Loc.getPointer() > BracLoc.getPointer())
995 if ((*I).Kind == AOK_ImmPrefix || (*I).Kind == AOK_Imm) {
996 assert (!Found && "ImmDisp already rewritten.");
998 (*I).Len = BracLoc.getPointer() - (*I).Loc.getPointer();
999 (*I).Val = FinalImmDisp;
1004 assert (Found && "Unable to rewrite ImmDisp.");
1007 // We have a symbolic and an immediate displacement, but no displacement
1008 // before the bracketed expression. Put the immediate displacement
1009 // before the bracketed expression.
1010 AsmRewrites->push_back(AsmRewrite(AOK_Imm, BracLoc, 0, FinalImmDisp));
1013 // Remove all the ImmPrefix rewrites within the brackets.
1014 for (SmallVectorImpl<AsmRewrite>::iterator I = AsmRewrites->begin(),
1015 E = AsmRewrites->end(); I != E; ++I) {
1016 if ((*I).Loc.getPointer() < StartInBrac.getPointer())
1018 if ((*I).Kind == AOK_ImmPrefix)
1019 (*I).Kind = AOK_Delete;
1021 const char *SymLocPtr = SymName.data();
1022 // Skip everything before the symbol.
1023 if (unsigned Len = SymLocPtr - StartInBrac.getPointer()) {
1024 assert(Len > 0 && "Expected a non-negative length.");
1025 AsmRewrites->push_back(AsmRewrite(AOK_Skip, StartInBrac, Len));
1027 // Skip everything after the symbol.
1028 if (unsigned Len = End.getPointer() - (SymLocPtr + SymName.size())) {
1029 SMLoc Loc = SMLoc::getFromPointer(SymLocPtr + SymName.size());
1030 assert(Len > 0 && "Expected a non-negative length.");
1031 AsmRewrites->push_back(AsmRewrite(AOK_Skip, Loc, Len));
1035 bool X86AsmParser::ParseIntelExpression(IntelExprStateMachine &SM, SMLoc &End) {
1036 const AsmToken &Tok = Parser.getTok();
1040 bool UpdateLocLex = true;
1042 // The period in the dot operator (e.g., [ebx].foo.bar) is parsed as an
1043 // identifier. Don't try an parse it as a register.
1044 if (Tok.getString().startswith("."))
1047 // If we're parsing an immediate expression, we don't expect a '['.
1048 if (SM.getStopOnLBrac() && getLexer().getKind() == AsmToken::LBrac)
1051 switch (getLexer().getKind()) {
1053 if (SM.isValidEndState()) {
1057 return Error(Tok.getLoc(), "unknown token in expression");
1059 case AsmToken::EndOfStatement: {
1063 case AsmToken::Identifier: {
1064 // This could be a register or a symbolic displacement.
1067 SMLoc IdentLoc = Tok.getLoc();
1068 StringRef Identifier = Tok.getString();
1069 if(!ParseRegister(TmpReg, IdentLoc, End)) {
1070 SM.onRegister(TmpReg);
1071 UpdateLocLex = false;
1074 if (!isParsingInlineAsm()) {
1075 if (getParser().parsePrimaryExpr(Val, End))
1076 return Error(Tok.getLoc(), "Unexpected identifier!");
1078 InlineAsmIdentifierInfo &Info = SM.getIdentifierInfo();
1079 if (ParseIntelIdentifier(Val, Identifier, Info,
1080 /*Unevaluated=*/false, End))
1083 SM.onIdentifierExpr(Val, Identifier);
1084 UpdateLocLex = false;
1087 return Error(Tok.getLoc(), "Unexpected identifier!");
1089 case AsmToken::Integer: {
1091 if (isParsingInlineAsm() && SM.getAddImmPrefix())
1092 InstInfo->AsmRewrites->push_back(AsmRewrite(AOK_ImmPrefix,
1094 // Look for 'b' or 'f' following an Integer as a directional label
1095 SMLoc Loc = getTok().getLoc();
1096 int64_t IntVal = getTok().getIntVal();
1097 End = consumeToken();
1098 UpdateLocLex = false;
1099 if (getLexer().getKind() == AsmToken::Identifier) {
1100 StringRef IDVal = getTok().getString();
1101 if (IDVal == "f" || IDVal == "b") {
1103 getContext().GetDirectionalLocalSymbol(IntVal,
1104 IDVal == "f" ? 1 : 0);
1105 MCSymbolRefExpr::VariantKind Variant = MCSymbolRefExpr::VK_None;
1107 MCSymbolRefExpr::Create(Sym, Variant, getContext());
1108 if (IDVal == "b" && Sym->isUndefined())
1109 return Error(Loc, "invalid reference to undefined symbol");
1110 StringRef Identifier = Sym->getName();
1111 SM.onIdentifierExpr(Val, Identifier);
1112 End = consumeToken();
1114 if (SM.onInteger(IntVal, ErrMsg))
1115 return Error(Loc, ErrMsg);
1118 if (SM.onInteger(IntVal, ErrMsg))
1119 return Error(Loc, ErrMsg);
1123 case AsmToken::Plus: SM.onPlus(); break;
1124 case AsmToken::Minus: SM.onMinus(); break;
1125 case AsmToken::Star: SM.onStar(); break;
1126 case AsmToken::Slash: SM.onDivide(); break;
1127 case AsmToken::Pipe: SM.onOr(); break;
1128 case AsmToken::Amp: SM.onAnd(); break;
1129 case AsmToken::LessLess:
1130 SM.onLShift(); break;
1131 case AsmToken::GreaterGreater:
1132 SM.onRShift(); break;
1133 case AsmToken::LBrac: SM.onLBrac(); break;
1134 case AsmToken::RBrac: SM.onRBrac(); break;
1135 case AsmToken::LParen: SM.onLParen(); break;
1136 case AsmToken::RParen: SM.onRParen(); break;
1139 return Error(Tok.getLoc(), "unknown token in expression");
1141 if (!Done && UpdateLocLex)
1142 End = consumeToken();
1147 X86Operand *X86AsmParser::ParseIntelBracExpression(unsigned SegReg, SMLoc Start,
1150 const AsmToken &Tok = Parser.getTok();
1151 SMLoc BracLoc = Tok.getLoc(), End = Tok.getEndLoc();
1152 if (getLexer().isNot(AsmToken::LBrac))
1153 return ErrorOperand(BracLoc, "Expected '[' token!");
1154 Parser.Lex(); // Eat '['
1156 SMLoc StartInBrac = Tok.getLoc();
1157 // Parse [ Symbol + ImmDisp ] and [ BaseReg + Scale*IndexReg + ImmDisp ]. We
1158 // may have already parsed an immediate displacement before the bracketed
1160 IntelExprStateMachine SM(ImmDisp, /*StopOnLBrac=*/false, /*AddImmPrefix=*/true);
1161 if (ParseIntelExpression(SM, End))
1164 const MCExpr *Disp = 0;
1165 if (const MCExpr *Sym = SM.getSym()) {
1166 // A symbolic displacement.
1168 if (isParsingInlineAsm())
1169 RewriteIntelBracExpression(InstInfo->AsmRewrites, SM.getSymName(),
1170 ImmDisp, SM.getImm(), BracLoc, StartInBrac,
1174 if (SM.getImm() || !Disp) {
1175 const MCExpr *Imm = MCConstantExpr::Create(SM.getImm(), getContext());
1177 Disp = MCBinaryExpr::CreateAdd(Disp, Imm, getContext());
1179 Disp = Imm; // An immediate displacement only.
1182 // Parse the dot operator (e.g., [ebx].foo.bar).
1183 if (Tok.getString().startswith(".")) {
1184 const MCExpr *NewDisp;
1185 if (ParseIntelDotOperator(Disp, NewDisp))
1188 End = Tok.getEndLoc();
1189 Parser.Lex(); // Eat the field.
1193 int BaseReg = SM.getBaseReg();
1194 int IndexReg = SM.getIndexReg();
1195 int Scale = SM.getScale();
1196 if (!isParsingInlineAsm()) {
1198 if (!BaseReg && !IndexReg) {
1200 return X86Operand::CreateMem(Disp, Start, End, Size);
1202 return X86Operand::CreateMem(SegReg, Disp, 0, 0, 1, Start, End, Size);
1205 if (CheckBaseRegAndIndexReg(BaseReg, IndexReg, ErrMsg)) {
1206 Error(StartInBrac, ErrMsg);
1209 return X86Operand::CreateMem(SegReg, Disp, BaseReg, IndexReg, Scale, Start,
1213 InlineAsmIdentifierInfo &Info = SM.getIdentifierInfo();
1214 return CreateMemForInlineAsm(SegReg, Disp, BaseReg, IndexReg, Scale, Start,
1215 End, Size, SM.getSymName(), Info);
1218 // Inline assembly may use variable names with namespace alias qualifiers.
1219 bool X86AsmParser::ParseIntelIdentifier(const MCExpr *&Val,
1220 StringRef &Identifier,
1221 InlineAsmIdentifierInfo &Info,
1222 bool IsUnevaluatedOperand, SMLoc &End) {
1223 assert (isParsingInlineAsm() && "Expected to be parsing inline assembly.");
1226 StringRef LineBuf(Identifier.data());
1227 SemaCallback->LookupInlineAsmIdentifier(LineBuf, Info, IsUnevaluatedOperand);
1229 const AsmToken &Tok = Parser.getTok();
1231 // Advance the token stream until the end of the current token is
1232 // after the end of what the frontend claimed.
1233 const char *EndPtr = Tok.getLoc().getPointer() + LineBuf.size();
1235 End = Tok.getEndLoc();
1238 assert(End.getPointer() <= EndPtr && "frontend claimed part of a token?");
1239 if (End.getPointer() == EndPtr) break;
1242 // Create the symbol reference.
1243 Identifier = LineBuf;
1244 MCSymbol *Sym = getContext().GetOrCreateSymbol(Identifier);
1245 MCSymbolRefExpr::VariantKind Variant = MCSymbolRefExpr::VK_None;
1246 Val = MCSymbolRefExpr::Create(Sym, Variant, getParser().getContext());
1250 /// \brief Parse intel style segment override.
1251 X86Operand *X86AsmParser::ParseIntelSegmentOverride(unsigned SegReg,
1254 assert(SegReg != 0 && "Tried to parse a segment override without a segment!");
1255 const AsmToken &Tok = Parser.getTok(); // Eat colon.
1256 if (Tok.isNot(AsmToken::Colon))
1257 return ErrorOperand(Tok.getLoc(), "Expected ':' token!");
1258 Parser.Lex(); // Eat ':'
1260 int64_t ImmDisp = 0;
1261 if (getLexer().is(AsmToken::Integer)) {
1262 ImmDisp = Tok.getIntVal();
1263 AsmToken ImmDispToken = Parser.Lex(); // Eat the integer.
1265 if (isParsingInlineAsm())
1266 InstInfo->AsmRewrites->push_back(
1267 AsmRewrite(AOK_ImmPrefix, ImmDispToken.getLoc()));
1269 if (getLexer().isNot(AsmToken::LBrac)) {
1270 // An immediate following a 'segment register', 'colon' token sequence can
1271 // be followed by a bracketed expression. If it isn't we know we have our
1272 // final segment override.
1273 const MCExpr *Disp = MCConstantExpr::Create(ImmDisp, getContext());
1274 return X86Operand::CreateMem(SegReg, Disp, /*BaseReg=*/0, /*IndexReg=*/0,
1275 /*Scale=*/1, Start, ImmDispToken.getEndLoc(),
1280 if (getLexer().is(AsmToken::LBrac))
1281 return ParseIntelBracExpression(SegReg, Start, ImmDisp, Size);
1285 if (!isParsingInlineAsm()) {
1286 if (getParser().parsePrimaryExpr(Val, End))
1287 return ErrorOperand(Tok.getLoc(), "unknown token in expression");
1289 return X86Operand::CreateMem(Val, Start, End, Size);
1292 InlineAsmIdentifierInfo Info;
1293 StringRef Identifier = Tok.getString();
1294 if (ParseIntelIdentifier(Val, Identifier, Info,
1295 /*Unevaluated=*/false, End))
1297 return CreateMemForInlineAsm(/*SegReg=*/0, Val, /*BaseReg=*/0,/*IndexReg=*/0,
1298 /*Scale=*/1, Start, End, Size, Identifier, Info);
1301 /// ParseIntelMemOperand - Parse intel style memory operand.
1302 X86Operand *X86AsmParser::ParseIntelMemOperand(int64_t ImmDisp, SMLoc Start,
1304 const AsmToken &Tok = Parser.getTok();
1307 // Parse ImmDisp [ BaseReg + Scale*IndexReg + Disp ].
1308 if (getLexer().is(AsmToken::LBrac))
1309 return ParseIntelBracExpression(/*SegReg=*/0, Start, ImmDisp, Size);
1312 if (!isParsingInlineAsm()) {
1313 if (getParser().parsePrimaryExpr(Val, End))
1314 return ErrorOperand(Tok.getLoc(), "unknown token in expression");
1316 return X86Operand::CreateMem(Val, Start, End, Size);
1319 InlineAsmIdentifierInfo Info;
1320 StringRef Identifier = Tok.getString();
1321 if (ParseIntelIdentifier(Val, Identifier, Info,
1322 /*Unevaluated=*/false, End))
1324 return CreateMemForInlineAsm(/*SegReg=*/0, Val, /*BaseReg=*/0, /*IndexReg=*/0,
1325 /*Scale=*/1, Start, End, Size, Identifier, Info);
1328 /// Parse the '.' operator.
1329 bool X86AsmParser::ParseIntelDotOperator(const MCExpr *Disp,
1330 const MCExpr *&NewDisp) {
1331 const AsmToken &Tok = Parser.getTok();
1332 int64_t OrigDispVal, DotDispVal;
1334 // FIXME: Handle non-constant expressions.
1335 if (const MCConstantExpr *OrigDisp = dyn_cast<MCConstantExpr>(Disp))
1336 OrigDispVal = OrigDisp->getValue();
1338 return Error(Tok.getLoc(), "Non-constant offsets are not supported!");
1341 StringRef DotDispStr = Tok.getString().drop_front(1);
1343 // .Imm gets lexed as a real.
1344 if (Tok.is(AsmToken::Real)) {
1346 DotDispStr.getAsInteger(10, DotDisp);
1347 DotDispVal = DotDisp.getZExtValue();
1348 } else if (isParsingInlineAsm() && Tok.is(AsmToken::Identifier)) {
1350 std::pair<StringRef, StringRef> BaseMember = DotDispStr.split('.');
1351 if (SemaCallback->LookupInlineAsmField(BaseMember.first, BaseMember.second,
1353 return Error(Tok.getLoc(), "Unable to lookup field reference!");
1354 DotDispVal = DotDisp;
1356 return Error(Tok.getLoc(), "Unexpected token type!");
1358 if (isParsingInlineAsm() && Tok.is(AsmToken::Identifier)) {
1359 SMLoc Loc = SMLoc::getFromPointer(DotDispStr.data());
1360 unsigned Len = DotDispStr.size();
1361 unsigned Val = OrigDispVal + DotDispVal;
1362 InstInfo->AsmRewrites->push_back(AsmRewrite(AOK_DotOperator, Loc, Len,
1366 NewDisp = MCConstantExpr::Create(OrigDispVal + DotDispVal, getContext());
1370 /// Parse the 'offset' operator. This operator is used to specify the
1371 /// location rather then the content of a variable.
1372 X86Operand *X86AsmParser::ParseIntelOffsetOfOperator() {
1373 const AsmToken &Tok = Parser.getTok();
1374 SMLoc OffsetOfLoc = Tok.getLoc();
1375 Parser.Lex(); // Eat offset.
1378 InlineAsmIdentifierInfo Info;
1379 SMLoc Start = Tok.getLoc(), End;
1380 StringRef Identifier = Tok.getString();
1381 if (ParseIntelIdentifier(Val, Identifier, Info,
1382 /*Unevaluated=*/false, End))
1385 // Don't emit the offset operator.
1386 InstInfo->AsmRewrites->push_back(AsmRewrite(AOK_Skip, OffsetOfLoc, 7));
1388 // The offset operator will have an 'r' constraint, thus we need to create
1389 // register operand to ensure proper matching. Just pick a GPR based on
1390 // the size of a pointer.
1392 is64BitMode() ? X86::RBX : (is32BitMode() ? X86::EBX : X86::BX);
1393 return X86Operand::CreateReg(RegNo, Start, End, /*GetAddress=*/true,
1394 OffsetOfLoc, Identifier, Info.OpDecl);
1397 enum IntelOperatorKind {
1403 /// Parse the 'LENGTH', 'TYPE' and 'SIZE' operators. The LENGTH operator
1404 /// returns the number of elements in an array. It returns the value 1 for
1405 /// non-array variables. The SIZE operator returns the size of a C or C++
1406 /// variable. A variable's size is the product of its LENGTH and TYPE. The
1407 /// TYPE operator returns the size of a C or C++ type or variable. If the
1408 /// variable is an array, TYPE returns the size of a single element.
1409 X86Operand *X86AsmParser::ParseIntelOperator(unsigned OpKind) {
1410 const AsmToken &Tok = Parser.getTok();
1411 SMLoc TypeLoc = Tok.getLoc();
1412 Parser.Lex(); // Eat operator.
1414 const MCExpr *Val = 0;
1415 InlineAsmIdentifierInfo Info;
1416 SMLoc Start = Tok.getLoc(), End;
1417 StringRef Identifier = Tok.getString();
1418 if (ParseIntelIdentifier(Val, Identifier, Info,
1419 /*Unevaluated=*/true, End))
1423 return ErrorOperand(Start, "unable to lookup expression");
1427 default: llvm_unreachable("Unexpected operand kind!");
1428 case IOK_LENGTH: CVal = Info.Length; break;
1429 case IOK_SIZE: CVal = Info.Size; break;
1430 case IOK_TYPE: CVal = Info.Type; break;
1433 // Rewrite the type operator and the C or C++ type or variable in terms of an
1434 // immediate. E.g. TYPE foo -> $$4
1435 unsigned Len = End.getPointer() - TypeLoc.getPointer();
1436 InstInfo->AsmRewrites->push_back(AsmRewrite(AOK_Imm, TypeLoc, Len, CVal));
1438 const MCExpr *Imm = MCConstantExpr::Create(CVal, getContext());
1439 return X86Operand::CreateImm(Imm, Start, End);
1442 X86Operand *X86AsmParser::ParseIntelOperand() {
1443 const AsmToken &Tok = Parser.getTok();
1446 // Offset, length, type and size operators.
1447 if (isParsingInlineAsm()) {
1448 StringRef AsmTokStr = Tok.getString();
1449 if (AsmTokStr == "offset" || AsmTokStr == "OFFSET")
1450 return ParseIntelOffsetOfOperator();
1451 if (AsmTokStr == "length" || AsmTokStr == "LENGTH")
1452 return ParseIntelOperator(IOK_LENGTH);
1453 if (AsmTokStr == "size" || AsmTokStr == "SIZE")
1454 return ParseIntelOperator(IOK_SIZE);
1455 if (AsmTokStr == "type" || AsmTokStr == "TYPE")
1456 return ParseIntelOperator(IOK_TYPE);
1459 unsigned Size = getIntelMemOperandSize(Tok.getString());
1461 Parser.Lex(); // Eat operand size (e.g., byte, word).
1462 if (Tok.getString() != "PTR" && Tok.getString() != "ptr")
1463 return ErrorOperand(Start, "Expected 'PTR' or 'ptr' token!");
1464 Parser.Lex(); // Eat ptr.
1466 Start = Tok.getLoc();
1469 if (getLexer().is(AsmToken::Integer) || getLexer().is(AsmToken::Minus) ||
1470 getLexer().is(AsmToken::LParen)) {
1471 AsmToken StartTok = Tok;
1472 IntelExprStateMachine SM(/*Imm=*/0, /*StopOnLBrac=*/true,
1473 /*AddImmPrefix=*/false);
1474 if (ParseIntelExpression(SM, End))
1477 int64_t Imm = SM.getImm();
1478 if (isParsingInlineAsm()) {
1479 unsigned Len = Tok.getLoc().getPointer() - Start.getPointer();
1480 if (StartTok.getString().size() == Len)
1481 // Just add a prefix if this wasn't a complex immediate expression.
1482 InstInfo->AsmRewrites->push_back(AsmRewrite(AOK_ImmPrefix, Start));
1484 // Otherwise, rewrite the complex expression as a single immediate.
1485 InstInfo->AsmRewrites->push_back(AsmRewrite(AOK_Imm, Start, Len, Imm));
1488 if (getLexer().isNot(AsmToken::LBrac)) {
1489 // If a directional label (ie. 1f or 2b) was parsed above from
1490 // ParseIntelExpression() then SM.getSym() was set to a pointer to
1491 // to the MCExpr with the directional local symbol and this is a
1492 // memory operand not an immediate operand.
1494 return X86Operand::CreateMem(SM.getSym(), Start, End, Size);
1496 const MCExpr *ImmExpr = MCConstantExpr::Create(Imm, getContext());
1497 return X86Operand::CreateImm(ImmExpr, Start, End);
1500 // Only positive immediates are valid.
1502 return ErrorOperand(Start, "expected a positive immediate displacement "
1503 "before bracketed expr.");
1505 // Parse ImmDisp [ BaseReg + Scale*IndexReg + Disp ].
1506 return ParseIntelMemOperand(Imm, Start, Size);
1511 if (!ParseRegister(RegNo, Start, End)) {
1512 // If this is a segment register followed by a ':', then this is the start
1513 // of a segment override, otherwise this is a normal register reference.
1514 if (getLexer().isNot(AsmToken::Colon))
1515 return X86Operand::CreateReg(RegNo, Start, End);
1517 return ParseIntelSegmentOverride(/*SegReg=*/RegNo, Start, Size);
1521 return ParseIntelMemOperand(/*Disp=*/0, Start, Size);
1524 X86Operand *X86AsmParser::ParseATTOperand() {
1525 switch (getLexer().getKind()) {
1527 // Parse a memory operand with no segment register.
1528 return ParseMemOperand(0, Parser.getTok().getLoc());
1529 case AsmToken::Percent: {
1530 // Read the register.
1533 if (ParseRegister(RegNo, Start, End)) return 0;
1534 if (RegNo == X86::EIZ || RegNo == X86::RIZ) {
1535 Error(Start, "%eiz and %riz can only be used as index registers",
1536 SMRange(Start, End));
1540 // If this is a segment register followed by a ':', then this is the start
1541 // of a memory reference, otherwise this is a normal register reference.
1542 if (getLexer().isNot(AsmToken::Colon))
1543 return X86Operand::CreateReg(RegNo, Start, End);
1545 getParser().Lex(); // Eat the colon.
1546 return ParseMemOperand(RegNo, Start);
1548 case AsmToken::Dollar: {
1549 // $42 -> immediate.
1550 SMLoc Start = Parser.getTok().getLoc(), End;
1553 if (getParser().parseExpression(Val, End))
1555 return X86Operand::CreateImm(Val, Start, End);
1561 X86AsmParser::HandleAVX512Operand(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
1562 const MCParsedAsmOperand &Op) {
1563 if(STI.getFeatureBits() & X86::FeatureAVX512) {
1564 if (getLexer().is(AsmToken::LCurly)) {
1565 // Eat "{" and mark the current place.
1566 const SMLoc consumedToken = consumeToken();
1567 // Distinguish {1to<NUM>} from {%k<NUM>}.
1568 if(getLexer().is(AsmToken::Integer)) {
1569 // Parse memory broadcasting ({1to<NUM>}).
1570 if (getLexer().getTok().getIntVal() != 1)
1571 return !ErrorAndEatStatement(getLexer().getLoc(),
1572 "Expected 1to<NUM> at this point");
1573 Parser.Lex(); // Eat "1" of 1to8
1574 if (!getLexer().is(AsmToken::Identifier) ||
1575 !getLexer().getTok().getIdentifier().startswith("to"))
1576 return !ErrorAndEatStatement(getLexer().getLoc(),
1577 "Expected 1to<NUM> at this point");
1578 // Recognize only reasonable suffixes.
1579 const char *BroadcastPrimitive =
1580 StringSwitch<const char*>(getLexer().getTok().getIdentifier())
1581 .Case("to8", "{1to8}")
1582 .Case("to16", "{1to16}")
1584 if (!BroadcastPrimitive)
1585 return !ErrorAndEatStatement(getLexer().getLoc(),
1586 "Invalid memory broadcast primitive.");
1587 Parser.Lex(); // Eat "toN" of 1toN
1588 if (!getLexer().is(AsmToken::RCurly))
1589 return !ErrorAndEatStatement(getLexer().getLoc(),
1590 "Expected } at this point");
1591 Parser.Lex(); // Eat "}"
1592 Operands.push_back(X86Operand::CreateToken(BroadcastPrimitive,
1594 // No AVX512 specific primitives can pass
1595 // after memory broadcasting, so return.
1598 // Parse mask register {%k1}
1599 Operands.push_back(X86Operand::CreateToken("{", consumedToken));
1600 if (X86Operand *Op = ParseOperand()) {
1601 Operands.push_back(Op);
1602 if (!getLexer().is(AsmToken::RCurly))
1603 return !ErrorAndEatStatement(getLexer().getLoc(),
1604 "Expected } at this point");
1605 Operands.push_back(X86Operand::CreateToken("}", consumeToken()));
1607 // Parse "zeroing non-masked" semantic {z}
1608 if (getLexer().is(AsmToken::LCurly)) {
1609 Operands.push_back(X86Operand::CreateToken("{z}", consumeToken()));
1610 if (!getLexer().is(AsmToken::Identifier) ||
1611 getLexer().getTok().getIdentifier() != "z")
1612 return !ErrorAndEatStatement(getLexer().getLoc(),
1613 "Expected z at this point");
1614 Parser.Lex(); // Eat the z
1615 if (!getLexer().is(AsmToken::RCurly))
1616 return !ErrorAndEatStatement(getLexer().getLoc(),
1617 "Expected } at this point");
1618 Parser.Lex(); // Eat the }
1627 /// ParseMemOperand: segment: disp(basereg, indexreg, scale). The '%ds:' prefix
1628 /// has already been parsed if present.
1629 X86Operand *X86AsmParser::ParseMemOperand(unsigned SegReg, SMLoc MemStart) {
1631 // We have to disambiguate a parenthesized expression "(4+5)" from the start
1632 // of a memory operand with a missing displacement "(%ebx)" or "(,%eax)". The
1633 // only way to do this without lookahead is to eat the '(' and see what is
1635 const MCExpr *Disp = MCConstantExpr::Create(0, getParser().getContext());
1636 if (getLexer().isNot(AsmToken::LParen)) {
1638 if (getParser().parseExpression(Disp, ExprEnd)) return 0;
1640 // After parsing the base expression we could either have a parenthesized
1641 // memory address or not. If not, return now. If so, eat the (.
1642 if (getLexer().isNot(AsmToken::LParen)) {
1643 // Unless we have a segment register, treat this as an immediate.
1645 return X86Operand::CreateMem(Disp, MemStart, ExprEnd);
1646 return X86Operand::CreateMem(SegReg, Disp, 0, 0, 1, MemStart, ExprEnd);
1652 // Okay, we have a '('. We don't know if this is an expression or not, but
1653 // so we have to eat the ( to see beyond it.
1654 SMLoc LParenLoc = Parser.getTok().getLoc();
1655 Parser.Lex(); // Eat the '('.
1657 if (getLexer().is(AsmToken::Percent) || getLexer().is(AsmToken::Comma)) {
1658 // Nothing to do here, fall into the code below with the '(' part of the
1659 // memory operand consumed.
1663 // It must be an parenthesized expression, parse it now.
1664 if (getParser().parseParenExpression(Disp, ExprEnd))
1667 // After parsing the base expression we could either have a parenthesized
1668 // memory address or not. If not, return now. If so, eat the (.
1669 if (getLexer().isNot(AsmToken::LParen)) {
1670 // Unless we have a segment register, treat this as an immediate.
1672 return X86Operand::CreateMem(Disp, LParenLoc, ExprEnd);
1673 return X86Operand::CreateMem(SegReg, Disp, 0, 0, 1, MemStart, ExprEnd);
1681 // If we reached here, then we just ate the ( of the memory operand. Process
1682 // the rest of the memory operand.
1683 unsigned BaseReg = 0, IndexReg = 0, Scale = 1;
1684 SMLoc IndexLoc, BaseLoc;
1686 if (getLexer().is(AsmToken::Percent)) {
1687 SMLoc StartLoc, EndLoc;
1688 BaseLoc = Parser.getTok().getLoc();
1689 if (ParseRegister(BaseReg, StartLoc, EndLoc)) return 0;
1690 if (BaseReg == X86::EIZ || BaseReg == X86::RIZ) {
1691 Error(StartLoc, "eiz and riz can only be used as index registers",
1692 SMRange(StartLoc, EndLoc));
1697 if (getLexer().is(AsmToken::Comma)) {
1698 Parser.Lex(); // Eat the comma.
1699 IndexLoc = Parser.getTok().getLoc();
1701 // Following the comma we should have either an index register, or a scale
1702 // value. We don't support the later form, but we want to parse it
1705 // Not that even though it would be completely consistent to support syntax
1706 // like "1(%eax,,1)", the assembler doesn't. Use "eiz" or "riz" for this.
1707 if (getLexer().is(AsmToken::Percent)) {
1709 if (ParseRegister(IndexReg, L, L)) return 0;
1711 if (getLexer().isNot(AsmToken::RParen)) {
1712 // Parse the scale amount:
1713 // ::= ',' [scale-expression]
1714 if (getLexer().isNot(AsmToken::Comma)) {
1715 Error(Parser.getTok().getLoc(),
1716 "expected comma in scale expression");
1719 Parser.Lex(); // Eat the comma.
1721 if (getLexer().isNot(AsmToken::RParen)) {
1722 SMLoc Loc = Parser.getTok().getLoc();
1725 if (getParser().parseAbsoluteExpression(ScaleVal)){
1726 Error(Loc, "expected scale expression");
1730 // Validate the scale amount.
1731 if (X86MCRegisterClasses[X86::GR16RegClassID].contains(BaseReg) &&
1733 Error(Loc, "scale factor in 16-bit address must be 1");
1736 if (ScaleVal != 1 && ScaleVal != 2 && ScaleVal != 4 && ScaleVal != 8){
1737 Error(Loc, "scale factor in address must be 1, 2, 4 or 8");
1740 Scale = (unsigned)ScaleVal;
1743 } else if (getLexer().isNot(AsmToken::RParen)) {
1744 // A scale amount without an index is ignored.
1746 SMLoc Loc = Parser.getTok().getLoc();
1749 if (getParser().parseAbsoluteExpression(Value))
1753 Warning(Loc, "scale factor without index register is ignored");
1758 // Ok, we've eaten the memory operand, verify we have a ')' and eat it too.
1759 if (getLexer().isNot(AsmToken::RParen)) {
1760 Error(Parser.getTok().getLoc(), "unexpected token in memory operand");
1763 SMLoc MemEnd = Parser.getTok().getEndLoc();
1764 Parser.Lex(); // Eat the ')'.
1766 // Check for use of invalid 16-bit registers. Only BX/BP/SI/DI are allowed,
1767 // and then only in non-64-bit modes. Except for DX, which is a special case
1768 // because an unofficial form of in/out instructions uses it.
1769 if (X86MCRegisterClasses[X86::GR16RegClassID].contains(BaseReg) &&
1770 (is64BitMode() || (BaseReg != X86::BX && BaseReg != X86::BP &&
1771 BaseReg != X86::SI && BaseReg != X86::DI)) &&
1772 BaseReg != X86::DX) {
1773 Error(BaseLoc, "invalid 16-bit base register");
1777 X86MCRegisterClasses[X86::GR16RegClassID].contains(IndexReg)) {
1778 Error(IndexLoc, "16-bit memory operand may not include only index register");
1783 if (CheckBaseRegAndIndexReg(BaseReg, IndexReg, ErrMsg)) {
1784 Error(BaseLoc, ErrMsg);
1788 return X86Operand::CreateMem(SegReg, Disp, BaseReg, IndexReg, Scale,
1793 ParseInstruction(ParseInstructionInfo &Info, StringRef Name, SMLoc NameLoc,
1794 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1796 StringRef PatchedName = Name;
1798 // FIXME: Hack to recognize setneb as setne.
1799 if (PatchedName.startswith("set") && PatchedName.endswith("b") &&
1800 PatchedName != "setb" && PatchedName != "setnb")
1801 PatchedName = PatchedName.substr(0, Name.size()-1);
1803 // FIXME: Hack to recognize cmp<comparison code>{ss,sd,ps,pd}.
1804 const MCExpr *ExtraImmOp = 0;
1805 if ((PatchedName.startswith("cmp") || PatchedName.startswith("vcmp")) &&
1806 (PatchedName.endswith("ss") || PatchedName.endswith("sd") ||
1807 PatchedName.endswith("ps") || PatchedName.endswith("pd"))) {
1808 bool IsVCMP = PatchedName[0] == 'v';
1809 unsigned SSECCIdx = IsVCMP ? 4 : 3;
1810 unsigned SSEComparisonCode = StringSwitch<unsigned>(
1811 PatchedName.slice(SSECCIdx, PatchedName.size() - 2))
1815 .Case("unord", 0x03)
1820 /* AVX only from here */
1821 .Case("eq_uq", 0x08)
1824 .Case("false", 0x0B)
1825 .Case("neq_oq", 0x0C)
1829 .Case("eq_os", 0x10)
1830 .Case("lt_oq", 0x11)
1831 .Case("le_oq", 0x12)
1832 .Case("unord_s", 0x13)
1833 .Case("neq_us", 0x14)
1834 .Case("nlt_uq", 0x15)
1835 .Case("nle_uq", 0x16)
1836 .Case("ord_s", 0x17)
1837 .Case("eq_us", 0x18)
1838 .Case("nge_uq", 0x19)
1839 .Case("ngt_uq", 0x1A)
1840 .Case("false_os", 0x1B)
1841 .Case("neq_os", 0x1C)
1842 .Case("ge_oq", 0x1D)
1843 .Case("gt_oq", 0x1E)
1844 .Case("true_us", 0x1F)
1846 if (SSEComparisonCode != ~0U && (IsVCMP || SSEComparisonCode < 8)) {
1847 ExtraImmOp = MCConstantExpr::Create(SSEComparisonCode,
1848 getParser().getContext());
1849 if (PatchedName.endswith("ss")) {
1850 PatchedName = IsVCMP ? "vcmpss" : "cmpss";
1851 } else if (PatchedName.endswith("sd")) {
1852 PatchedName = IsVCMP ? "vcmpsd" : "cmpsd";
1853 } else if (PatchedName.endswith("ps")) {
1854 PatchedName = IsVCMP ? "vcmpps" : "cmpps";
1856 assert(PatchedName.endswith("pd") && "Unexpected mnemonic!");
1857 PatchedName = IsVCMP ? "vcmppd" : "cmppd";
1862 Operands.push_back(X86Operand::CreateToken(PatchedName, NameLoc));
1864 if (ExtraImmOp && !isParsingIntelSyntax())
1865 Operands.push_back(X86Operand::CreateImm(ExtraImmOp, NameLoc, NameLoc));
1867 // Determine whether this is an instruction prefix.
1869 Name == "lock" || Name == "rep" ||
1870 Name == "repe" || Name == "repz" ||
1871 Name == "repne" || Name == "repnz" ||
1872 Name == "rex64" || Name == "data16";
1875 // This does the actual operand parsing. Don't parse any more if we have a
1876 // prefix juxtaposed with an operation like "lock incl 4(%rax)", because we
1877 // just want to parse the "lock" as the first instruction and the "incl" as
1879 if (getLexer().isNot(AsmToken::EndOfStatement) && !isPrefix) {
1881 // Parse '*' modifier.
1882 if (getLexer().is(AsmToken::Star))
1883 Operands.push_back(X86Operand::CreateToken("*", consumeToken()));
1885 // Read the operands.
1887 if (X86Operand *Op = ParseOperand()) {
1888 Operands.push_back(Op);
1889 if (!HandleAVX512Operand(Operands, *Op))
1892 Parser.eatToEndOfStatement();
1895 // check for comma and eat it
1896 if (getLexer().is(AsmToken::Comma))
1902 if (getLexer().isNot(AsmToken::EndOfStatement))
1903 return ErrorAndEatStatement(getLexer().getLoc(),
1904 "unexpected token in argument list");
1907 // Consume the EndOfStatement or the prefix separator Slash
1908 if (getLexer().is(AsmToken::EndOfStatement) ||
1909 (isPrefix && getLexer().is(AsmToken::Slash)))
1912 if (ExtraImmOp && isParsingIntelSyntax())
1913 Operands.push_back(X86Operand::CreateImm(ExtraImmOp, NameLoc, NameLoc));
1915 // This is a terrible hack to handle "out[bwl]? %al, (%dx)" ->
1916 // "outb %al, %dx". Out doesn't take a memory form, but this is a widely
1917 // documented form in various unofficial manuals, so a lot of code uses it.
1918 if ((Name == "outb" || Name == "outw" || Name == "outl" || Name == "out") &&
1919 Operands.size() == 3) {
1920 X86Operand &Op = *(X86Operand*)Operands.back();
1921 if (Op.isMem() && Op.Mem.SegReg == 0 &&
1922 isa<MCConstantExpr>(Op.Mem.Disp) &&
1923 cast<MCConstantExpr>(Op.Mem.Disp)->getValue() == 0 &&
1924 Op.Mem.BaseReg == MatchRegisterName("dx") && Op.Mem.IndexReg == 0) {
1925 SMLoc Loc = Op.getEndLoc();
1926 Operands.back() = X86Operand::CreateReg(Op.Mem.BaseReg, Loc, Loc);
1930 // Same hack for "in[bwl]? (%dx), %al" -> "inb %dx, %al".
1931 if ((Name == "inb" || Name == "inw" || Name == "inl" || Name == "in") &&
1932 Operands.size() == 3) {
1933 X86Operand &Op = *(X86Operand*)Operands.begin()[1];
1934 if (Op.isMem() && Op.Mem.SegReg == 0 &&
1935 isa<MCConstantExpr>(Op.Mem.Disp) &&
1936 cast<MCConstantExpr>(Op.Mem.Disp)->getValue() == 0 &&
1937 Op.Mem.BaseReg == MatchRegisterName("dx") && Op.Mem.IndexReg == 0) {
1938 SMLoc Loc = Op.getEndLoc();
1939 Operands.begin()[1] = X86Operand::CreateReg(Op.Mem.BaseReg, Loc, Loc);
1944 // Append default arguments to "ins[bwld]"
1945 if (Name.startswith("ins") && Operands.size() == 1 &&
1946 (Name == "insb" || Name == "insw" || Name == "insl" ||
1948 if (isParsingIntelSyntax()) {
1949 Operands.push_back(X86Operand::CreateReg(X86::DX, NameLoc, NameLoc));
1950 Operands.push_back(DefaultMemDIOperand(NameLoc));
1952 Operands.push_back(X86Operand::CreateReg(X86::DX, NameLoc, NameLoc));
1953 Operands.push_back(DefaultMemDIOperand(NameLoc));
1957 // Append default arguments to "outs[bwld]"
1958 if (Name.startswith("outs") && Operands.size() == 1 &&
1959 (Name == "outsb" || Name == "outsw" || Name == "outsl" ||
1960 Name == "outsd" )) {
1961 if (isParsingIntelSyntax()) {
1962 Operands.push_back(DefaultMemSIOperand(NameLoc));
1963 Operands.push_back(X86Operand::CreateReg(X86::DX, NameLoc, NameLoc));
1965 Operands.push_back(DefaultMemSIOperand(NameLoc));
1966 Operands.push_back(X86Operand::CreateReg(X86::DX, NameLoc, NameLoc));
1970 // Transform "lods[bwlq]" into "lods[bwlq] ($SIREG)" for appropriate
1971 // values of $SIREG according to the mode. It would be nice if this
1972 // could be achieved with InstAlias in the tables.
1973 if (Name.startswith("lods") && Operands.size() == 1 &&
1974 (Name == "lods" || Name == "lodsb" || Name == "lodsw" ||
1975 Name == "lodsl" || Name == "lodsd" || Name == "lodsq"))
1976 Operands.push_back(DefaultMemSIOperand(NameLoc));
1978 // Transform "stos[bwlq]" into "stos[bwlq] ($DIREG)" for appropriate
1979 // values of $DIREG according to the mode. It would be nice if this
1980 // could be achieved with InstAlias in the tables.
1981 if (Name.startswith("stos") && Operands.size() == 1 &&
1982 (Name == "stos" || Name == "stosb" || Name == "stosw" ||
1983 Name == "stosl" || Name == "stosd" || Name == "stosq"))
1984 Operands.push_back(DefaultMemDIOperand(NameLoc));
1986 // Transform "scas[bwlq]" into "scas[bwlq] ($DIREG)" for appropriate
1987 // values of $DIREG according to the mode. It would be nice if this
1988 // could be achieved with InstAlias in the tables.
1989 if (Name.startswith("scas") && Operands.size() == 1 &&
1990 (Name == "scas" || Name == "scasb" || Name == "scasw" ||
1991 Name == "scasl" || Name == "scasd" || Name == "scasq"))
1992 Operands.push_back(DefaultMemDIOperand(NameLoc));
1994 // Add default SI and DI operands to "cmps[bwlq]".
1995 if (Name.startswith("cmps") &&
1996 (Name == "cmps" || Name == "cmpsb" || Name == "cmpsw" ||
1997 Name == "cmpsl" || Name == "cmpsd" || Name == "cmpsq")) {
1998 if (Operands.size() == 1) {
1999 if (isParsingIntelSyntax()) {
2000 Operands.push_back(DefaultMemSIOperand(NameLoc));
2001 Operands.push_back(DefaultMemDIOperand(NameLoc));
2003 Operands.push_back(DefaultMemDIOperand(NameLoc));
2004 Operands.push_back(DefaultMemSIOperand(NameLoc));
2006 } else if (Operands.size() == 3) {
2007 X86Operand &Op = *(X86Operand*)Operands.begin()[1];
2008 X86Operand &Op2 = *(X86Operand*)Operands.begin()[2];
2009 if (!doSrcDstMatch(Op, Op2))
2010 return Error(Op.getStartLoc(),
2011 "mismatching source and destination index registers");
2015 // Add default SI and DI operands to "movs[bwlq]".
2016 if ((Name.startswith("movs") &&
2017 (Name == "movs" || Name == "movsb" || Name == "movsw" ||
2018 Name == "movsl" || Name == "movsd" || Name == "movsq")) ||
2019 (Name.startswith("smov") &&
2020 (Name == "smov" || Name == "smovb" || Name == "smovw" ||
2021 Name == "smovl" || Name == "smovd" || Name == "smovq"))) {
2022 if (Operands.size() == 1) {
2023 if (Name == "movsd")
2024 Operands.back() = X86Operand::CreateToken("movsl", NameLoc);
2025 if (isParsingIntelSyntax()) {
2026 Operands.push_back(DefaultMemDIOperand(NameLoc));
2027 Operands.push_back(DefaultMemSIOperand(NameLoc));
2029 Operands.push_back(DefaultMemSIOperand(NameLoc));
2030 Operands.push_back(DefaultMemDIOperand(NameLoc));
2032 } else if (Operands.size() == 3) {
2033 X86Operand &Op = *(X86Operand*)Operands.begin()[1];
2034 X86Operand &Op2 = *(X86Operand*)Operands.begin()[2];
2035 if (!doSrcDstMatch(Op, Op2))
2036 return Error(Op.getStartLoc(),
2037 "mismatching source and destination index registers");
2041 // FIXME: Hack to handle recognize s{hr,ar,hl} $1, <op>. Canonicalize to
2043 if ((Name.startswith("shr") || Name.startswith("sar") ||
2044 Name.startswith("shl") || Name.startswith("sal") ||
2045 Name.startswith("rcl") || Name.startswith("rcr") ||
2046 Name.startswith("rol") || Name.startswith("ror")) &&
2047 Operands.size() == 3) {
2048 if (isParsingIntelSyntax()) {
2050 X86Operand *Op1 = static_cast<X86Operand*>(Operands[2]);
2051 if (Op1->isImm() && isa<MCConstantExpr>(Op1->getImm()) &&
2052 cast<MCConstantExpr>(Op1->getImm())->getValue() == 1) {
2054 Operands.pop_back();
2057 X86Operand *Op1 = static_cast<X86Operand*>(Operands[1]);
2058 if (Op1->isImm() && isa<MCConstantExpr>(Op1->getImm()) &&
2059 cast<MCConstantExpr>(Op1->getImm())->getValue() == 1) {
2061 Operands.erase(Operands.begin() + 1);
2066 // Transforms "int $3" into "int3" as a size optimization. We can't write an
2067 // instalias with an immediate operand yet.
2068 if (Name == "int" && Operands.size() == 2) {
2069 X86Operand *Op1 = static_cast<X86Operand*>(Operands[1]);
2070 if (Op1->isImm() && isa<MCConstantExpr>(Op1->getImm()) &&
2071 cast<MCConstantExpr>(Op1->getImm())->getValue() == 3) {
2073 Operands.erase(Operands.begin() + 1);
2074 static_cast<X86Operand*>(Operands[0])->setTokenValue("int3");
2081 static bool convertToSExti8(MCInst &Inst, unsigned Opcode, unsigned Reg,
2084 TmpInst.setOpcode(Opcode);
2086 TmpInst.addOperand(MCOperand::CreateReg(Reg));
2087 TmpInst.addOperand(MCOperand::CreateReg(Reg));
2088 TmpInst.addOperand(Inst.getOperand(0));
2093 static bool convert16i16to16ri8(MCInst &Inst, unsigned Opcode,
2094 bool isCmp = false) {
2095 if (!Inst.getOperand(0).isImm() ||
2096 !isImmSExti16i8Value(Inst.getOperand(0).getImm()))
2099 return convertToSExti8(Inst, Opcode, X86::AX, isCmp);
2102 static bool convert32i32to32ri8(MCInst &Inst, unsigned Opcode,
2103 bool isCmp = false) {
2104 if (!Inst.getOperand(0).isImm() ||
2105 !isImmSExti32i8Value(Inst.getOperand(0).getImm()))
2108 return convertToSExti8(Inst, Opcode, X86::EAX, isCmp);
2111 static bool convert64i32to64ri8(MCInst &Inst, unsigned Opcode,
2112 bool isCmp = false) {
2113 if (!Inst.getOperand(0).isImm() ||
2114 !isImmSExti64i8Value(Inst.getOperand(0).getImm()))
2117 return convertToSExti8(Inst, Opcode, X86::RAX, isCmp);
2121 processInstruction(MCInst &Inst,
2122 const SmallVectorImpl<MCParsedAsmOperand*> &Ops) {
2123 switch (Inst.getOpcode()) {
2124 default: return false;
2125 case X86::AND16i16: return convert16i16to16ri8(Inst, X86::AND16ri8);
2126 case X86::AND32i32: return convert32i32to32ri8(Inst, X86::AND32ri8);
2127 case X86::AND64i32: return convert64i32to64ri8(Inst, X86::AND64ri8);
2128 case X86::XOR16i16: return convert16i16to16ri8(Inst, X86::XOR16ri8);
2129 case X86::XOR32i32: return convert32i32to32ri8(Inst, X86::XOR32ri8);
2130 case X86::XOR64i32: return convert64i32to64ri8(Inst, X86::XOR64ri8);
2131 case X86::OR16i16: return convert16i16to16ri8(Inst, X86::OR16ri8);
2132 case X86::OR32i32: return convert32i32to32ri8(Inst, X86::OR32ri8);
2133 case X86::OR64i32: return convert64i32to64ri8(Inst, X86::OR64ri8);
2134 case X86::CMP16i16: return convert16i16to16ri8(Inst, X86::CMP16ri8, true);
2135 case X86::CMP32i32: return convert32i32to32ri8(Inst, X86::CMP32ri8, true);
2136 case X86::CMP64i32: return convert64i32to64ri8(Inst, X86::CMP64ri8, true);
2137 case X86::ADD16i16: return convert16i16to16ri8(Inst, X86::ADD16ri8);
2138 case X86::ADD32i32: return convert32i32to32ri8(Inst, X86::ADD32ri8);
2139 case X86::ADD64i32: return convert64i32to64ri8(Inst, X86::ADD64ri8);
2140 case X86::SUB16i16: return convert16i16to16ri8(Inst, X86::SUB16ri8);
2141 case X86::SUB32i32: return convert32i32to32ri8(Inst, X86::SUB32ri8);
2142 case X86::SUB64i32: return convert64i32to64ri8(Inst, X86::SUB64ri8);
2143 case X86::ADC16i16: return convert16i16to16ri8(Inst, X86::ADC16ri8);
2144 case X86::ADC32i32: return convert32i32to32ri8(Inst, X86::ADC32ri8);
2145 case X86::ADC64i32: return convert64i32to64ri8(Inst, X86::ADC64ri8);
2146 case X86::SBB16i16: return convert16i16to16ri8(Inst, X86::SBB16ri8);
2147 case X86::SBB32i32: return convert32i32to32ri8(Inst, X86::SBB32ri8);
2148 case X86::SBB64i32: return convert64i32to64ri8(Inst, X86::SBB64ri8);
2149 case X86::VMOVAPDrr:
2150 case X86::VMOVAPDYrr:
2151 case X86::VMOVAPSrr:
2152 case X86::VMOVAPSYrr:
2153 case X86::VMOVDQArr:
2154 case X86::VMOVDQAYrr:
2155 case X86::VMOVDQUrr:
2156 case X86::VMOVDQUYrr:
2157 case X86::VMOVUPDrr:
2158 case X86::VMOVUPDYrr:
2159 case X86::VMOVUPSrr:
2160 case X86::VMOVUPSYrr: {
2161 if (X86II::isX86_64ExtendedReg(Inst.getOperand(0).getReg()) ||
2162 !X86II::isX86_64ExtendedReg(Inst.getOperand(1).getReg()))
2166 switch (Inst.getOpcode()) {
2167 default: llvm_unreachable("Invalid opcode");
2168 case X86::VMOVAPDrr: NewOpc = X86::VMOVAPDrr_REV; break;
2169 case X86::VMOVAPDYrr: NewOpc = X86::VMOVAPDYrr_REV; break;
2170 case X86::VMOVAPSrr: NewOpc = X86::VMOVAPSrr_REV; break;
2171 case X86::VMOVAPSYrr: NewOpc = X86::VMOVAPSYrr_REV; break;
2172 case X86::VMOVDQArr: NewOpc = X86::VMOVDQArr_REV; break;
2173 case X86::VMOVDQAYrr: NewOpc = X86::VMOVDQAYrr_REV; break;
2174 case X86::VMOVDQUrr: NewOpc = X86::VMOVDQUrr_REV; break;
2175 case X86::VMOVDQUYrr: NewOpc = X86::VMOVDQUYrr_REV; break;
2176 case X86::VMOVUPDrr: NewOpc = X86::VMOVUPDrr_REV; break;
2177 case X86::VMOVUPDYrr: NewOpc = X86::VMOVUPDYrr_REV; break;
2178 case X86::VMOVUPSrr: NewOpc = X86::VMOVUPSrr_REV; break;
2179 case X86::VMOVUPSYrr: NewOpc = X86::VMOVUPSYrr_REV; break;
2181 Inst.setOpcode(NewOpc);
2185 case X86::VMOVSSrr: {
2186 if (X86II::isX86_64ExtendedReg(Inst.getOperand(0).getReg()) ||
2187 !X86II::isX86_64ExtendedReg(Inst.getOperand(2).getReg()))
2190 switch (Inst.getOpcode()) {
2191 default: llvm_unreachable("Invalid opcode");
2192 case X86::VMOVSDrr: NewOpc = X86::VMOVSDrr_REV; break;
2193 case X86::VMOVSSrr: NewOpc = X86::VMOVSSrr_REV; break;
2195 Inst.setOpcode(NewOpc);
2201 static const char *getSubtargetFeatureName(unsigned Val);
2203 MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
2204 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
2205 MCStreamer &Out, unsigned &ErrorInfo,
2206 bool MatchingInlineAsm) {
2207 assert(!Operands.empty() && "Unexpect empty operand list!");
2208 X86Operand *Op = static_cast<X86Operand*>(Operands[0]);
2209 assert(Op->isToken() && "Leading operand should always be a mnemonic!");
2210 ArrayRef<SMRange> EmptyRanges = None;
2212 // First, handle aliases that expand to multiple instructions.
2213 // FIXME: This should be replaced with a real .td file alias mechanism.
2214 // Also, MatchInstructionImpl should actually *do* the EmitInstruction
2216 if (Op->getToken() == "fstsw" || Op->getToken() == "fstcw" ||
2217 Op->getToken() == "fstsww" || Op->getToken() == "fstcww" ||
2218 Op->getToken() == "finit" || Op->getToken() == "fsave" ||
2219 Op->getToken() == "fstenv" || Op->getToken() == "fclex") {
2221 Inst.setOpcode(X86::WAIT);
2223 if (!MatchingInlineAsm)
2224 Out.EmitInstruction(Inst, STI);
2227 StringSwitch<const char*>(Op->getToken())
2228 .Case("finit", "fninit")
2229 .Case("fsave", "fnsave")
2230 .Case("fstcw", "fnstcw")
2231 .Case("fstcww", "fnstcw")
2232 .Case("fstenv", "fnstenv")
2233 .Case("fstsw", "fnstsw")
2234 .Case("fstsww", "fnstsw")
2235 .Case("fclex", "fnclex")
2237 assert(Repl && "Unknown wait-prefixed instruction");
2239 Operands[0] = X86Operand::CreateToken(Repl, IDLoc);
2242 bool WasOriginallyInvalidOperand = false;
2245 // First, try a direct match.
2246 switch (MatchInstructionImpl(Operands, Inst,
2247 ErrorInfo, MatchingInlineAsm,
2248 isParsingIntelSyntax())) {
2251 // Some instructions need post-processing to, for example, tweak which
2252 // encoding is selected. Loop on it while changes happen so the
2253 // individual transformations can chain off each other.
2254 if (!MatchingInlineAsm)
2255 while (processInstruction(Inst, Operands))
2259 if (!MatchingInlineAsm)
2260 Out.EmitInstruction(Inst, STI);
2261 Opcode = Inst.getOpcode();
2263 case Match_MissingFeature: {
2264 assert(ErrorInfo && "Unknown missing feature!");
2265 // Special case the error message for the very common case where only
2266 // a single subtarget feature is missing.
2267 std::string Msg = "instruction requires:";
2269 for (unsigned i = 0; i < (sizeof(ErrorInfo)*8-1); ++i) {
2270 if (ErrorInfo & Mask) {
2272 Msg += getSubtargetFeatureName(ErrorInfo & Mask);
2276 return Error(IDLoc, Msg, EmptyRanges, MatchingInlineAsm);
2278 case Match_InvalidOperand:
2279 WasOriginallyInvalidOperand = true;
2281 case Match_MnemonicFail:
2285 // FIXME: Ideally, we would only attempt suffix matches for things which are
2286 // valid prefixes, and we could just infer the right unambiguous
2287 // type. However, that requires substantially more matcher support than the
2290 // Change the operand to point to a temporary token.
2291 StringRef Base = Op->getToken();
2292 SmallString<16> Tmp;
2295 Op->setTokenValue(Tmp.str());
2297 // If this instruction starts with an 'f', then it is a floating point stack
2298 // instruction. These come in up to three forms for 32-bit, 64-bit, and
2299 // 80-bit floating point, which use the suffixes s,l,t respectively.
2301 // Otherwise, we assume that this may be an integer instruction, which comes
2302 // in 8/16/32/64-bit forms using the b,w,l,q suffixes respectively.
2303 const char *Suffixes = Base[0] != 'f' ? "bwlq" : "slt\0";
2305 // Check for the various suffix matches.
2306 Tmp[Base.size()] = Suffixes[0];
2307 unsigned ErrorInfoIgnore;
2308 unsigned ErrorInfoMissingFeature = 0; // Init suppresses compiler warnings.
2309 unsigned Match1, Match2, Match3, Match4;
2311 Match1 = MatchInstructionImpl(Operands, Inst, ErrorInfoIgnore,
2312 MatchingInlineAsm, isParsingIntelSyntax());
2313 // If this returned as a missing feature failure, remember that.
2314 if (Match1 == Match_MissingFeature)
2315 ErrorInfoMissingFeature = ErrorInfoIgnore;
2316 Tmp[Base.size()] = Suffixes[1];
2317 Match2 = MatchInstructionImpl(Operands, Inst, ErrorInfoIgnore,
2318 MatchingInlineAsm, isParsingIntelSyntax());
2319 // If this returned as a missing feature failure, remember that.
2320 if (Match2 == Match_MissingFeature)
2321 ErrorInfoMissingFeature = ErrorInfoIgnore;
2322 Tmp[Base.size()] = Suffixes[2];
2323 Match3 = MatchInstructionImpl(Operands, Inst, ErrorInfoIgnore,
2324 MatchingInlineAsm, isParsingIntelSyntax());
2325 // If this returned as a missing feature failure, remember that.
2326 if (Match3 == Match_MissingFeature)
2327 ErrorInfoMissingFeature = ErrorInfoIgnore;
2328 Tmp[Base.size()] = Suffixes[3];
2329 Match4 = MatchInstructionImpl(Operands, Inst, ErrorInfoIgnore,
2330 MatchingInlineAsm, isParsingIntelSyntax());
2331 // If this returned as a missing feature failure, remember that.
2332 if (Match4 == Match_MissingFeature)
2333 ErrorInfoMissingFeature = ErrorInfoIgnore;
2335 // Restore the old token.
2336 Op->setTokenValue(Base);
2338 // If exactly one matched, then we treat that as a successful match (and the
2339 // instruction will already have been filled in correctly, since the failing
2340 // matches won't have modified it).
2341 unsigned NumSuccessfulMatches =
2342 (Match1 == Match_Success) + (Match2 == Match_Success) +
2343 (Match3 == Match_Success) + (Match4 == Match_Success);
2344 if (NumSuccessfulMatches == 1) {
2346 if (!MatchingInlineAsm)
2347 Out.EmitInstruction(Inst, STI);
2348 Opcode = Inst.getOpcode();
2352 // Otherwise, the match failed, try to produce a decent error message.
2354 // If we had multiple suffix matches, then identify this as an ambiguous
2356 if (NumSuccessfulMatches > 1) {
2358 unsigned NumMatches = 0;
2359 if (Match1 == Match_Success) MatchChars[NumMatches++] = Suffixes[0];
2360 if (Match2 == Match_Success) MatchChars[NumMatches++] = Suffixes[1];
2361 if (Match3 == Match_Success) MatchChars[NumMatches++] = Suffixes[2];
2362 if (Match4 == Match_Success) MatchChars[NumMatches++] = Suffixes[3];
2364 SmallString<126> Msg;
2365 raw_svector_ostream OS(Msg);
2366 OS << "ambiguous instructions require an explicit suffix (could be ";
2367 for (unsigned i = 0; i != NumMatches; ++i) {
2370 if (i + 1 == NumMatches)
2372 OS << "'" << Base << MatchChars[i] << "'";
2375 Error(IDLoc, OS.str(), EmptyRanges, MatchingInlineAsm);
2379 // Okay, we know that none of the variants matched successfully.
2381 // If all of the instructions reported an invalid mnemonic, then the original
2382 // mnemonic was invalid.
2383 if ((Match1 == Match_MnemonicFail) && (Match2 == Match_MnemonicFail) &&
2384 (Match3 == Match_MnemonicFail) && (Match4 == Match_MnemonicFail)) {
2385 if (!WasOriginallyInvalidOperand) {
2386 ArrayRef<SMRange> Ranges = MatchingInlineAsm ? EmptyRanges :
2388 return Error(IDLoc, "invalid instruction mnemonic '" + Base + "'",
2389 Ranges, MatchingInlineAsm);
2392 // Recover location info for the operand if we know which was the problem.
2393 if (ErrorInfo != ~0U) {
2394 if (ErrorInfo >= Operands.size())
2395 return Error(IDLoc, "too few operands for instruction",
2396 EmptyRanges, MatchingInlineAsm);
2398 X86Operand *Operand = (X86Operand*)Operands[ErrorInfo];
2399 if (Operand->getStartLoc().isValid()) {
2400 SMRange OperandRange = Operand->getLocRange();
2401 return Error(Operand->getStartLoc(), "invalid operand for instruction",
2402 OperandRange, MatchingInlineAsm);
2406 return Error(IDLoc, "invalid operand for instruction", EmptyRanges,
2410 // If one instruction matched with a missing feature, report this as a
2412 if ((Match1 == Match_MissingFeature) + (Match2 == Match_MissingFeature) +
2413 (Match3 == Match_MissingFeature) + (Match4 == Match_MissingFeature) == 1){
2414 std::string Msg = "instruction requires:";
2416 for (unsigned i = 0; i < (sizeof(ErrorInfoMissingFeature)*8-1); ++i) {
2417 if (ErrorInfoMissingFeature & Mask) {
2419 Msg += getSubtargetFeatureName(ErrorInfoMissingFeature & Mask);
2423 return Error(IDLoc, Msg, EmptyRanges, MatchingInlineAsm);
2426 // If one instruction matched with an invalid operand, report this as an
2428 if ((Match1 == Match_InvalidOperand) + (Match2 == Match_InvalidOperand) +
2429 (Match3 == Match_InvalidOperand) + (Match4 == Match_InvalidOperand) == 1){
2430 Error(IDLoc, "invalid operand for instruction", EmptyRanges,
2435 // If all of these were an outright failure, report it in a useless way.
2436 Error(IDLoc, "unknown use of instruction mnemonic without a size suffix",
2437 EmptyRanges, MatchingInlineAsm);
2442 bool X86AsmParser::ParseDirective(AsmToken DirectiveID) {
2443 StringRef IDVal = DirectiveID.getIdentifier();
2444 if (IDVal == ".word")
2445 return ParseDirectiveWord(2, DirectiveID.getLoc());
2446 else if (IDVal.startswith(".code"))
2447 return ParseDirectiveCode(IDVal, DirectiveID.getLoc());
2448 else if (IDVal.startswith(".att_syntax")) {
2449 getParser().setAssemblerDialect(0);
2451 } else if (IDVal.startswith(".intel_syntax")) {
2452 getParser().setAssemblerDialect(1);
2453 if (getLexer().isNot(AsmToken::EndOfStatement)) {
2454 // FIXME: Handle noprefix
2455 if (Parser.getTok().getString() == "noprefix")
2463 /// ParseDirectiveWord
2464 /// ::= .word [ expression (, expression)* ]
2465 bool X86AsmParser::ParseDirectiveWord(unsigned Size, SMLoc L) {
2466 if (getLexer().isNot(AsmToken::EndOfStatement)) {
2468 const MCExpr *Value;
2469 if (getParser().parseExpression(Value))
2472 getParser().getStreamer().EmitValue(Value, Size);
2474 if (getLexer().is(AsmToken::EndOfStatement))
2477 // FIXME: Improve diagnostic.
2478 if (getLexer().isNot(AsmToken::Comma)) {
2479 Error(L, "unexpected token in directive");
2490 /// ParseDirectiveCode
2491 /// ::= .code16 | .code32 | .code64
2492 bool X86AsmParser::ParseDirectiveCode(StringRef IDVal, SMLoc L) {
2493 if (IDVal == ".code16") {
2495 if (!is16BitMode()) {
2496 SwitchMode(X86::Mode16Bit);
2497 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
2499 } else if (IDVal == ".code32") {
2501 if (!is32BitMode()) {
2502 SwitchMode(X86::Mode32Bit);
2503 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
2505 } else if (IDVal == ".code64") {
2507 if (!is64BitMode()) {
2508 SwitchMode(X86::Mode64Bit);
2509 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code64);
2512 Error(L, "unknown directive " + IDVal);
2519 // Force static initialization.
2520 extern "C" void LLVMInitializeX86AsmParser() {
2521 RegisterMCAsmParser<X86AsmParser> X(TheX86_32Target);
2522 RegisterMCAsmParser<X86AsmParser> Y(TheX86_64Target);
2525 #define GET_REGISTER_MATCHER
2526 #define GET_MATCHER_IMPLEMENTATION
2527 #define GET_SUBTARGET_FEATURE_NAME
2528 #include "X86GenAsmMatcher.inc"