1 //===-- X86AsmParser.cpp - Parse X86 assembly to MCInst instructions ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 #include "llvm/ADT/SmallVector.h"
12 #include "llvm/ADT/Twine.h"
13 #include "llvm/MC/MCAsmLexer.h"
14 #include "llvm/MC/MCAsmParser.h"
15 #include "llvm/MC/MCInst.h"
16 #include "llvm/MC/MCValue.h"
17 #include "llvm/Support/SourceMgr.h"
18 #include "llvm/Target/TargetRegistry.h"
19 #include "llvm/Target/TargetAsmParser.h"
25 class X86ATTAsmParser : public TargetAsmParser {
29 MCAsmParser &getParser() const { return Parser; }
31 MCAsmLexer &getLexer() const { return Parser.getLexer(); }
33 void Warning(SMLoc L, const Twine &Msg) { Parser.Warning(L, Msg); }
35 bool Error(SMLoc L, const Twine &Msg) { return Parser.Error(L, Msg); }
37 bool ParseRegister(X86Operand &Op);
39 bool ParseOperand(X86Operand &Op);
41 bool ParseMemOperand(X86Operand &Op);
43 /// @name Auto-generated Match Functions
46 bool MatchInstruction(SmallVectorImpl<X86Operand> &Operands,
49 bool MatchRegisterName(const StringRef &Name, unsigned &RegNo);
54 X86ATTAsmParser(const Target &T, MCAsmParser &_Parser)
55 : TargetAsmParser(T), Parser(_Parser) {}
57 virtual bool ParseInstruction(const StringRef &Name, MCInst &Inst);
60 } // end anonymous namespace
65 /// X86Operand - Instances of this class represent a parsed X86 machine
98 StringRef getToken() const {
99 assert(Kind == Token && "Invalid access!");
100 return StringRef(Tok.Data, Tok.Length);
103 unsigned getReg() const {
104 assert(Kind == Register && "Invalid access!");
108 const MCValue &getImm() const {
109 assert(Kind == Immediate && "Invalid access!");
113 const MCValue &getMemDisp() const {
114 assert(Kind == Memory && "Invalid access!");
117 unsigned getMemSegReg() const {
118 assert(Kind == Memory && "Invalid access!");
121 unsigned getMemBaseReg() const {
122 assert(Kind == Memory && "Invalid access!");
125 unsigned getMemIndexReg() const {
126 assert(Kind == Memory && "Invalid access!");
129 unsigned getMemScale() const {
130 assert(Kind == Memory && "Invalid access!");
134 bool isToken(const StringRef &Str) const {
135 return Kind == Token && Str == getToken();
138 bool isImm() const { return Kind == Immediate; }
140 bool isMem() const { return Kind == Memory; }
142 bool isReg() const { return Kind == Register; }
144 void addRegOperands(MCInst &Inst, unsigned N) {
145 assert(N == 1 && "Invalid number of operands!");
146 Inst.addOperand(MCOperand::CreateReg(getReg()));
149 void addImmOperands(MCInst &Inst, unsigned N) {
150 assert(N == 1 && "Invalid number of operands!");
151 Inst.addOperand(MCOperand::CreateMCValue(getImm()));
154 void addMemOperands(MCInst &Inst, unsigned N) {
155 assert((N == 4 || N == 5) && "Invalid number of operands!");
157 Inst.addOperand(MCOperand::CreateReg(getMemBaseReg()));
158 Inst.addOperand(MCOperand::CreateImm(getMemScale()));
159 Inst.addOperand(MCOperand::CreateReg(getMemIndexReg()));
160 Inst.addOperand(MCOperand::CreateMCValue(getMemDisp()));
162 // FIXME: What a hack.
164 Inst.addOperand(MCOperand::CreateReg(getMemSegReg()));
167 static X86Operand CreateToken(StringRef Str) {
170 Res.Tok.Data = Str.data();
171 Res.Tok.Length = Str.size();
175 static X86Operand CreateReg(unsigned RegNo) {
178 Res.Reg.RegNo = RegNo;
182 static X86Operand CreateImm(MCValue Val) {
184 Res.Kind = Immediate;
189 static X86Operand CreateMem(unsigned SegReg, MCValue Disp, unsigned BaseReg,
190 unsigned IndexReg, unsigned Scale) {
191 // We should never just have a displacement, that would be an immediate.
192 assert((SegReg || BaseReg || IndexReg) && "Invalid memory operand!");
194 // The scale should always be one of {1,2,4,8}.
195 assert(((Scale == 1 || Scale == 2 || Scale == 4 || Scale == 8)) &&
199 Res.Mem.SegReg = SegReg;
201 Res.Mem.BaseReg = BaseReg;
202 Res.Mem.IndexReg = IndexReg;
203 Res.Mem.Scale = Scale;
208 } // end anonymous namespace.
211 bool X86ATTAsmParser::ParseRegister(X86Operand &Op) {
212 const AsmToken &Tok = getLexer().getTok();
213 assert(Tok.is(AsmToken::Register) && "Invalid token kind!");
215 // FIXME: Validate register for the current architecture; we have to do
216 // validation later, so maybe there is no need for this here.
218 assert(Tok.getString().startswith("%") && "Invalid register name!");
219 if (MatchRegisterName(Tok.getString().substr(1), RegNo))
220 return Error(Tok.getLoc(), "invalid register name");
222 Op = X86Operand::CreateReg(RegNo);
223 getLexer().Lex(); // Eat register token.
228 bool X86ATTAsmParser::ParseOperand(X86Operand &Op) {
229 switch (getLexer().getKind()) {
231 return ParseMemOperand(Op);
232 case AsmToken::Register:
233 // FIXME: if a segment register, this could either be just the seg reg, or
234 // the start of a memory operand.
235 return ParseRegister(Op);
236 case AsmToken::Dollar: {
240 if (getParser().ParseRelocatableExpression(Val))
242 Op = X86Operand::CreateImm(Val);
246 getLexer().Lex(); // Eat the star.
248 if (getLexer().is(AsmToken::Register)) {
249 if (ParseRegister(Op))
251 } else if (ParseMemOperand(Op))
254 // FIXME: Note the '*' in the operand for use by the matcher.
259 /// ParseMemOperand: segment: disp(basereg, indexreg, scale)
260 bool X86ATTAsmParser::ParseMemOperand(X86Operand &Op) {
261 // FIXME: If SegReg ':' (e.g. %gs:), eat and remember.
264 // We have to disambiguate a parenthesized expression "(4+5)" from the start
265 // of a memory operand with a missing displacement "(%ebx)" or "(,%eax)". The
266 // only way to do this without lookahead is to eat the ( and see what is after
268 MCValue Disp = MCValue::get(0, 0, 0);
269 if (getLexer().isNot(AsmToken::LParen)) {
270 if (getParser().ParseRelocatableExpression(Disp)) return true;
272 // After parsing the base expression we could either have a parenthesized
273 // memory address or not. If not, return now. If so, eat the (.
274 if (getLexer().isNot(AsmToken::LParen)) {
275 // Unless we have a segment register, treat this as an immediate.
277 Op = X86Operand::CreateMem(SegReg, Disp, 0, 0, 1);
279 Op = X86Operand::CreateImm(Disp);
286 // Okay, we have a '('. We don't know if this is an expression or not, but
287 // so we have to eat the ( to see beyond it.
288 getLexer().Lex(); // Eat the '('.
290 if (getLexer().is(AsmToken::Register) || getLexer().is(AsmToken::Comma)) {
291 // Nothing to do here, fall into the code below with the '(' part of the
292 // memory operand consumed.
294 // It must be an parenthesized expression, parse it now.
295 if (getParser().ParseParenRelocatableExpression(Disp))
298 // After parsing the base expression we could either have a parenthesized
299 // memory address or not. If not, return now. If so, eat the (.
300 if (getLexer().isNot(AsmToken::LParen)) {
301 // Unless we have a segment register, treat this as an immediate.
303 Op = X86Operand::CreateMem(SegReg, Disp, 0, 0, 1);
305 Op = X86Operand::CreateImm(Disp);
314 // If we reached here, then we just ate the ( of the memory operand. Process
315 // the rest of the memory operand.
316 unsigned BaseReg = 0, IndexReg = 0, Scale = 1;
318 if (getLexer().is(AsmToken::Register)) {
319 if (ParseRegister(Op))
321 BaseReg = Op.getReg();
324 if (getLexer().is(AsmToken::Comma)) {
325 getLexer().Lex(); // Eat the comma.
327 // Following the comma we should have either an index register, or a scale
328 // value. We don't support the later form, but we want to parse it
331 // Not that even though it would be completely consistent to support syntax
332 // like "1(%eax,,1)", the assembler doesn't.
333 if (getLexer().is(AsmToken::Register)) {
334 if (ParseRegister(Op))
336 IndexReg = Op.getReg();
338 if (getLexer().isNot(AsmToken::RParen)) {
339 // Parse the scale amount:
340 // ::= ',' [scale-expression]
341 if (getLexer().isNot(AsmToken::Comma))
343 getLexer().Lex(); // Eat the comma.
345 if (getLexer().isNot(AsmToken::RParen)) {
346 SMLoc Loc = getLexer().getTok().getLoc();
349 if (getParser().ParseAbsoluteExpression(ScaleVal))
352 // Validate the scale amount.
353 if (ScaleVal != 1 && ScaleVal != 2 && ScaleVal != 4 && ScaleVal != 8)
354 return Error(Loc, "scale factor in address must be 1, 2, 4 or 8");
355 Scale = (unsigned)ScaleVal;
358 } else if (getLexer().isNot(AsmToken::RParen)) {
359 // Otherwise we have the unsupported form of a scale amount without an
361 SMLoc Loc = getLexer().getTok().getLoc();
364 if (getParser().ParseAbsoluteExpression(Value))
367 return Error(Loc, "cannot have scale factor without index register");
371 // Ok, we've eaten the memory operand, verify we have a ')' and eat it too.
372 if (getLexer().isNot(AsmToken::RParen))
373 return Error(getLexer().getTok().getLoc(),
374 "unexpected token in memory operand");
375 getLexer().Lex(); // Eat the ')'.
377 Op = X86Operand::CreateMem(SegReg, Disp, BaseReg, IndexReg, Scale);
381 bool X86ATTAsmParser::ParseInstruction(const StringRef &Name, MCInst &Inst) {
382 SmallVector<X86Operand, 8> Operands;
384 Operands.push_back(X86Operand::CreateToken(Name));
386 SMLoc Loc = getLexer().getTok().getLoc();
387 if (getLexer().isNot(AsmToken::EndOfStatement)) {
388 // Read the first operand.
389 Operands.push_back(X86Operand());
390 if (ParseOperand(Operands.back()))
393 while (getLexer().is(AsmToken::Comma)) {
394 getLexer().Lex(); // Eat the comma.
396 // Parse and remember the operand.
397 Operands.push_back(X86Operand());
398 if (ParseOperand(Operands.back()))
403 if (!MatchInstruction(Operands, Inst))
406 // FIXME: We should give nicer diagnostics about the exact failure.
408 // FIXME: For now we just treat unrecognized instructions as "warnings".
409 Warning(Loc, "unrecognized instruction");
414 // Force static initialization.
415 extern "C" void LLVMInitializeX86AsmParser() {
416 RegisterAsmParser<X86ATTAsmParser> X(TheX86_32Target);
417 RegisterAsmParser<X86ATTAsmParser> Y(TheX86_64Target);
420 // FIXME: Disabled for now, this is causing gcc-4.0 to run out of memory during
424 #include "X86GenAsmMatcher.inc"
428 bool X86ATTAsmParser::MatchInstruction(SmallVectorImpl<X86Operand> &Operands,
433 bool X86ATTAsmParser::MatchRegisterName(const StringRef &Name,