1 //===-- X86AsmParser.cpp - Parse X86 assembly to MCInst instructions ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "MCTargetDesc/X86BaseInfo.h"
11 #include "llvm/ADT/APFloat.h"
12 #include "llvm/ADT/SmallString.h"
13 #include "llvm/ADT/SmallVector.h"
14 #include "llvm/ADT/StringSwitch.h"
15 #include "llvm/ADT/Twine.h"
16 #include "llvm/MC/MCContext.h"
17 #include "llvm/MC/MCExpr.h"
18 #include "llvm/MC/MCInst.h"
19 #include "llvm/MC/MCParser/MCAsmLexer.h"
20 #include "llvm/MC/MCParser/MCAsmParser.h"
21 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
22 #include "llvm/MC/MCRegisterInfo.h"
23 #include "llvm/MC/MCStreamer.h"
24 #include "llvm/MC/MCSubtargetInfo.h"
25 #include "llvm/MC/MCSymbol.h"
26 #include "llvm/MC/MCTargetAsmParser.h"
27 #include "llvm/Support/SourceMgr.h"
28 #include "llvm/Support/TargetRegistry.h"
29 #include "llvm/Support/raw_ostream.h"
36 class X86AsmParser : public MCTargetAsmParser {
39 ParseInstructionInfo *InstInfo;
41 MCAsmParser &getParser() const { return Parser; }
43 MCAsmLexer &getLexer() const { return Parser.getLexer(); }
45 bool Error(SMLoc L, const Twine &Msg,
46 ArrayRef<SMRange> Ranges = ArrayRef<SMRange>(),
47 bool MatchingInlineAsm = false) {
48 if (MatchingInlineAsm) return true;
49 return Parser.Error(L, Msg, Ranges);
52 X86Operand *ErrorOperand(SMLoc Loc, StringRef Msg) {
57 X86Operand *ParseOperand();
58 X86Operand *ParseATTOperand();
59 X86Operand *ParseIntelOperand();
60 X86Operand *ParseIntelOffsetOfOperator(SMLoc StartLoc);
61 X86Operand *ParseIntelOperator(SMLoc StartLoc, unsigned OpKind);
62 X86Operand *ParseIntelMemOperand(unsigned SegReg, uint64_t ImmDisp,
64 X86Operand *ParseIntelBracExpression(unsigned SegReg, uint64_t ImmDisp,
66 X86Operand *ParseIntelVarWithQualifier(const MCExpr *&Disp,
68 X86Operand *ParseMemOperand(unsigned SegReg, SMLoc StartLoc);
70 X86Operand *CreateMemForInlineAsm(const MCExpr *Disp, SMLoc Start, SMLoc End,
71 SMLoc SizeDirLoc, unsigned Size);
73 bool ParseIntelDotOperator(const MCExpr *Disp, const MCExpr **NewDisp,
74 SmallString<64> &Err);
76 bool ParseDirectiveWord(unsigned Size, SMLoc L);
77 bool ParseDirectiveCode(StringRef IDVal, SMLoc L);
79 bool processInstruction(MCInst &Inst,
80 const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
82 bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
83 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
84 MCStreamer &Out, unsigned &ErrorInfo,
85 bool MatchingInlineAsm);
87 /// isSrcOp - Returns true if operand is either (%rsi) or %ds:%(rsi)
88 /// in 64bit mode or (%esi) or %es:(%esi) in 32bit mode.
89 bool isSrcOp(X86Operand &Op);
91 /// isDstOp - Returns true if operand is either (%rdi) or %es:(%rdi)
92 /// in 64bit mode or (%edi) or %es:(%edi) in 32bit mode.
93 bool isDstOp(X86Operand &Op);
95 bool is64BitMode() const {
96 // FIXME: Can tablegen auto-generate this?
97 return (STI.getFeatureBits() & X86::Mode64Bit) != 0;
100 unsigned FB = ComputeAvailableFeatures(STI.ToggleFeature(X86::Mode64Bit));
101 setAvailableFeatures(FB);
104 /// @name Auto-generated Matcher Functions
107 #define GET_ASSEMBLER_HEADER
108 #include "X86GenAsmMatcher.inc"
113 X86AsmParser(MCSubtargetInfo &sti, MCAsmParser &parser)
114 : MCTargetAsmParser(), STI(sti), Parser(parser), InstInfo(0) {
116 // Initialize the set of available features.
117 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
119 virtual bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc);
121 virtual bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
123 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
125 virtual bool ParseDirective(AsmToken DirectiveID);
127 bool isParsingIntelSyntax() {
128 return getParser().getAssemblerDialect();
131 } // end anonymous namespace
133 /// @name Auto-generated Match Functions
136 static unsigned MatchRegisterName(StringRef Name);
140 static bool isImmSExti16i8Value(uint64_t Value) {
141 return (( Value <= 0x000000000000007FULL)||
142 (0x000000000000FF80ULL <= Value && Value <= 0x000000000000FFFFULL)||
143 (0xFFFFFFFFFFFFFF80ULL <= Value && Value <= 0xFFFFFFFFFFFFFFFFULL));
146 static bool isImmSExti32i8Value(uint64_t Value) {
147 return (( Value <= 0x000000000000007FULL)||
148 (0x00000000FFFFFF80ULL <= Value && Value <= 0x00000000FFFFFFFFULL)||
149 (0xFFFFFFFFFFFFFF80ULL <= Value && Value <= 0xFFFFFFFFFFFFFFFFULL));
152 static bool isImmZExtu32u8Value(uint64_t Value) {
153 return (Value <= 0x00000000000000FFULL);
156 static bool isImmSExti64i8Value(uint64_t Value) {
157 return (( Value <= 0x000000000000007FULL)||
158 (0xFFFFFFFFFFFFFF80ULL <= Value && Value <= 0xFFFFFFFFFFFFFFFFULL));
161 static bool isImmSExti64i32Value(uint64_t Value) {
162 return (( Value <= 0x000000007FFFFFFFULL)||
163 (0xFFFFFFFF80000000ULL <= Value && Value <= 0xFFFFFFFFFFFFFFFFULL));
167 /// X86Operand - Instances of this class represent a parsed X86 machine
169 struct X86Operand : public MCParsedAsmOperand {
177 SMLoc StartLoc, EndLoc;
210 X86Operand(KindTy K, SMLoc Start, SMLoc End)
211 : Kind(K), StartLoc(Start), EndLoc(End) {}
213 /// getStartLoc - Get the location of the first token of this operand.
214 SMLoc getStartLoc() const { return StartLoc; }
215 /// getEndLoc - Get the location of the last token of this operand.
216 SMLoc getEndLoc() const { return EndLoc; }
217 /// getLocRange - Get the range between the first and last token of this
219 SMRange getLocRange() const { return SMRange(StartLoc, EndLoc); }
220 /// getOffsetOfLoc - Get the location of the offset operator.
221 SMLoc getOffsetOfLoc() const { return OffsetOfLoc; }
223 virtual void print(raw_ostream &OS) const {}
225 StringRef getToken() const {
226 assert(Kind == Token && "Invalid access!");
227 return StringRef(Tok.Data, Tok.Length);
229 void setTokenValue(StringRef Value) {
230 assert(Kind == Token && "Invalid access!");
231 Tok.Data = Value.data();
232 Tok.Length = Value.size();
235 unsigned getReg() const {
236 assert(Kind == Register && "Invalid access!");
240 const MCExpr *getImm() const {
241 assert(Kind == Immediate && "Invalid access!");
245 const MCExpr *getMemDisp() const {
246 assert(Kind == Memory && "Invalid access!");
249 unsigned getMemSegReg() const {
250 assert(Kind == Memory && "Invalid access!");
253 unsigned getMemBaseReg() const {
254 assert(Kind == Memory && "Invalid access!");
257 unsigned getMemIndexReg() const {
258 assert(Kind == Memory && "Invalid access!");
261 unsigned getMemScale() const {
262 assert(Kind == Memory && "Invalid access!");
266 bool isToken() const {return Kind == Token; }
268 bool isImm() const { return Kind == Immediate; }
270 bool isImmSExti16i8() const {
274 // If this isn't a constant expr, just assume it fits and let relaxation
276 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
280 // Otherwise, check the value is in a range that makes sense for this
282 return isImmSExti16i8Value(CE->getValue());
284 bool isImmSExti32i8() const {
288 // If this isn't a constant expr, just assume it fits and let relaxation
290 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
294 // Otherwise, check the value is in a range that makes sense for this
296 return isImmSExti32i8Value(CE->getValue());
298 bool isImmZExtu32u8() const {
302 // If this isn't a constant expr, just assume it fits and let relaxation
304 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
308 // Otherwise, check the value is in a range that makes sense for this
310 return isImmZExtu32u8Value(CE->getValue());
312 bool isImmSExti64i8() const {
316 // If this isn't a constant expr, just assume it fits and let relaxation
318 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
322 // Otherwise, check the value is in a range that makes sense for this
324 return isImmSExti64i8Value(CE->getValue());
326 bool isImmSExti64i32() const {
330 // If this isn't a constant expr, just assume it fits and let relaxation
332 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
336 // Otherwise, check the value is in a range that makes sense for this
338 return isImmSExti64i32Value(CE->getValue());
341 bool isOffsetOf() const {
342 return OffsetOfLoc.getPointer();
345 bool needAddressOf() const {
349 bool isMem() const { return Kind == Memory; }
350 bool isMem8() const {
351 return Kind == Memory && (!Mem.Size || Mem.Size == 8);
353 bool isMem16() const {
354 return Kind == Memory && (!Mem.Size || Mem.Size == 16);
356 bool isMem32() const {
357 return Kind == Memory && (!Mem.Size || Mem.Size == 32);
359 bool isMem64() const {
360 return Kind == Memory && (!Mem.Size || Mem.Size == 64);
362 bool isMem80() const {
363 return Kind == Memory && (!Mem.Size || Mem.Size == 80);
365 bool isMem128() const {
366 return Kind == Memory && (!Mem.Size || Mem.Size == 128);
368 bool isMem256() const {
369 return Kind == Memory && (!Mem.Size || Mem.Size == 256);
372 bool isMemVX32() const {
373 return Kind == Memory && (!Mem.Size || Mem.Size == 32) &&
374 getMemIndexReg() >= X86::XMM0 && getMemIndexReg() <= X86::XMM15;
376 bool isMemVY32() const {
377 return Kind == Memory && (!Mem.Size || Mem.Size == 32) &&
378 getMemIndexReg() >= X86::YMM0 && getMemIndexReg() <= X86::YMM15;
380 bool isMemVX64() const {
381 return Kind == Memory && (!Mem.Size || Mem.Size == 64) &&
382 getMemIndexReg() >= X86::XMM0 && getMemIndexReg() <= X86::XMM15;
384 bool isMemVY64() const {
385 return Kind == Memory && (!Mem.Size || Mem.Size == 64) &&
386 getMemIndexReg() >= X86::YMM0 && getMemIndexReg() <= X86::YMM15;
389 bool isAbsMem() const {
390 return Kind == Memory && !getMemSegReg() && !getMemBaseReg() &&
391 !getMemIndexReg() && getMemScale() == 1;
394 bool isReg() const { return Kind == Register; }
396 void addExpr(MCInst &Inst, const MCExpr *Expr) const {
397 // Add as immediates when possible.
398 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
399 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
401 Inst.addOperand(MCOperand::CreateExpr(Expr));
404 void addRegOperands(MCInst &Inst, unsigned N) const {
405 assert(N == 1 && "Invalid number of operands!");
406 Inst.addOperand(MCOperand::CreateReg(getReg()));
409 void addImmOperands(MCInst &Inst, unsigned N) const {
410 assert(N == 1 && "Invalid number of operands!");
411 addExpr(Inst, getImm());
414 void addMem8Operands(MCInst &Inst, unsigned N) const {
415 addMemOperands(Inst, N);
417 void addMem16Operands(MCInst &Inst, unsigned N) const {
418 addMemOperands(Inst, N);
420 void addMem32Operands(MCInst &Inst, unsigned N) const {
421 addMemOperands(Inst, N);
423 void addMem64Operands(MCInst &Inst, unsigned N) const {
424 addMemOperands(Inst, N);
426 void addMem80Operands(MCInst &Inst, unsigned N) const {
427 addMemOperands(Inst, N);
429 void addMem128Operands(MCInst &Inst, unsigned N) const {
430 addMemOperands(Inst, N);
432 void addMem256Operands(MCInst &Inst, unsigned N) const {
433 addMemOperands(Inst, N);
435 void addMemVX32Operands(MCInst &Inst, unsigned N) const {
436 addMemOperands(Inst, N);
438 void addMemVY32Operands(MCInst &Inst, unsigned N) const {
439 addMemOperands(Inst, N);
441 void addMemVX64Operands(MCInst &Inst, unsigned N) const {
442 addMemOperands(Inst, N);
444 void addMemVY64Operands(MCInst &Inst, unsigned N) const {
445 addMemOperands(Inst, N);
448 void addMemOperands(MCInst &Inst, unsigned N) const {
449 assert((N == 5) && "Invalid number of operands!");
450 Inst.addOperand(MCOperand::CreateReg(getMemBaseReg()));
451 Inst.addOperand(MCOperand::CreateImm(getMemScale()));
452 Inst.addOperand(MCOperand::CreateReg(getMemIndexReg()));
453 addExpr(Inst, getMemDisp());
454 Inst.addOperand(MCOperand::CreateReg(getMemSegReg()));
457 void addAbsMemOperands(MCInst &Inst, unsigned N) const {
458 assert((N == 1) && "Invalid number of operands!");
459 // Add as immediates when possible.
460 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getMemDisp()))
461 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
463 Inst.addOperand(MCOperand::CreateExpr(getMemDisp()));
466 static X86Operand *CreateToken(StringRef Str, SMLoc Loc) {
467 SMLoc EndLoc = SMLoc::getFromPointer(Loc.getPointer() + Str.size());
468 X86Operand *Res = new X86Operand(Token, Loc, EndLoc);
469 Res->Tok.Data = Str.data();
470 Res->Tok.Length = Str.size();
474 static X86Operand *CreateReg(unsigned RegNo, SMLoc StartLoc, SMLoc EndLoc,
475 bool AddressOf = false,
476 SMLoc OffsetOfLoc = SMLoc()) {
477 X86Operand *Res = new X86Operand(Register, StartLoc, EndLoc);
478 Res->Reg.RegNo = RegNo;
479 Res->AddressOf = AddressOf;
480 Res->OffsetOfLoc = OffsetOfLoc;
484 static X86Operand *CreateImm(const MCExpr *Val, SMLoc StartLoc, SMLoc EndLoc){
485 X86Operand *Res = new X86Operand(Immediate, StartLoc, EndLoc);
490 /// Create an absolute memory operand.
491 static X86Operand *CreateMem(const MCExpr *Disp, SMLoc StartLoc, SMLoc EndLoc,
493 X86Operand *Res = new X86Operand(Memory, StartLoc, EndLoc);
495 Res->Mem.Disp = Disp;
496 Res->Mem.BaseReg = 0;
497 Res->Mem.IndexReg = 0;
499 Res->Mem.Size = Size;
500 Res->AddressOf = false;
504 /// Create a generalized memory operand.
505 static X86Operand *CreateMem(unsigned SegReg, const MCExpr *Disp,
506 unsigned BaseReg, unsigned IndexReg,
507 unsigned Scale, SMLoc StartLoc, SMLoc EndLoc,
509 // We should never just have a displacement, that should be parsed as an
510 // absolute memory operand.
511 assert((SegReg || BaseReg || IndexReg) && "Invalid memory operand!");
513 // The scale should always be one of {1,2,4,8}.
514 assert(((Scale == 1 || Scale == 2 || Scale == 4 || Scale == 8)) &&
516 X86Operand *Res = new X86Operand(Memory, StartLoc, EndLoc);
517 Res->Mem.SegReg = SegReg;
518 Res->Mem.Disp = Disp;
519 Res->Mem.BaseReg = BaseReg;
520 Res->Mem.IndexReg = IndexReg;
521 Res->Mem.Scale = Scale;
522 Res->Mem.Size = Size;
523 Res->AddressOf = false;
528 } // end anonymous namespace.
530 bool X86AsmParser::isSrcOp(X86Operand &Op) {
531 unsigned basereg = is64BitMode() ? X86::RSI : X86::ESI;
533 return (Op.isMem() &&
534 (Op.Mem.SegReg == 0 || Op.Mem.SegReg == X86::DS) &&
535 isa<MCConstantExpr>(Op.Mem.Disp) &&
536 cast<MCConstantExpr>(Op.Mem.Disp)->getValue() == 0 &&
537 Op.Mem.BaseReg == basereg && Op.Mem.IndexReg == 0);
540 bool X86AsmParser::isDstOp(X86Operand &Op) {
541 unsigned basereg = is64BitMode() ? X86::RDI : X86::EDI;
544 (Op.Mem.SegReg == 0 || Op.Mem.SegReg == X86::ES) &&
545 isa<MCConstantExpr>(Op.Mem.Disp) &&
546 cast<MCConstantExpr>(Op.Mem.Disp)->getValue() == 0 &&
547 Op.Mem.BaseReg == basereg && Op.Mem.IndexReg == 0;
550 bool X86AsmParser::ParseRegister(unsigned &RegNo,
551 SMLoc &StartLoc, SMLoc &EndLoc) {
553 const AsmToken &PercentTok = Parser.getTok();
554 StartLoc = PercentTok.getLoc();
556 // If we encounter a %, ignore it. This code handles registers with and
557 // without the prefix, unprefixed registers can occur in cfi directives.
558 if (!isParsingIntelSyntax() && PercentTok.is(AsmToken::Percent))
559 Parser.Lex(); // Eat percent token.
561 const AsmToken &Tok = Parser.getTok();
562 EndLoc = Tok.getEndLoc();
564 if (Tok.isNot(AsmToken::Identifier)) {
565 if (isParsingIntelSyntax()) return true;
566 return Error(StartLoc, "invalid register name",
567 SMRange(StartLoc, EndLoc));
570 RegNo = MatchRegisterName(Tok.getString());
572 // If the match failed, try the register name as lowercase.
574 RegNo = MatchRegisterName(Tok.getString().lower());
576 if (!is64BitMode()) {
577 // FIXME: This should be done using Requires<In32BitMode> and
578 // Requires<In64BitMode> so "eiz" usage in 64-bit instructions can be also
580 // FIXME: Check AH, CH, DH, BH cannot be used in an instruction requiring a
582 if (RegNo == X86::RIZ ||
583 X86MCRegisterClasses[X86::GR64RegClassID].contains(RegNo) ||
584 X86II::isX86_64NonExtLowByteReg(RegNo) ||
585 X86II::isX86_64ExtendedReg(RegNo))
586 return Error(StartLoc, "register %"
587 + Tok.getString() + " is only available in 64-bit mode",
588 SMRange(StartLoc, EndLoc));
591 // Parse "%st" as "%st(0)" and "%st(1)", which is multiple tokens.
592 if (RegNo == 0 && (Tok.getString() == "st" || Tok.getString() == "ST")) {
594 Parser.Lex(); // Eat 'st'
596 // Check to see if we have '(4)' after %st.
597 if (getLexer().isNot(AsmToken::LParen))
602 const AsmToken &IntTok = Parser.getTok();
603 if (IntTok.isNot(AsmToken::Integer))
604 return Error(IntTok.getLoc(), "expected stack index");
605 switch (IntTok.getIntVal()) {
606 case 0: RegNo = X86::ST0; break;
607 case 1: RegNo = X86::ST1; break;
608 case 2: RegNo = X86::ST2; break;
609 case 3: RegNo = X86::ST3; break;
610 case 4: RegNo = X86::ST4; break;
611 case 5: RegNo = X86::ST5; break;
612 case 6: RegNo = X86::ST6; break;
613 case 7: RegNo = X86::ST7; break;
614 default: return Error(IntTok.getLoc(), "invalid stack index");
617 if (getParser().Lex().isNot(AsmToken::RParen))
618 return Error(Parser.getTok().getLoc(), "expected ')'");
620 EndLoc = Parser.getTok().getEndLoc();
621 Parser.Lex(); // Eat ')'
625 EndLoc = Parser.getTok().getEndLoc();
627 // If this is "db[0-7]", match it as an alias
629 if (RegNo == 0 && Tok.getString().size() == 3 &&
630 Tok.getString().startswith("db")) {
631 switch (Tok.getString()[2]) {
632 case '0': RegNo = X86::DR0; break;
633 case '1': RegNo = X86::DR1; break;
634 case '2': RegNo = X86::DR2; break;
635 case '3': RegNo = X86::DR3; break;
636 case '4': RegNo = X86::DR4; break;
637 case '5': RegNo = X86::DR5; break;
638 case '6': RegNo = X86::DR6; break;
639 case '7': RegNo = X86::DR7; break;
643 EndLoc = Parser.getTok().getEndLoc();
644 Parser.Lex(); // Eat it.
650 if (isParsingIntelSyntax()) return true;
651 return Error(StartLoc, "invalid register name",
652 SMRange(StartLoc, EndLoc));
655 Parser.Lex(); // Eat identifier token.
659 X86Operand *X86AsmParser::ParseOperand() {
660 if (isParsingIntelSyntax())
661 return ParseIntelOperand();
662 return ParseATTOperand();
665 /// getIntelMemOperandSize - Return intel memory operand size.
666 static unsigned getIntelMemOperandSize(StringRef OpStr) {
667 unsigned Size = StringSwitch<unsigned>(OpStr)
668 .Cases("BYTE", "byte", 8)
669 .Cases("WORD", "word", 16)
670 .Cases("DWORD", "dword", 32)
671 .Cases("QWORD", "qword", 64)
672 .Cases("XWORD", "xword", 80)
673 .Cases("XMMWORD", "xmmword", 128)
674 .Cases("YMMWORD", "ymmword", 256)
679 enum InfixCalculatorTok {
689 static const char OpPrecedence[] = {
700 class InfixCalculator {
701 typedef std::pair< InfixCalculatorTok, int64_t > ICToken;
702 SmallVector<InfixCalculatorTok, 4> InfixOperatorStack;
703 SmallVector<ICToken, 4> PostfixStack;
706 int64_t popOperand() {
707 assert (!PostfixStack.empty() && "Poped an empty stack!");
708 ICToken Op = PostfixStack.pop_back_val();
709 assert ((Op.first == IC_IMM || Op.first == IC_REGISTER)
710 && "Expected and immediate or register!");
713 void pushOperand(InfixCalculatorTok Op, int64_t Val = 0) {
714 assert ((Op == IC_IMM || Op == IC_REGISTER) &&
715 "Unexpected operand!");
716 PostfixStack.push_back(std::make_pair(Op, Val));
719 void popOperator() { InfixOperatorStack.pop_back_val(); }
720 void pushOperator(InfixCalculatorTok Op) {
721 // Push the new operator if the stack is empty.
722 if (InfixOperatorStack.empty()) {
723 InfixOperatorStack.push_back(Op);
727 // Push the new operator if it has a higher precedence than the operator on
728 // the top of the stack or the operator on the top of the stack is a left
730 unsigned Idx = InfixOperatorStack.size() - 1;
731 InfixCalculatorTok StackOp = InfixOperatorStack[Idx];
732 if (OpPrecedence[Op] > OpPrecedence[StackOp] || StackOp == IC_LPAREN) {
733 InfixOperatorStack.push_back(Op);
737 // The operator on the top of the stack has higher precedence than the
739 unsigned ParenCount = 0;
741 // Nothing to process.
742 if (InfixOperatorStack.empty())
745 Idx = InfixOperatorStack.size() - 1;
746 StackOp = InfixOperatorStack[Idx];
747 if (!(OpPrecedence[StackOp] >= OpPrecedence[Op] || ParenCount))
750 // If we have an even parentheses count and we see a left parentheses,
751 // then stop processing.
752 if (!ParenCount && StackOp == IC_LPAREN)
755 if (StackOp == IC_RPAREN) {
757 InfixOperatorStack.pop_back_val();
758 } else if (StackOp == IC_LPAREN) {
760 InfixOperatorStack.pop_back_val();
762 InfixOperatorStack.pop_back_val();
763 PostfixStack.push_back(std::make_pair(StackOp, 0));
766 // Push the new operator.
767 InfixOperatorStack.push_back(Op);
770 // Push any remaining operators onto the postfix stack.
771 while (!InfixOperatorStack.empty()) {
772 InfixCalculatorTok StackOp = InfixOperatorStack.pop_back_val();
773 if (StackOp != IC_LPAREN && StackOp != IC_RPAREN)
774 PostfixStack.push_back(std::make_pair(StackOp, 0));
777 if (PostfixStack.empty())
780 SmallVector<ICToken, 16> OperandStack;
781 for (unsigned i = 0, e = PostfixStack.size(); i != e; ++i) {
782 ICToken Op = PostfixStack[i];
783 if (Op.first == IC_IMM || Op.first == IC_REGISTER) {
784 OperandStack.push_back(Op);
786 assert (OperandStack.size() > 1 && "Too few operands.");
788 ICToken Op2 = OperandStack.pop_back_val();
789 ICToken Op1 = OperandStack.pop_back_val();
792 report_fatal_error("Unexpected operator!");
795 Val = Op1.second + Op2.second;
796 OperandStack.push_back(std::make_pair(IC_IMM, Val));
799 Val = Op1.second - Op2.second;
800 OperandStack.push_back(std::make_pair(IC_IMM, Val));
803 assert (Op1.first == IC_IMM && Op2.first == IC_IMM &&
804 "Multiply operation with an immediate and a register!");
805 Val = Op1.second * Op2.second;
806 OperandStack.push_back(std::make_pair(IC_IMM, Val));
809 assert (Op1.first == IC_IMM && Op2.first == IC_IMM &&
810 "Divide operation with an immediate and a register!");
811 assert (Op2.second != 0 && "Division by zero!");
812 Val = Op1.second / Op2.second;
813 OperandStack.push_back(std::make_pair(IC_IMM, Val));
818 assert (OperandStack.size() == 1 && "Expected a single result.");
819 return OperandStack.pop_back_val().second;
823 enum IntelBracExprState {
840 class IntelBracExprStateMachine {
841 IntelBracExprState State;
842 unsigned BaseReg, IndexReg, TmpReg, Scale;
846 IntelBracExprStateMachine(MCAsmParser &parser, int64_t disp) :
847 State(IBES_PLUS), BaseReg(0), IndexReg(0), TmpReg(0), Scale(1), Disp(disp){}
849 unsigned getBaseReg() { return BaseReg; }
850 unsigned getIndexReg() { return IndexReg; }
851 unsigned getScale() { return Scale; }
852 int64_t getDisp() { return Disp + IC.execute(); }
853 bool isValidEndState() { return State == IBES_RBRAC; }
863 IC.pushOperator(IC_PLUS);
867 // If we already have a BaseReg, then assume this is the IndexReg with a
872 assert (!IndexReg && "BaseReg/IndexReg already set!");
876 IC.pushOperator(IC_PLUS);
887 IC.pushOperand(IC_IMM);
891 IC.pushOperator(IC_MINUS);
895 // If we already have a BaseReg, then assume this is the IndexReg with a
900 assert (!IndexReg && "BaseReg/IndexReg already set!");
904 IC.pushOperator(IC_MINUS);
908 void onRegister(unsigned Reg) {
915 State = IBES_REGISTER;
917 IC.pushOperand(IC_REGISTER);
919 case IBES_INTEGER_STAR:
920 assert (!IndexReg && "IndexReg already set!");
921 State = IBES_INTEGER;
923 Scale = IC.popOperand();
924 IC.pushOperand(IC_IMM);
936 State = IBES_INTEGER;
937 IC.pushOperand(IC_IMM);
941 void onInteger(int64_t TmpInt) {
951 case IBES_INTEGER_STAR:
952 State = IBES_INTEGER;
953 IC.pushOperand(IC_IMM, TmpInt);
955 case IBES_REGISTER_STAR:
956 assert (!IndexReg && "IndexReg already set!");
957 State = IBES_INTEGER;
970 State = IBES_INTEGER_STAR;
971 IC.pushOperator(IC_MULTIPLY);
974 State = IBES_REGISTER_STAR;
975 IC.pushOperator(IC_MULTIPLY);
978 State = IBES_MULTIPLY;
979 IC.pushOperator(IC_MULTIPLY);
990 IC.pushOperator(IC_DIVIDE);
1001 IC.pushOperator(IC_PLUS);
1016 // If we already have a BaseReg, then assume this is the IndexReg with a
1021 assert (!IndexReg && "BaseReg/IndexReg already set!");
1037 case IBES_INTEGER_STAR:
1039 State = IBES_LPAREN;
1040 IC.pushOperator(IC_LPAREN);
1056 State = IBES_RPAREN;
1057 IC.pushOperator(IC_RPAREN);
1063 X86Operand *X86AsmParser::CreateMemForInlineAsm(const MCExpr *Disp, SMLoc Start,
1064 SMLoc End, SMLoc SizeDirLoc,
1066 bool NeedSizeDir = false;
1067 bool IsVarDecl = false;
1068 if (const MCSymbolRefExpr *SymRef = dyn_cast<MCSymbolRefExpr>(Disp)) {
1069 const MCSymbol &Sym = SymRef->getSymbol();
1070 // FIXME: The SemaLookup will fail if the name is anything other then an
1072 // FIXME: Pass a valid SMLoc.
1073 unsigned tLength, tSize, tType;
1074 SemaCallback->LookupInlineAsmIdentifier(Sym.getName(), NULL, tLength,
1075 tSize, tType, IsVarDecl);
1077 Size = tType * 8; // Size is in terms of bits in this context.
1078 NeedSizeDir = Size > 0;
1082 // If this is not a VarDecl then assume it is a FuncDecl or some other label
1083 // reference. We need an 'r' constraint here, so we need to create register
1084 // operand to ensure proper matching. Just pick a GPR based on the size of
1087 unsigned RegNo = is64BitMode() ? X86::RBX : X86::EBX;
1088 return X86Operand::CreateReg(RegNo, Start, End, /*AddressOf=*/true);
1092 InstInfo->AsmRewrites->push_back(AsmRewrite(AOK_SizeDirective, SizeDirLoc,
1095 // When parsing inline assembly we set the base register to a non-zero value
1096 // as we don't know the actual value at this time. This is necessary to
1097 // get the matching correct in some cases.
1098 return X86Operand::CreateMem(/*SegReg*/0, Disp, /*BaseReg*/1, /*IndexReg*/0,
1099 /*Scale*/1, Start, End, Size);
1102 X86Operand *X86AsmParser::ParseIntelBracExpression(unsigned SegReg,
1105 const AsmToken &Tok = Parser.getTok();
1106 SMLoc Start = Tok.getLoc(), End = Tok.getEndLoc();
1109 if (getLexer().isNot(AsmToken::LBrac))
1110 return ErrorOperand(Start, "Expected '[' token!");
1113 unsigned TmpReg = 0;
1115 // Try to handle '[' 'Symbol' ']'
1116 if (getLexer().is(AsmToken::Identifier)) {
1117 if (ParseRegister(TmpReg, Start, End)) {
1119 SMLoc IdentStart = Tok.getLoc();
1120 if (getParser().parseExpression(Disp, End))
1123 if (X86Operand *Err = ParseIntelVarWithQualifier(Disp, IdentStart))
1126 if (getLexer().isNot(AsmToken::RBrac))
1127 return ErrorOperand(Parser.getTok().getLoc(), "Expected ']' token!");
1129 // FIXME: We don't handle 'ImmDisp' '[' 'Symbol' ']'.
1131 return ErrorOperand(Start, "Unsupported immediate displacement!");
1133 // Adjust the EndLoc due to the ']'.
1134 End = SMLoc::getFromPointer(Parser.getTok().getEndLoc().getPointer()-1);
1136 if (!isParsingInlineAsm())
1137 return X86Operand::CreateMem(Disp, Start, End, Size);
1139 // We want the size directive before the '['.
1140 SMLoc SizeDirLoc = SMLoc::getFromPointer(Start.getPointer()-1);
1141 return CreateMemForInlineAsm(Disp, Start, End, SizeDirLoc, Size);
1145 // Parse [ BaseReg + Scale*IndexReg + Disp ]. We may have already parsed an
1146 // immediate displacement before the bracketed expression.
1148 IntelBracExprStateMachine SM(Parser, ImmDisp);
1150 // If we parsed a register, then the end loc has already been set and
1151 // the identifier has already been lexed. We also need to update the
1154 SM.onRegister(TmpReg);
1156 const MCExpr *Disp = 0;
1158 bool UpdateLocLex = true;
1160 // The period in the dot operator (e.g., [ebx].foo.bar) is parsed as an
1161 // identifier. Don't try an parse it as a register.
1162 if (Tok.getString().startswith("."))
1165 switch (getLexer().getKind()) {
1167 if (SM.isValidEndState()) {
1171 return ErrorOperand(Tok.getLoc(), "Unexpected token!");
1173 case AsmToken::Identifier: {
1174 // This could be a register or a displacement expression.
1175 if(!ParseRegister(TmpReg, Start, End)) {
1176 SM.onRegister(TmpReg);
1177 UpdateLocLex = false;
1179 } else if (!getParser().parseExpression(Disp, End)) {
1181 UpdateLocLex = false;
1184 return ErrorOperand(Tok.getLoc(), "Unexpected identifier!");
1186 case AsmToken::Integer:
1187 if (isParsingInlineAsm())
1188 InstInfo->AsmRewrites->push_back(AsmRewrite(AOK_ImmPrefix,
1190 SM.onInteger(Tok.getIntVal());
1192 case AsmToken::Plus: SM.onPlus(); break;
1193 case AsmToken::Minus: SM.onMinus(); break;
1194 case AsmToken::Star: SM.onStar(); break;
1195 case AsmToken::Slash: SM.onDivide(); break;
1196 case AsmToken::LBrac: SM.onLBrac(); break;
1197 case AsmToken::RBrac: SM.onRBrac(); break;
1198 case AsmToken::LParen: SM.onLParen(); break;
1199 case AsmToken::RParen: SM.onRParen(); break;
1201 if (!Done && UpdateLocLex) {
1203 Parser.Lex(); // Consume the token.
1208 Disp = MCConstantExpr::Create(SM.getDisp(), getContext());
1210 // Parse the dot operator (e.g., [ebx].foo.bar).
1211 if (Tok.getString().startswith(".")) {
1212 SmallString<64> Err;
1213 const MCExpr *NewDisp;
1214 if (ParseIntelDotOperator(Disp, &NewDisp, Err))
1215 return ErrorOperand(Tok.getLoc(), Err);
1217 End = Parser.getTok().getEndLoc();
1218 Parser.Lex(); // Eat the field.
1222 int BaseReg = SM.getBaseReg();
1223 int IndexReg = SM.getIndexReg();
1226 if (!BaseReg && !IndexReg) {
1228 return X86Operand::CreateMem(Disp, Start, End);
1230 return X86Operand::CreateMem(SegReg, Disp, 0, 0, 1, Start, End, Size);
1233 int Scale = SM.getScale();
1234 return X86Operand::CreateMem(SegReg, Disp, BaseReg, IndexReg, Scale,
1238 // Inline assembly may use variable names with namespace alias qualifiers.
1239 X86Operand *X86AsmParser::ParseIntelVarWithQualifier(const MCExpr *&Disp,
1240 SMLoc &IdentStart) {
1241 // We should only see Foo::Bar if we're parsing inline assembly.
1242 if (!isParsingInlineAsm())
1245 // If we don't see a ':' then there can't be a qualifier.
1246 if (getLexer().isNot(AsmToken::Colon))
1251 const AsmToken &Tok = Parser.getTok();
1252 SMLoc IdentEnd = Tok.getEndLoc();
1254 switch (getLexer().getKind()) {
1258 case AsmToken::Colon:
1259 getLexer().Lex(); // Consume ':'.
1260 if (getLexer().isNot(AsmToken::Colon))
1261 return ErrorOperand(Tok.getLoc(), "Expected ':' token!");
1262 getLexer().Lex(); // Consume second ':'.
1263 if (getLexer().isNot(AsmToken::Identifier))
1264 return ErrorOperand(Tok.getLoc(), "Expected an identifier token!");
1266 case AsmToken::Identifier:
1267 IdentEnd = Tok.getEndLoc();
1268 getLexer().Lex(); // Consume the identifier.
1272 size_t Len = IdentEnd.getPointer() - IdentStart.getPointer();
1273 StringRef Identifier(IdentStart.getPointer(), Len);
1274 MCSymbol *Sym = getContext().GetOrCreateSymbol(Identifier);
1275 MCSymbolRefExpr::VariantKind Variant = MCSymbolRefExpr::VK_None;
1276 Disp = MCSymbolRefExpr::Create(Sym, Variant, getParser().getContext());
1280 /// ParseIntelMemOperand - Parse intel style memory operand.
1281 X86Operand *X86AsmParser::ParseIntelMemOperand(unsigned SegReg,
1284 const AsmToken &Tok = Parser.getTok();
1287 unsigned Size = getIntelMemOperandSize(Tok.getString());
1290 assert ((Tok.getString() == "PTR" || Tok.getString() == "ptr") &&
1291 "Unexpected token!");
1295 // Parse ImmDisp [ BaseReg + Scale*IndexReg + Disp ].
1296 if (getLexer().is(AsmToken::Integer)) {
1297 const AsmToken &IntTok = Parser.getTok();
1298 if (isParsingInlineAsm())
1299 InstInfo->AsmRewrites->push_back(AsmRewrite(AOK_ImmPrefix,
1301 uint64_t ImmDisp = IntTok.getIntVal();
1302 Parser.Lex(); // Eat the integer.
1303 if (getLexer().isNot(AsmToken::LBrac))
1304 return ErrorOperand(Start, "Expected '[' token!");
1305 return ParseIntelBracExpression(SegReg, ImmDisp, Size);
1308 if (getLexer().is(AsmToken::LBrac))
1309 return ParseIntelBracExpression(SegReg, ImmDisp, Size);
1311 if (!ParseRegister(SegReg, Start, End)) {
1312 // Handel SegReg : [ ... ]
1313 if (getLexer().isNot(AsmToken::Colon))
1314 return ErrorOperand(Start, "Expected ':' token!");
1315 Parser.Lex(); // Eat :
1316 if (getLexer().isNot(AsmToken::LBrac))
1317 return ErrorOperand(Start, "Expected '[' token!");
1318 return ParseIntelBracExpression(SegReg, ImmDisp, Size);
1321 const MCExpr *Disp = MCConstantExpr::Create(0, getParser().getContext());
1322 SMLoc IdentStart = Tok.getLoc();
1323 if (getParser().parseExpression(Disp, End))
1326 if (!isParsingInlineAsm())
1327 return X86Operand::CreateMem(Disp, Start, End, Size);
1329 if (X86Operand *Err = ParseIntelVarWithQualifier(Disp, IdentStart))
1332 return CreateMemForInlineAsm(Disp, Start, End, Start, Size);
1335 /// Parse the '.' operator.
1336 bool X86AsmParser::ParseIntelDotOperator(const MCExpr *Disp,
1337 const MCExpr **NewDisp,
1338 SmallString<64> &Err) {
1339 AsmToken Tok = *&Parser.getTok();
1340 uint64_t OrigDispVal, DotDispVal;
1342 // FIXME: Handle non-constant expressions.
1343 if (const MCConstantExpr *OrigDisp = dyn_cast<MCConstantExpr>(Disp)) {
1344 OrigDispVal = OrigDisp->getValue();
1346 Err = "Non-constant offsets are not supported!";
1351 StringRef DotDispStr = Tok.getString().drop_front(1);
1353 // .Imm gets lexed as a real.
1354 if (Tok.is(AsmToken::Real)) {
1356 DotDispStr.getAsInteger(10, DotDisp);
1357 DotDispVal = DotDisp.getZExtValue();
1358 } else if (Tok.is(AsmToken::Identifier)) {
1359 // We should only see an identifier when parsing the original inline asm.
1360 // The front-end should rewrite this in terms of immediates.
1361 assert (isParsingInlineAsm() && "Unexpected field name!");
1364 std::pair<StringRef, StringRef> BaseMember = DotDispStr.split('.');
1365 if (SemaCallback->LookupInlineAsmField(BaseMember.first, BaseMember.second,
1367 Err = "Unable to lookup field reference!";
1370 DotDispVal = DotDisp;
1372 Err = "Unexpected token type!";
1376 if (isParsingInlineAsm() && Tok.is(AsmToken::Identifier)) {
1377 SMLoc Loc = SMLoc::getFromPointer(DotDispStr.data());
1378 unsigned Len = DotDispStr.size();
1379 unsigned Val = OrigDispVal + DotDispVal;
1380 InstInfo->AsmRewrites->push_back(AsmRewrite(AOK_DotOperator, Loc, Len,
1384 *NewDisp = MCConstantExpr::Create(OrigDispVal + DotDispVal, getContext());
1388 /// Parse the 'offset' operator. This operator is used to specify the
1389 /// location rather then the content of a variable.
1390 X86Operand *X86AsmParser::ParseIntelOffsetOfOperator(SMLoc Start) {
1391 SMLoc OffsetOfLoc = Start;
1392 Parser.Lex(); // Eat offset.
1393 Start = Parser.getTok().getLoc();
1394 assert (Parser.getTok().is(AsmToken::Identifier) && "Expected an identifier");
1398 if (getParser().parseExpression(Val, End))
1399 return ErrorOperand(Start, "Unable to parse expression!");
1401 // Don't emit the offset operator.
1402 InstInfo->AsmRewrites->push_back(AsmRewrite(AOK_Skip, OffsetOfLoc, 7));
1404 // The offset operator will have an 'r' constraint, thus we need to create
1405 // register operand to ensure proper matching. Just pick a GPR based on
1406 // the size of a pointer.
1407 unsigned RegNo = is64BitMode() ? X86::RBX : X86::EBX;
1408 return X86Operand::CreateReg(RegNo, Start, End, /*GetAddress=*/true,
1412 enum IntelOperatorKind {
1418 /// Parse the 'LENGTH', 'TYPE' and 'SIZE' operators. The LENGTH operator
1419 /// returns the number of elements in an array. It returns the value 1 for
1420 /// non-array variables. The SIZE operator returns the size of a C or C++
1421 /// variable. A variable's size is the product of its LENGTH and TYPE. The
1422 /// TYPE operator returns the size of a C or C++ type or variable. If the
1423 /// variable is an array, TYPE returns the size of a single element.
1424 X86Operand *X86AsmParser::ParseIntelOperator(SMLoc Start, unsigned OpKind) {
1425 SMLoc TypeLoc = Start;
1426 Parser.Lex(); // Eat offset.
1427 Start = Parser.getTok().getLoc();
1428 assert (Parser.getTok().is(AsmToken::Identifier) && "Expected an identifier");
1432 if (getParser().parseExpression(Val, End))
1435 unsigned Length = 0, Size = 0, Type = 0;
1436 if (const MCSymbolRefExpr *SymRef = dyn_cast<MCSymbolRefExpr>(Val)) {
1437 const MCSymbol &Sym = SymRef->getSymbol();
1438 // FIXME: The SemaLookup will fail if the name is anything other then an
1440 // FIXME: Pass a valid SMLoc.
1442 if (!SemaCallback->LookupInlineAsmIdentifier(Sym.getName(), NULL, Length,
1443 Size, Type, IsVarDecl))
1444 return ErrorOperand(Start, "Unable to lookup expr!");
1448 default: llvm_unreachable("Unexpected operand kind!");
1449 case IOK_LENGTH: CVal = Length; break;
1450 case IOK_SIZE: CVal = Size; break;
1451 case IOK_TYPE: CVal = Type; break;
1454 // Rewrite the type operator and the C or C++ type or variable in terms of an
1455 // immediate. E.g. TYPE foo -> $$4
1456 unsigned Len = End.getPointer() - TypeLoc.getPointer();
1457 InstInfo->AsmRewrites->push_back(AsmRewrite(AOK_Imm, TypeLoc, Len, CVal));
1459 const MCExpr *Imm = MCConstantExpr::Create(CVal, getContext());
1460 return X86Operand::CreateImm(Imm, Start, End);
1463 X86Operand *X86AsmParser::ParseIntelOperand() {
1464 SMLoc Start = Parser.getTok().getLoc(), End;
1465 StringRef AsmTokStr = Parser.getTok().getString();
1467 // Offset, length, type and size operators.
1468 if (isParsingInlineAsm()) {
1469 if (AsmTokStr == "offset" || AsmTokStr == "OFFSET")
1470 return ParseIntelOffsetOfOperator(Start);
1471 if (AsmTokStr == "length" || AsmTokStr == "LENGTH")
1472 return ParseIntelOperator(Start, IOK_LENGTH);
1473 if (AsmTokStr == "size" || AsmTokStr == "SIZE")
1474 return ParseIntelOperator(Start, IOK_SIZE);
1475 if (AsmTokStr == "type" || AsmTokStr == "TYPE")
1476 return ParseIntelOperator(Start, IOK_TYPE);
1480 if (getLexer().is(AsmToken::Integer) || getLexer().is(AsmToken::Real) ||
1481 getLexer().is(AsmToken::Minus)) {
1483 bool isInteger = getLexer().is(AsmToken::Integer);
1484 if (!getParser().parseExpression(Val, End)) {
1485 if (isParsingInlineAsm())
1486 InstInfo->AsmRewrites->push_back(AsmRewrite(AOK_ImmPrefix, Start));
1488 if (getLexer().isNot(AsmToken::LBrac))
1489 return X86Operand::CreateImm(Val, Start, End);
1491 // Only positive immediates are valid.
1493 Error(Parser.getTok().getLoc(), "expected a positive immediate "
1494 "displacement before bracketed expr.");
1498 // Parse ImmDisp [ BaseReg + Scale*IndexReg + Disp ].
1499 if (uint64_t ImmDisp = dyn_cast<MCConstantExpr>(Val)->getValue())
1500 return ParseIntelMemOperand(/*SegReg=*/0, ImmDisp, Start);
1506 if (!ParseRegister(RegNo, Start, End)) {
1507 // If this is a segment register followed by a ':', then this is the start
1508 // of a memory reference, otherwise this is a normal register reference.
1509 if (getLexer().isNot(AsmToken::Colon))
1510 return X86Operand::CreateReg(RegNo, Start, End);
1512 getParser().Lex(); // Eat the colon.
1513 return ParseIntelMemOperand(/*SegReg=*/RegNo, /*Disp=*/0, Start);
1517 return ParseIntelMemOperand(/*SegReg=*/0, /*Disp=*/0, Start);
1520 X86Operand *X86AsmParser::ParseATTOperand() {
1521 switch (getLexer().getKind()) {
1523 // Parse a memory operand with no segment register.
1524 return ParseMemOperand(0, Parser.getTok().getLoc());
1525 case AsmToken::Percent: {
1526 // Read the register.
1529 if (ParseRegister(RegNo, Start, End)) return 0;
1530 if (RegNo == X86::EIZ || RegNo == X86::RIZ) {
1531 Error(Start, "%eiz and %riz can only be used as index registers",
1532 SMRange(Start, End));
1536 // If this is a segment register followed by a ':', then this is the start
1537 // of a memory reference, otherwise this is a normal register reference.
1538 if (getLexer().isNot(AsmToken::Colon))
1539 return X86Operand::CreateReg(RegNo, Start, End);
1541 getParser().Lex(); // Eat the colon.
1542 return ParseMemOperand(RegNo, Start);
1544 case AsmToken::Dollar: {
1545 // $42 -> immediate.
1546 SMLoc Start = Parser.getTok().getLoc(), End;
1549 if (getParser().parseExpression(Val, End))
1551 return X86Operand::CreateImm(Val, Start, End);
1556 /// ParseMemOperand: segment: disp(basereg, indexreg, scale). The '%ds:' prefix
1557 /// has already been parsed if present.
1558 X86Operand *X86AsmParser::ParseMemOperand(unsigned SegReg, SMLoc MemStart) {
1560 // We have to disambiguate a parenthesized expression "(4+5)" from the start
1561 // of a memory operand with a missing displacement "(%ebx)" or "(,%eax)". The
1562 // only way to do this without lookahead is to eat the '(' and see what is
1564 const MCExpr *Disp = MCConstantExpr::Create(0, getParser().getContext());
1565 if (getLexer().isNot(AsmToken::LParen)) {
1567 if (getParser().parseExpression(Disp, ExprEnd)) return 0;
1569 // After parsing the base expression we could either have a parenthesized
1570 // memory address or not. If not, return now. If so, eat the (.
1571 if (getLexer().isNot(AsmToken::LParen)) {
1572 // Unless we have a segment register, treat this as an immediate.
1574 return X86Operand::CreateMem(Disp, MemStart, ExprEnd);
1575 return X86Operand::CreateMem(SegReg, Disp, 0, 0, 1, MemStart, ExprEnd);
1581 // Okay, we have a '('. We don't know if this is an expression or not, but
1582 // so we have to eat the ( to see beyond it.
1583 SMLoc LParenLoc = Parser.getTok().getLoc();
1584 Parser.Lex(); // Eat the '('.
1586 if (getLexer().is(AsmToken::Percent) || getLexer().is(AsmToken::Comma)) {
1587 // Nothing to do here, fall into the code below with the '(' part of the
1588 // memory operand consumed.
1592 // It must be an parenthesized expression, parse it now.
1593 if (getParser().parseParenExpression(Disp, ExprEnd))
1596 // After parsing the base expression we could either have a parenthesized
1597 // memory address or not. If not, return now. If so, eat the (.
1598 if (getLexer().isNot(AsmToken::LParen)) {
1599 // Unless we have a segment register, treat this as an immediate.
1601 return X86Operand::CreateMem(Disp, LParenLoc, ExprEnd);
1602 return X86Operand::CreateMem(SegReg, Disp, 0, 0, 1, MemStart, ExprEnd);
1610 // If we reached here, then we just ate the ( of the memory operand. Process
1611 // the rest of the memory operand.
1612 unsigned BaseReg = 0, IndexReg = 0, Scale = 1;
1615 if (getLexer().is(AsmToken::Percent)) {
1616 SMLoc StartLoc, EndLoc;
1617 if (ParseRegister(BaseReg, StartLoc, EndLoc)) return 0;
1618 if (BaseReg == X86::EIZ || BaseReg == X86::RIZ) {
1619 Error(StartLoc, "eiz and riz can only be used as index registers",
1620 SMRange(StartLoc, EndLoc));
1625 if (getLexer().is(AsmToken::Comma)) {
1626 Parser.Lex(); // Eat the comma.
1627 IndexLoc = Parser.getTok().getLoc();
1629 // Following the comma we should have either an index register, or a scale
1630 // value. We don't support the later form, but we want to parse it
1633 // Not that even though it would be completely consistent to support syntax
1634 // like "1(%eax,,1)", the assembler doesn't. Use "eiz" or "riz" for this.
1635 if (getLexer().is(AsmToken::Percent)) {
1637 if (ParseRegister(IndexReg, L, L)) return 0;
1639 if (getLexer().isNot(AsmToken::RParen)) {
1640 // Parse the scale amount:
1641 // ::= ',' [scale-expression]
1642 if (getLexer().isNot(AsmToken::Comma)) {
1643 Error(Parser.getTok().getLoc(),
1644 "expected comma in scale expression");
1647 Parser.Lex(); // Eat the comma.
1649 if (getLexer().isNot(AsmToken::RParen)) {
1650 SMLoc Loc = Parser.getTok().getLoc();
1653 if (getParser().parseAbsoluteExpression(ScaleVal)){
1654 Error(Loc, "expected scale expression");
1658 // Validate the scale amount.
1659 if (ScaleVal != 1 && ScaleVal != 2 && ScaleVal != 4 && ScaleVal != 8){
1660 Error(Loc, "scale factor in address must be 1, 2, 4 or 8");
1663 Scale = (unsigned)ScaleVal;
1666 } else if (getLexer().isNot(AsmToken::RParen)) {
1667 // A scale amount without an index is ignored.
1669 SMLoc Loc = Parser.getTok().getLoc();
1672 if (getParser().parseAbsoluteExpression(Value))
1676 Warning(Loc, "scale factor without index register is ignored");
1681 // Ok, we've eaten the memory operand, verify we have a ')' and eat it too.
1682 if (getLexer().isNot(AsmToken::RParen)) {
1683 Error(Parser.getTok().getLoc(), "unexpected token in memory operand");
1686 SMLoc MemEnd = Parser.getTok().getEndLoc();
1687 Parser.Lex(); // Eat the ')'.
1689 // If we have both a base register and an index register make sure they are
1690 // both 64-bit or 32-bit registers.
1691 // To support VSIB, IndexReg can be 128-bit or 256-bit registers.
1692 if (BaseReg != 0 && IndexReg != 0) {
1693 if (X86MCRegisterClasses[X86::GR64RegClassID].contains(BaseReg) &&
1694 (X86MCRegisterClasses[X86::GR16RegClassID].contains(IndexReg) ||
1695 X86MCRegisterClasses[X86::GR32RegClassID].contains(IndexReg)) &&
1696 IndexReg != X86::RIZ) {
1697 Error(IndexLoc, "index register is 32-bit, but base register is 64-bit");
1700 if (X86MCRegisterClasses[X86::GR32RegClassID].contains(BaseReg) &&
1701 (X86MCRegisterClasses[X86::GR16RegClassID].contains(IndexReg) ||
1702 X86MCRegisterClasses[X86::GR64RegClassID].contains(IndexReg)) &&
1703 IndexReg != X86::EIZ){
1704 Error(IndexLoc, "index register is 64-bit, but base register is 32-bit");
1709 return X86Operand::CreateMem(SegReg, Disp, BaseReg, IndexReg, Scale,
1714 ParseInstruction(ParseInstructionInfo &Info, StringRef Name, SMLoc NameLoc,
1715 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1717 StringRef PatchedName = Name;
1719 // FIXME: Hack to recognize setneb as setne.
1720 if (PatchedName.startswith("set") && PatchedName.endswith("b") &&
1721 PatchedName != "setb" && PatchedName != "setnb")
1722 PatchedName = PatchedName.substr(0, Name.size()-1);
1724 // FIXME: Hack to recognize cmp<comparison code>{ss,sd,ps,pd}.
1725 const MCExpr *ExtraImmOp = 0;
1726 if ((PatchedName.startswith("cmp") || PatchedName.startswith("vcmp")) &&
1727 (PatchedName.endswith("ss") || PatchedName.endswith("sd") ||
1728 PatchedName.endswith("ps") || PatchedName.endswith("pd"))) {
1729 bool IsVCMP = PatchedName[0] == 'v';
1730 unsigned SSECCIdx = IsVCMP ? 4 : 3;
1731 unsigned SSEComparisonCode = StringSwitch<unsigned>(
1732 PatchedName.slice(SSECCIdx, PatchedName.size() - 2))
1736 .Case("unord", 0x03)
1741 /* AVX only from here */
1742 .Case("eq_uq", 0x08)
1745 .Case("false", 0x0B)
1746 .Case("neq_oq", 0x0C)
1750 .Case("eq_os", 0x10)
1751 .Case("lt_oq", 0x11)
1752 .Case("le_oq", 0x12)
1753 .Case("unord_s", 0x13)
1754 .Case("neq_us", 0x14)
1755 .Case("nlt_uq", 0x15)
1756 .Case("nle_uq", 0x16)
1757 .Case("ord_s", 0x17)
1758 .Case("eq_us", 0x18)
1759 .Case("nge_uq", 0x19)
1760 .Case("ngt_uq", 0x1A)
1761 .Case("false_os", 0x1B)
1762 .Case("neq_os", 0x1C)
1763 .Case("ge_oq", 0x1D)
1764 .Case("gt_oq", 0x1E)
1765 .Case("true_us", 0x1F)
1767 if (SSEComparisonCode != ~0U && (IsVCMP || SSEComparisonCode < 8)) {
1768 ExtraImmOp = MCConstantExpr::Create(SSEComparisonCode,
1769 getParser().getContext());
1770 if (PatchedName.endswith("ss")) {
1771 PatchedName = IsVCMP ? "vcmpss" : "cmpss";
1772 } else if (PatchedName.endswith("sd")) {
1773 PatchedName = IsVCMP ? "vcmpsd" : "cmpsd";
1774 } else if (PatchedName.endswith("ps")) {
1775 PatchedName = IsVCMP ? "vcmpps" : "cmpps";
1777 assert(PatchedName.endswith("pd") && "Unexpected mnemonic!");
1778 PatchedName = IsVCMP ? "vcmppd" : "cmppd";
1783 Operands.push_back(X86Operand::CreateToken(PatchedName, NameLoc));
1785 if (ExtraImmOp && !isParsingIntelSyntax())
1786 Operands.push_back(X86Operand::CreateImm(ExtraImmOp, NameLoc, NameLoc));
1788 // Determine whether this is an instruction prefix.
1790 Name == "lock" || Name == "rep" ||
1791 Name == "repe" || Name == "repz" ||
1792 Name == "repne" || Name == "repnz" ||
1793 Name == "rex64" || Name == "data16";
1796 // This does the actual operand parsing. Don't parse any more if we have a
1797 // prefix juxtaposed with an operation like "lock incl 4(%rax)", because we
1798 // just want to parse the "lock" as the first instruction and the "incl" as
1800 if (getLexer().isNot(AsmToken::EndOfStatement) && !isPrefix) {
1802 // Parse '*' modifier.
1803 if (getLexer().is(AsmToken::Star)) {
1804 SMLoc Loc = Parser.getTok().getLoc();
1805 Operands.push_back(X86Operand::CreateToken("*", Loc));
1806 Parser.Lex(); // Eat the star.
1809 // Read the first operand.
1810 if (X86Operand *Op = ParseOperand())
1811 Operands.push_back(Op);
1813 Parser.eatToEndOfStatement();
1817 while (getLexer().is(AsmToken::Comma)) {
1818 Parser.Lex(); // Eat the comma.
1820 // Parse and remember the operand.
1821 if (X86Operand *Op = ParseOperand())
1822 Operands.push_back(Op);
1824 Parser.eatToEndOfStatement();
1829 if (getLexer().isNot(AsmToken::EndOfStatement)) {
1830 SMLoc Loc = getLexer().getLoc();
1831 Parser.eatToEndOfStatement();
1832 return Error(Loc, "unexpected token in argument list");
1836 if (getLexer().is(AsmToken::EndOfStatement))
1837 Parser.Lex(); // Consume the EndOfStatement
1838 else if (isPrefix && getLexer().is(AsmToken::Slash))
1839 Parser.Lex(); // Consume the prefix separator Slash
1841 if (ExtraImmOp && isParsingIntelSyntax())
1842 Operands.push_back(X86Operand::CreateImm(ExtraImmOp, NameLoc, NameLoc));
1844 // This is a terrible hack to handle "out[bwl]? %al, (%dx)" ->
1845 // "outb %al, %dx". Out doesn't take a memory form, but this is a widely
1846 // documented form in various unofficial manuals, so a lot of code uses it.
1847 if ((Name == "outb" || Name == "outw" || Name == "outl" || Name == "out") &&
1848 Operands.size() == 3) {
1849 X86Operand &Op = *(X86Operand*)Operands.back();
1850 if (Op.isMem() && Op.Mem.SegReg == 0 &&
1851 isa<MCConstantExpr>(Op.Mem.Disp) &&
1852 cast<MCConstantExpr>(Op.Mem.Disp)->getValue() == 0 &&
1853 Op.Mem.BaseReg == MatchRegisterName("dx") && Op.Mem.IndexReg == 0) {
1854 SMLoc Loc = Op.getEndLoc();
1855 Operands.back() = X86Operand::CreateReg(Op.Mem.BaseReg, Loc, Loc);
1859 // Same hack for "in[bwl]? (%dx), %al" -> "inb %dx, %al".
1860 if ((Name == "inb" || Name == "inw" || Name == "inl" || Name == "in") &&
1861 Operands.size() == 3) {
1862 X86Operand &Op = *(X86Operand*)Operands.begin()[1];
1863 if (Op.isMem() && Op.Mem.SegReg == 0 &&
1864 isa<MCConstantExpr>(Op.Mem.Disp) &&
1865 cast<MCConstantExpr>(Op.Mem.Disp)->getValue() == 0 &&
1866 Op.Mem.BaseReg == MatchRegisterName("dx") && Op.Mem.IndexReg == 0) {
1867 SMLoc Loc = Op.getEndLoc();
1868 Operands.begin()[1] = X86Operand::CreateReg(Op.Mem.BaseReg, Loc, Loc);
1872 // Transform "ins[bwl] %dx, %es:(%edi)" into "ins[bwl]"
1873 if (Name.startswith("ins") && Operands.size() == 3 &&
1874 (Name == "insb" || Name == "insw" || Name == "insl")) {
1875 X86Operand &Op = *(X86Operand*)Operands.begin()[1];
1876 X86Operand &Op2 = *(X86Operand*)Operands.begin()[2];
1877 if (Op.isReg() && Op.getReg() == X86::DX && isDstOp(Op2)) {
1878 Operands.pop_back();
1879 Operands.pop_back();
1885 // Transform "outs[bwl] %ds:(%esi), %dx" into "out[bwl]"
1886 if (Name.startswith("outs") && Operands.size() == 3 &&
1887 (Name == "outsb" || Name == "outsw" || Name == "outsl")) {
1888 X86Operand &Op = *(X86Operand*)Operands.begin()[1];
1889 X86Operand &Op2 = *(X86Operand*)Operands.begin()[2];
1890 if (isSrcOp(Op) && Op2.isReg() && Op2.getReg() == X86::DX) {
1891 Operands.pop_back();
1892 Operands.pop_back();
1898 // Transform "movs[bwl] %ds:(%esi), %es:(%edi)" into "movs[bwl]"
1899 if (Name.startswith("movs") && Operands.size() == 3 &&
1900 (Name == "movsb" || Name == "movsw" || Name == "movsl" ||
1901 (is64BitMode() && Name == "movsq"))) {
1902 X86Operand &Op = *(X86Operand*)Operands.begin()[1];
1903 X86Operand &Op2 = *(X86Operand*)Operands.begin()[2];
1904 if (isSrcOp(Op) && isDstOp(Op2)) {
1905 Operands.pop_back();
1906 Operands.pop_back();
1911 // Transform "lods[bwl] %ds:(%esi),{%al,%ax,%eax,%rax}" into "lods[bwl]"
1912 if (Name.startswith("lods") && Operands.size() == 3 &&
1913 (Name == "lods" || Name == "lodsb" || Name == "lodsw" ||
1914 Name == "lodsl" || (is64BitMode() && Name == "lodsq"))) {
1915 X86Operand *Op1 = static_cast<X86Operand*>(Operands[1]);
1916 X86Operand *Op2 = static_cast<X86Operand*>(Operands[2]);
1917 if (isSrcOp(*Op1) && Op2->isReg()) {
1919 unsigned reg = Op2->getReg();
1920 bool isLods = Name == "lods";
1921 if (reg == X86::AL && (isLods || Name == "lodsb"))
1923 else if (reg == X86::AX && (isLods || Name == "lodsw"))
1925 else if (reg == X86::EAX && (isLods || Name == "lodsl"))
1927 else if (reg == X86::RAX && (isLods || Name == "lodsq"))
1932 Operands.pop_back();
1933 Operands.pop_back();
1937 static_cast<X86Operand*>(Operands[0])->setTokenValue(ins);
1941 // Transform "stos[bwl] {%al,%ax,%eax,%rax},%es:(%edi)" into "stos[bwl]"
1942 if (Name.startswith("stos") && Operands.size() == 3 &&
1943 (Name == "stos" || Name == "stosb" || Name == "stosw" ||
1944 Name == "stosl" || (is64BitMode() && Name == "stosq"))) {
1945 X86Operand *Op1 = static_cast<X86Operand*>(Operands[1]);
1946 X86Operand *Op2 = static_cast<X86Operand*>(Operands[2]);
1947 if (isDstOp(*Op2) && Op1->isReg()) {
1949 unsigned reg = Op1->getReg();
1950 bool isStos = Name == "stos";
1951 if (reg == X86::AL && (isStos || Name == "stosb"))
1953 else if (reg == X86::AX && (isStos || Name == "stosw"))
1955 else if (reg == X86::EAX && (isStos || Name == "stosl"))
1957 else if (reg == X86::RAX && (isStos || Name == "stosq"))
1962 Operands.pop_back();
1963 Operands.pop_back();
1967 static_cast<X86Operand*>(Operands[0])->setTokenValue(ins);
1972 // FIXME: Hack to handle recognize s{hr,ar,hl} $1, <op>. Canonicalize to
1974 if ((Name.startswith("shr") || Name.startswith("sar") ||
1975 Name.startswith("shl") || Name.startswith("sal") ||
1976 Name.startswith("rcl") || Name.startswith("rcr") ||
1977 Name.startswith("rol") || Name.startswith("ror")) &&
1978 Operands.size() == 3) {
1979 if (isParsingIntelSyntax()) {
1981 X86Operand *Op1 = static_cast<X86Operand*>(Operands[2]);
1982 if (Op1->isImm() && isa<MCConstantExpr>(Op1->getImm()) &&
1983 cast<MCConstantExpr>(Op1->getImm())->getValue() == 1) {
1985 Operands.pop_back();
1988 X86Operand *Op1 = static_cast<X86Operand*>(Operands[1]);
1989 if (Op1->isImm() && isa<MCConstantExpr>(Op1->getImm()) &&
1990 cast<MCConstantExpr>(Op1->getImm())->getValue() == 1) {
1992 Operands.erase(Operands.begin() + 1);
1997 // Transforms "int $3" into "int3" as a size optimization. We can't write an
1998 // instalias with an immediate operand yet.
1999 if (Name == "int" && Operands.size() == 2) {
2000 X86Operand *Op1 = static_cast<X86Operand*>(Operands[1]);
2001 if (Op1->isImm() && isa<MCConstantExpr>(Op1->getImm()) &&
2002 cast<MCConstantExpr>(Op1->getImm())->getValue() == 3) {
2004 Operands.erase(Operands.begin() + 1);
2005 static_cast<X86Operand*>(Operands[0])->setTokenValue("int3");
2012 static bool convertToSExti8(MCInst &Inst, unsigned Opcode, unsigned Reg,
2015 TmpInst.setOpcode(Opcode);
2017 TmpInst.addOperand(MCOperand::CreateReg(Reg));
2018 TmpInst.addOperand(MCOperand::CreateReg(Reg));
2019 TmpInst.addOperand(Inst.getOperand(0));
2024 static bool convert16i16to16ri8(MCInst &Inst, unsigned Opcode,
2025 bool isCmp = false) {
2026 if (!Inst.getOperand(0).isImm() ||
2027 !isImmSExti16i8Value(Inst.getOperand(0).getImm()))
2030 return convertToSExti8(Inst, Opcode, X86::AX, isCmp);
2033 static bool convert32i32to32ri8(MCInst &Inst, unsigned Opcode,
2034 bool isCmp = false) {
2035 if (!Inst.getOperand(0).isImm() ||
2036 !isImmSExti32i8Value(Inst.getOperand(0).getImm()))
2039 return convertToSExti8(Inst, Opcode, X86::EAX, isCmp);
2042 static bool convert64i32to64ri8(MCInst &Inst, unsigned Opcode,
2043 bool isCmp = false) {
2044 if (!Inst.getOperand(0).isImm() ||
2045 !isImmSExti64i8Value(Inst.getOperand(0).getImm()))
2048 return convertToSExti8(Inst, Opcode, X86::RAX, isCmp);
2052 processInstruction(MCInst &Inst,
2053 const SmallVectorImpl<MCParsedAsmOperand*> &Ops) {
2054 switch (Inst.getOpcode()) {
2055 default: return false;
2056 case X86::AND16i16: return convert16i16to16ri8(Inst, X86::AND16ri8);
2057 case X86::AND32i32: return convert32i32to32ri8(Inst, X86::AND32ri8);
2058 case X86::AND64i32: return convert64i32to64ri8(Inst, X86::AND64ri8);
2059 case X86::XOR16i16: return convert16i16to16ri8(Inst, X86::XOR16ri8);
2060 case X86::XOR32i32: return convert32i32to32ri8(Inst, X86::XOR32ri8);
2061 case X86::XOR64i32: return convert64i32to64ri8(Inst, X86::XOR64ri8);
2062 case X86::OR16i16: return convert16i16to16ri8(Inst, X86::OR16ri8);
2063 case X86::OR32i32: return convert32i32to32ri8(Inst, X86::OR32ri8);
2064 case X86::OR64i32: return convert64i32to64ri8(Inst, X86::OR64ri8);
2065 case X86::CMP16i16: return convert16i16to16ri8(Inst, X86::CMP16ri8, true);
2066 case X86::CMP32i32: return convert32i32to32ri8(Inst, X86::CMP32ri8, true);
2067 case X86::CMP64i32: return convert64i32to64ri8(Inst, X86::CMP64ri8, true);
2068 case X86::ADD16i16: return convert16i16to16ri8(Inst, X86::ADD16ri8);
2069 case X86::ADD32i32: return convert32i32to32ri8(Inst, X86::ADD32ri8);
2070 case X86::ADD64i32: return convert64i32to64ri8(Inst, X86::ADD64ri8);
2071 case X86::SUB16i16: return convert16i16to16ri8(Inst, X86::SUB16ri8);
2072 case X86::SUB32i32: return convert32i32to32ri8(Inst, X86::SUB32ri8);
2073 case X86::SUB64i32: return convert64i32to64ri8(Inst, X86::SUB64ri8);
2074 case X86::ADC16i16: return convert16i16to16ri8(Inst, X86::ADC16ri8);
2075 case X86::ADC32i32: return convert32i32to32ri8(Inst, X86::ADC32ri8);
2076 case X86::ADC64i32: return convert64i32to64ri8(Inst, X86::ADC64ri8);
2077 case X86::SBB16i16: return convert16i16to16ri8(Inst, X86::SBB16ri8);
2078 case X86::SBB32i32: return convert32i32to32ri8(Inst, X86::SBB32ri8);
2079 case X86::SBB64i32: return convert64i32to64ri8(Inst, X86::SBB64ri8);
2083 static const char *getSubtargetFeatureName(unsigned Val);
2085 MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
2086 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
2087 MCStreamer &Out, unsigned &ErrorInfo,
2088 bool MatchingInlineAsm) {
2089 assert(!Operands.empty() && "Unexpect empty operand list!");
2090 X86Operand *Op = static_cast<X86Operand*>(Operands[0]);
2091 assert(Op->isToken() && "Leading operand should always be a mnemonic!");
2092 ArrayRef<SMRange> EmptyRanges = ArrayRef<SMRange>();
2094 // First, handle aliases that expand to multiple instructions.
2095 // FIXME: This should be replaced with a real .td file alias mechanism.
2096 // Also, MatchInstructionImpl should actually *do* the EmitInstruction
2098 if (Op->getToken() == "fstsw" || Op->getToken() == "fstcw" ||
2099 Op->getToken() == "fstsww" || Op->getToken() == "fstcww" ||
2100 Op->getToken() == "finit" || Op->getToken() == "fsave" ||
2101 Op->getToken() == "fstenv" || Op->getToken() == "fclex") {
2103 Inst.setOpcode(X86::WAIT);
2105 if (!MatchingInlineAsm)
2106 Out.EmitInstruction(Inst);
2109 StringSwitch<const char*>(Op->getToken())
2110 .Case("finit", "fninit")
2111 .Case("fsave", "fnsave")
2112 .Case("fstcw", "fnstcw")
2113 .Case("fstcww", "fnstcw")
2114 .Case("fstenv", "fnstenv")
2115 .Case("fstsw", "fnstsw")
2116 .Case("fstsww", "fnstsw")
2117 .Case("fclex", "fnclex")
2119 assert(Repl && "Unknown wait-prefixed instruction");
2121 Operands[0] = X86Operand::CreateToken(Repl, IDLoc);
2124 bool WasOriginallyInvalidOperand = false;
2127 // First, try a direct match.
2128 switch (MatchInstructionImpl(Operands, Inst,
2129 ErrorInfo, MatchingInlineAsm,
2130 isParsingIntelSyntax())) {
2133 // Some instructions need post-processing to, for example, tweak which
2134 // encoding is selected. Loop on it while changes happen so the
2135 // individual transformations can chain off each other.
2136 if (!MatchingInlineAsm)
2137 while (processInstruction(Inst, Operands))
2141 if (!MatchingInlineAsm)
2142 Out.EmitInstruction(Inst);
2143 Opcode = Inst.getOpcode();
2145 case Match_MissingFeature: {
2146 assert(ErrorInfo && "Unknown missing feature!");
2147 // Special case the error message for the very common case where only
2148 // a single subtarget feature is missing.
2149 std::string Msg = "instruction requires:";
2151 for (unsigned i = 0; i < (sizeof(ErrorInfo)*8-1); ++i) {
2152 if (ErrorInfo & Mask) {
2154 Msg += getSubtargetFeatureName(ErrorInfo & Mask);
2158 return Error(IDLoc, Msg, EmptyRanges, MatchingInlineAsm);
2160 case Match_InvalidOperand:
2161 WasOriginallyInvalidOperand = true;
2163 case Match_MnemonicFail:
2167 // FIXME: Ideally, we would only attempt suffix matches for things which are
2168 // valid prefixes, and we could just infer the right unambiguous
2169 // type. However, that requires substantially more matcher support than the
2172 // Change the operand to point to a temporary token.
2173 StringRef Base = Op->getToken();
2174 SmallString<16> Tmp;
2177 Op->setTokenValue(Tmp.str());
2179 // If this instruction starts with an 'f', then it is a floating point stack
2180 // instruction. These come in up to three forms for 32-bit, 64-bit, and
2181 // 80-bit floating point, which use the suffixes s,l,t respectively.
2183 // Otherwise, we assume that this may be an integer instruction, which comes
2184 // in 8/16/32/64-bit forms using the b,w,l,q suffixes respectively.
2185 const char *Suffixes = Base[0] != 'f' ? "bwlq" : "slt\0";
2187 // Check for the various suffix matches.
2188 Tmp[Base.size()] = Suffixes[0];
2189 unsigned ErrorInfoIgnore;
2190 unsigned ErrorInfoMissingFeature = 0; // Init suppresses compiler warnings.
2191 unsigned Match1, Match2, Match3, Match4;
2193 Match1 = MatchInstructionImpl(Operands, Inst, ErrorInfoIgnore,
2194 isParsingIntelSyntax());
2195 // If this returned as a missing feature failure, remember that.
2196 if (Match1 == Match_MissingFeature)
2197 ErrorInfoMissingFeature = ErrorInfoIgnore;
2198 Tmp[Base.size()] = Suffixes[1];
2199 Match2 = MatchInstructionImpl(Operands, Inst, ErrorInfoIgnore,
2200 isParsingIntelSyntax());
2201 // If this returned as a missing feature failure, remember that.
2202 if (Match2 == Match_MissingFeature)
2203 ErrorInfoMissingFeature = ErrorInfoIgnore;
2204 Tmp[Base.size()] = Suffixes[2];
2205 Match3 = MatchInstructionImpl(Operands, Inst, ErrorInfoIgnore,
2206 isParsingIntelSyntax());
2207 // If this returned as a missing feature failure, remember that.
2208 if (Match3 == Match_MissingFeature)
2209 ErrorInfoMissingFeature = ErrorInfoIgnore;
2210 Tmp[Base.size()] = Suffixes[3];
2211 Match4 = MatchInstructionImpl(Operands, Inst, ErrorInfoIgnore,
2212 isParsingIntelSyntax());
2213 // If this returned as a missing feature failure, remember that.
2214 if (Match4 == Match_MissingFeature)
2215 ErrorInfoMissingFeature = ErrorInfoIgnore;
2217 // Restore the old token.
2218 Op->setTokenValue(Base);
2220 // If exactly one matched, then we treat that as a successful match (and the
2221 // instruction will already have been filled in correctly, since the failing
2222 // matches won't have modified it).
2223 unsigned NumSuccessfulMatches =
2224 (Match1 == Match_Success) + (Match2 == Match_Success) +
2225 (Match3 == Match_Success) + (Match4 == Match_Success);
2226 if (NumSuccessfulMatches == 1) {
2228 if (!MatchingInlineAsm)
2229 Out.EmitInstruction(Inst);
2230 Opcode = Inst.getOpcode();
2234 // Otherwise, the match failed, try to produce a decent error message.
2236 // If we had multiple suffix matches, then identify this as an ambiguous
2238 if (NumSuccessfulMatches > 1) {
2240 unsigned NumMatches = 0;
2241 if (Match1 == Match_Success) MatchChars[NumMatches++] = Suffixes[0];
2242 if (Match2 == Match_Success) MatchChars[NumMatches++] = Suffixes[1];
2243 if (Match3 == Match_Success) MatchChars[NumMatches++] = Suffixes[2];
2244 if (Match4 == Match_Success) MatchChars[NumMatches++] = Suffixes[3];
2246 SmallString<126> Msg;
2247 raw_svector_ostream OS(Msg);
2248 OS << "ambiguous instructions require an explicit suffix (could be ";
2249 for (unsigned i = 0; i != NumMatches; ++i) {
2252 if (i + 1 == NumMatches)
2254 OS << "'" << Base << MatchChars[i] << "'";
2257 Error(IDLoc, OS.str(), EmptyRanges, MatchingInlineAsm);
2261 // Okay, we know that none of the variants matched successfully.
2263 // If all of the instructions reported an invalid mnemonic, then the original
2264 // mnemonic was invalid.
2265 if ((Match1 == Match_MnemonicFail) && (Match2 == Match_MnemonicFail) &&
2266 (Match3 == Match_MnemonicFail) && (Match4 == Match_MnemonicFail)) {
2267 if (!WasOriginallyInvalidOperand) {
2268 ArrayRef<SMRange> Ranges = MatchingInlineAsm ? EmptyRanges :
2270 return Error(IDLoc, "invalid instruction mnemonic '" + Base + "'",
2271 Ranges, MatchingInlineAsm);
2274 // Recover location info for the operand if we know which was the problem.
2275 if (ErrorInfo != ~0U) {
2276 if (ErrorInfo >= Operands.size())
2277 return Error(IDLoc, "too few operands for instruction",
2278 EmptyRanges, MatchingInlineAsm);
2280 X86Operand *Operand = (X86Operand*)Operands[ErrorInfo];
2281 if (Operand->getStartLoc().isValid()) {
2282 SMRange OperandRange = Operand->getLocRange();
2283 return Error(Operand->getStartLoc(), "invalid operand for instruction",
2284 OperandRange, MatchingInlineAsm);
2288 return Error(IDLoc, "invalid operand for instruction", EmptyRanges,
2292 // If one instruction matched with a missing feature, report this as a
2294 if ((Match1 == Match_MissingFeature) + (Match2 == Match_MissingFeature) +
2295 (Match3 == Match_MissingFeature) + (Match4 == Match_MissingFeature) == 1){
2296 std::string Msg = "instruction requires:";
2298 for (unsigned i = 0; i < (sizeof(ErrorInfoMissingFeature)*8-1); ++i) {
2299 if (ErrorInfoMissingFeature & Mask) {
2301 Msg += getSubtargetFeatureName(ErrorInfoMissingFeature & Mask);
2305 return Error(IDLoc, Msg, EmptyRanges, MatchingInlineAsm);
2308 // If one instruction matched with an invalid operand, report this as an
2310 if ((Match1 == Match_InvalidOperand) + (Match2 == Match_InvalidOperand) +
2311 (Match3 == Match_InvalidOperand) + (Match4 == Match_InvalidOperand) == 1){
2312 Error(IDLoc, "invalid operand for instruction", EmptyRanges,
2317 // If all of these were an outright failure, report it in a useless way.
2318 Error(IDLoc, "unknown use of instruction mnemonic without a size suffix",
2319 EmptyRanges, MatchingInlineAsm);
2324 bool X86AsmParser::ParseDirective(AsmToken DirectiveID) {
2325 StringRef IDVal = DirectiveID.getIdentifier();
2326 if (IDVal == ".word")
2327 return ParseDirectiveWord(2, DirectiveID.getLoc());
2328 else if (IDVal.startswith(".code"))
2329 return ParseDirectiveCode(IDVal, DirectiveID.getLoc());
2330 else if (IDVal.startswith(".att_syntax")) {
2331 getParser().setAssemblerDialect(0);
2333 } else if (IDVal.startswith(".intel_syntax")) {
2334 getParser().setAssemblerDialect(1);
2335 if (getLexer().isNot(AsmToken::EndOfStatement)) {
2336 if(Parser.getTok().getString() == "noprefix") {
2337 // FIXME : Handle noprefix
2347 /// ParseDirectiveWord
2348 /// ::= .word [ expression (, expression)* ]
2349 bool X86AsmParser::ParseDirectiveWord(unsigned Size, SMLoc L) {
2350 if (getLexer().isNot(AsmToken::EndOfStatement)) {
2352 const MCExpr *Value;
2353 if (getParser().parseExpression(Value))
2356 getParser().getStreamer().EmitValue(Value, Size);
2358 if (getLexer().is(AsmToken::EndOfStatement))
2361 // FIXME: Improve diagnostic.
2362 if (getLexer().isNot(AsmToken::Comma))
2363 return Error(L, "unexpected token in directive");
2372 /// ParseDirectiveCode
2373 /// ::= .code32 | .code64
2374 bool X86AsmParser::ParseDirectiveCode(StringRef IDVal, SMLoc L) {
2375 if (IDVal == ".code32") {
2377 if (is64BitMode()) {
2379 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
2381 } else if (IDVal == ".code64") {
2383 if (!is64BitMode()) {
2385 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code64);
2388 return Error(L, "unexpected directive " + IDVal);
2394 // Force static initialization.
2395 extern "C" void LLVMInitializeX86AsmParser() {
2396 RegisterMCAsmParser<X86AsmParser> X(TheX86_32Target);
2397 RegisterMCAsmParser<X86AsmParser> Y(TheX86_64Target);
2400 #define GET_REGISTER_MATCHER
2401 #define GET_MATCHER_IMPLEMENTATION
2402 #define GET_SUBTARGET_FEATURE_NAME
2403 #include "X86GenAsmMatcher.inc"