1 //===-- X86AsmParser.cpp - Parse X86 assembly to MCInst instructions ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "llvm/Target/TargetAsmParser.h"
12 #include "X86Subtarget.h"
13 #include "llvm/Target/TargetRegistry.h"
14 #include "llvm/Target/TargetAsmParser.h"
15 #include "llvm/MC/MCStreamer.h"
16 #include "llvm/MC/MCExpr.h"
17 #include "llvm/MC/MCInst.h"
18 #include "llvm/MC/MCParser/MCAsmLexer.h"
19 #include "llvm/MC/MCParser/MCAsmParser.h"
20 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
21 #include "llvm/ADT/SmallString.h"
22 #include "llvm/ADT/SmallVector.h"
23 #include "llvm/ADT/StringExtras.h"
24 #include "llvm/ADT/StringSwitch.h"
25 #include "llvm/ADT/Twine.h"
26 #include "llvm/Support/SourceMgr.h"
27 #include "llvm/Support/raw_ostream.h"
33 class X86ATTAsmParser : public TargetAsmParser {
41 MCAsmParser &getParser() const { return Parser; }
43 MCAsmLexer &getLexer() const { return Parser.getLexer(); }
45 bool Error(SMLoc L, const Twine &Msg) { return Parser.Error(L, Msg); }
47 bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc);
49 X86Operand *ParseOperand();
50 X86Operand *ParseMemOperand(unsigned SegReg, SMLoc StartLoc);
52 bool ParseDirectiveWord(unsigned Size, SMLoc L);
54 bool MatchAndEmitInstruction(SMLoc IDLoc,
55 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
58 /// @name Auto-generated Matcher Functions
61 #define GET_ASSEMBLER_HEADER
62 #include "X86GenAsmMatcher.inc"
67 X86ATTAsmParser(const Target &T, MCAsmParser &_Parser, TargetMachine &TM)
68 : TargetAsmParser(T), Parser(_Parser), TM(TM) {
70 // Initialize the set of available features.
71 setAvailableFeatures(ComputeAvailableFeatures(
72 &TM.getSubtarget<X86Subtarget>()));
75 virtual bool ParseInstruction(StringRef Name, SMLoc NameLoc,
76 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
78 virtual bool ParseDirective(AsmToken DirectiveID);
81 class X86_32ATTAsmParser : public X86ATTAsmParser {
83 X86_32ATTAsmParser(const Target &T, MCAsmParser &_Parser, TargetMachine &TM)
84 : X86ATTAsmParser(T, _Parser, TM) {
89 class X86_64ATTAsmParser : public X86ATTAsmParser {
91 X86_64ATTAsmParser(const Target &T, MCAsmParser &_Parser, TargetMachine &TM)
92 : X86ATTAsmParser(T, _Parser, TM) {
97 } // end anonymous namespace
99 /// @name Auto-generated Match Functions
102 static unsigned MatchRegisterName(StringRef Name);
108 /// X86Operand - Instances of this class represent a parsed X86 machine
110 struct X86Operand : public MCParsedAsmOperand {
118 SMLoc StartLoc, EndLoc;
143 X86Operand(KindTy K, SMLoc Start, SMLoc End)
144 : Kind(K), StartLoc(Start), EndLoc(End) {}
146 /// getStartLoc - Get the location of the first token of this operand.
147 SMLoc getStartLoc() const { return StartLoc; }
148 /// getEndLoc - Get the location of the last token of this operand.
149 SMLoc getEndLoc() const { return EndLoc; }
151 virtual void dump(raw_ostream &OS) const {}
153 StringRef getToken() const {
154 assert(Kind == Token && "Invalid access!");
155 return StringRef(Tok.Data, Tok.Length);
157 void setTokenValue(StringRef Value) {
158 assert(Kind == Token && "Invalid access!");
159 Tok.Data = Value.data();
160 Tok.Length = Value.size();
163 unsigned getReg() const {
164 assert(Kind == Register && "Invalid access!");
168 const MCExpr *getImm() const {
169 assert(Kind == Immediate && "Invalid access!");
173 const MCExpr *getMemDisp() const {
174 assert(Kind == Memory && "Invalid access!");
177 unsigned getMemSegReg() const {
178 assert(Kind == Memory && "Invalid access!");
181 unsigned getMemBaseReg() const {
182 assert(Kind == Memory && "Invalid access!");
185 unsigned getMemIndexReg() const {
186 assert(Kind == Memory && "Invalid access!");
189 unsigned getMemScale() const {
190 assert(Kind == Memory && "Invalid access!");
194 bool isToken() const {return Kind == Token; }
196 bool isImm() const { return Kind == Immediate; }
198 bool isImmSExti16i8() const {
202 // If this isn't a constant expr, just assume it fits and let relaxation
204 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
208 // Otherwise, check the value is in a range that makes sense for this
210 uint64_t Value = CE->getValue();
211 return (( Value <= 0x000000000000007FULL)||
212 (0x000000000000FF80ULL <= Value && Value <= 0x000000000000FFFFULL)||
213 (0xFFFFFFFFFFFFFF80ULL <= Value && Value <= 0xFFFFFFFFFFFFFFFFULL));
215 bool isImmSExti32i8() const {
219 // If this isn't a constant expr, just assume it fits and let relaxation
221 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
225 // Otherwise, check the value is in a range that makes sense for this
227 uint64_t Value = CE->getValue();
228 return (( Value <= 0x000000000000007FULL)||
229 (0x00000000FFFFFF80ULL <= Value && Value <= 0x00000000FFFFFFFFULL)||
230 (0xFFFFFFFFFFFFFF80ULL <= Value && Value <= 0xFFFFFFFFFFFFFFFFULL));
232 bool isImmSExti64i8() const {
236 // If this isn't a constant expr, just assume it fits and let relaxation
238 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
242 // Otherwise, check the value is in a range that makes sense for this
244 uint64_t Value = CE->getValue();
245 return (( Value <= 0x000000000000007FULL)||
246 (0xFFFFFFFFFFFFFF80ULL <= Value && Value <= 0xFFFFFFFFFFFFFFFFULL));
248 bool isImmSExti64i32() const {
252 // If this isn't a constant expr, just assume it fits and let relaxation
254 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
258 // Otherwise, check the value is in a range that makes sense for this
260 uint64_t Value = CE->getValue();
261 return (( Value <= 0x000000007FFFFFFFULL)||
262 (0xFFFFFFFF80000000ULL <= Value && Value <= 0xFFFFFFFFFFFFFFFFULL));
265 bool isMem() const { return Kind == Memory; }
267 bool isAbsMem() const {
268 return Kind == Memory && !getMemSegReg() && !getMemBaseReg() &&
269 !getMemIndexReg() && getMemScale() == 1;
272 bool isReg() const { return Kind == Register; }
274 void addExpr(MCInst &Inst, const MCExpr *Expr) const {
275 // Add as immediates when possible.
276 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
277 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
279 Inst.addOperand(MCOperand::CreateExpr(Expr));
282 void addRegOperands(MCInst &Inst, unsigned N) const {
283 assert(N == 1 && "Invalid number of operands!");
284 Inst.addOperand(MCOperand::CreateReg(getReg()));
287 void addImmOperands(MCInst &Inst, unsigned N) const {
288 assert(N == 1 && "Invalid number of operands!");
289 addExpr(Inst, getImm());
292 void addMemOperands(MCInst &Inst, unsigned N) const {
293 assert((N == 5) && "Invalid number of operands!");
294 Inst.addOperand(MCOperand::CreateReg(getMemBaseReg()));
295 Inst.addOperand(MCOperand::CreateImm(getMemScale()));
296 Inst.addOperand(MCOperand::CreateReg(getMemIndexReg()));
297 addExpr(Inst, getMemDisp());
298 Inst.addOperand(MCOperand::CreateReg(getMemSegReg()));
301 void addAbsMemOperands(MCInst &Inst, unsigned N) const {
302 assert((N == 1) && "Invalid number of operands!");
303 Inst.addOperand(MCOperand::CreateExpr(getMemDisp()));
306 static X86Operand *CreateToken(StringRef Str, SMLoc Loc) {
307 X86Operand *Res = new X86Operand(Token, Loc, Loc);
308 Res->Tok.Data = Str.data();
309 Res->Tok.Length = Str.size();
313 static X86Operand *CreateReg(unsigned RegNo, SMLoc StartLoc, SMLoc EndLoc) {
314 X86Operand *Res = new X86Operand(Register, StartLoc, EndLoc);
315 Res->Reg.RegNo = RegNo;
319 static X86Operand *CreateImm(const MCExpr *Val, SMLoc StartLoc, SMLoc EndLoc){
320 X86Operand *Res = new X86Operand(Immediate, StartLoc, EndLoc);
325 /// Create an absolute memory operand.
326 static X86Operand *CreateMem(const MCExpr *Disp, SMLoc StartLoc,
328 X86Operand *Res = new X86Operand(Memory, StartLoc, EndLoc);
330 Res->Mem.Disp = Disp;
331 Res->Mem.BaseReg = 0;
332 Res->Mem.IndexReg = 0;
337 /// Create a generalized memory operand.
338 static X86Operand *CreateMem(unsigned SegReg, const MCExpr *Disp,
339 unsigned BaseReg, unsigned IndexReg,
340 unsigned Scale, SMLoc StartLoc, SMLoc EndLoc) {
341 // We should never just have a displacement, that should be parsed as an
342 // absolute memory operand.
343 assert((SegReg || BaseReg || IndexReg) && "Invalid memory operand!");
345 // The scale should always be one of {1,2,4,8}.
346 assert(((Scale == 1 || Scale == 2 || Scale == 4 || Scale == 8)) &&
348 X86Operand *Res = new X86Operand(Memory, StartLoc, EndLoc);
349 Res->Mem.SegReg = SegReg;
350 Res->Mem.Disp = Disp;
351 Res->Mem.BaseReg = BaseReg;
352 Res->Mem.IndexReg = IndexReg;
353 Res->Mem.Scale = Scale;
358 } // end anonymous namespace.
361 bool X86ATTAsmParser::ParseRegister(unsigned &RegNo,
362 SMLoc &StartLoc, SMLoc &EndLoc) {
364 const AsmToken &TokPercent = Parser.getTok();
365 assert(TokPercent.is(AsmToken::Percent) && "Invalid token kind!");
366 StartLoc = TokPercent.getLoc();
367 Parser.Lex(); // Eat percent token.
369 const AsmToken &Tok = Parser.getTok();
370 if (Tok.isNot(AsmToken::Identifier))
371 return Error(Tok.getLoc(), "invalid register name");
373 // FIXME: Validate register for the current architecture; we have to do
374 // validation later, so maybe there is no need for this here.
375 RegNo = MatchRegisterName(Tok.getString());
377 // If the match failed, try the register name as lowercase.
379 RegNo = MatchRegisterName(LowercaseString(Tok.getString()));
381 // FIXME: This should be done using Requires<In32BitMode> and
382 // Requires<In64BitMode> so "eiz" usage in 64-bit instructions
383 // can be also checked.
384 if (RegNo == X86::RIZ && !Is64Bit)
385 return Error(Tok.getLoc(), "riz register in 64-bit mode only");
387 // Parse "%st" as "%st(0)" and "%st(1)", which is multiple tokens.
388 if (RegNo == 0 && (Tok.getString() == "st" || Tok.getString() == "ST")) {
390 EndLoc = Tok.getLoc();
391 Parser.Lex(); // Eat 'st'
393 // Check to see if we have '(4)' after %st.
394 if (getLexer().isNot(AsmToken::LParen))
399 const AsmToken &IntTok = Parser.getTok();
400 if (IntTok.isNot(AsmToken::Integer))
401 return Error(IntTok.getLoc(), "expected stack index");
402 switch (IntTok.getIntVal()) {
403 case 0: RegNo = X86::ST0; break;
404 case 1: RegNo = X86::ST1; break;
405 case 2: RegNo = X86::ST2; break;
406 case 3: RegNo = X86::ST3; break;
407 case 4: RegNo = X86::ST4; break;
408 case 5: RegNo = X86::ST5; break;
409 case 6: RegNo = X86::ST6; break;
410 case 7: RegNo = X86::ST7; break;
411 default: return Error(IntTok.getLoc(), "invalid stack index");
414 if (getParser().Lex().isNot(AsmToken::RParen))
415 return Error(Parser.getTok().getLoc(), "expected ')'");
417 EndLoc = Tok.getLoc();
418 Parser.Lex(); // Eat ')'
422 // If this is "db[0-7]", match it as an alias
424 if (RegNo == 0 && Tok.getString().size() == 3 &&
425 Tok.getString().startswith("db")) {
426 switch (Tok.getString()[2]) {
427 case '0': RegNo = X86::DR0; break;
428 case '1': RegNo = X86::DR1; break;
429 case '2': RegNo = X86::DR2; break;
430 case '3': RegNo = X86::DR3; break;
431 case '4': RegNo = X86::DR4; break;
432 case '5': RegNo = X86::DR5; break;
433 case '6': RegNo = X86::DR6; break;
434 case '7': RegNo = X86::DR7; break;
438 EndLoc = Tok.getLoc();
439 Parser.Lex(); // Eat it.
445 return Error(Tok.getLoc(), "invalid register name");
447 EndLoc = Tok.getLoc();
448 Parser.Lex(); // Eat identifier token.
452 X86Operand *X86ATTAsmParser::ParseOperand() {
453 switch (getLexer().getKind()) {
455 // Parse a memory operand with no segment register.
456 return ParseMemOperand(0, Parser.getTok().getLoc());
457 case AsmToken::Percent: {
458 // Read the register.
461 if (ParseRegister(RegNo, Start, End)) return 0;
462 if (RegNo == X86::EIZ || RegNo == X86::RIZ) {
463 Error(Start, "eiz and riz can only be used as index registers");
467 // If this is a segment register followed by a ':', then this is the start
468 // of a memory reference, otherwise this is a normal register reference.
469 if (getLexer().isNot(AsmToken::Colon))
470 return X86Operand::CreateReg(RegNo, Start, End);
473 getParser().Lex(); // Eat the colon.
474 return ParseMemOperand(RegNo, Start);
476 case AsmToken::Dollar: {
478 SMLoc Start = Parser.getTok().getLoc(), End;
481 if (getParser().ParseExpression(Val, End))
483 return X86Operand::CreateImm(Val, Start, End);
488 /// ParseMemOperand: segment: disp(basereg, indexreg, scale). The '%ds:' prefix
489 /// has already been parsed if present.
490 X86Operand *X86ATTAsmParser::ParseMemOperand(unsigned SegReg, SMLoc MemStart) {
492 // We have to disambiguate a parenthesized expression "(4+5)" from the start
493 // of a memory operand with a missing displacement "(%ebx)" or "(,%eax)". The
494 // only way to do this without lookahead is to eat the '(' and see what is
496 const MCExpr *Disp = MCConstantExpr::Create(0, getParser().getContext());
497 if (getLexer().isNot(AsmToken::LParen)) {
499 if (getParser().ParseExpression(Disp, ExprEnd)) return 0;
501 // After parsing the base expression we could either have a parenthesized
502 // memory address or not. If not, return now. If so, eat the (.
503 if (getLexer().isNot(AsmToken::LParen)) {
504 // Unless we have a segment register, treat this as an immediate.
506 return X86Operand::CreateMem(Disp, MemStart, ExprEnd);
507 return X86Operand::CreateMem(SegReg, Disp, 0, 0, 1, MemStart, ExprEnd);
513 // Okay, we have a '('. We don't know if this is an expression or not, but
514 // so we have to eat the ( to see beyond it.
515 SMLoc LParenLoc = Parser.getTok().getLoc();
516 Parser.Lex(); // Eat the '('.
518 if (getLexer().is(AsmToken::Percent) || getLexer().is(AsmToken::Comma)) {
519 // Nothing to do here, fall into the code below with the '(' part of the
520 // memory operand consumed.
524 // It must be an parenthesized expression, parse it now.
525 if (getParser().ParseParenExpression(Disp, ExprEnd))
528 // After parsing the base expression we could either have a parenthesized
529 // memory address or not. If not, return now. If so, eat the (.
530 if (getLexer().isNot(AsmToken::LParen)) {
531 // Unless we have a segment register, treat this as an immediate.
533 return X86Operand::CreateMem(Disp, LParenLoc, ExprEnd);
534 return X86Operand::CreateMem(SegReg, Disp, 0, 0, 1, MemStart, ExprEnd);
542 // If we reached here, then we just ate the ( of the memory operand. Process
543 // the rest of the memory operand.
544 unsigned BaseReg = 0, IndexReg = 0, Scale = 1;
546 if (getLexer().is(AsmToken::Percent)) {
548 if (ParseRegister(BaseReg, L, L)) return 0;
549 if (BaseReg == X86::EIZ || BaseReg == X86::RIZ) {
550 Error(L, "eiz and riz can only be used as index registers");
555 if (getLexer().is(AsmToken::Comma)) {
556 Parser.Lex(); // Eat the comma.
558 // Following the comma we should have either an index register, or a scale
559 // value. We don't support the later form, but we want to parse it
562 // Not that even though it would be completely consistent to support syntax
563 // like "1(%eax,,1)", the assembler doesn't. Use "eiz" or "riz" for this.
564 if (getLexer().is(AsmToken::Percent)) {
566 if (ParseRegister(IndexReg, L, L)) return 0;
568 if (getLexer().isNot(AsmToken::RParen)) {
569 // Parse the scale amount:
570 // ::= ',' [scale-expression]
571 if (getLexer().isNot(AsmToken::Comma)) {
572 Error(Parser.getTok().getLoc(),
573 "expected comma in scale expression");
576 Parser.Lex(); // Eat the comma.
578 if (getLexer().isNot(AsmToken::RParen)) {
579 SMLoc Loc = Parser.getTok().getLoc();
582 if (getParser().ParseAbsoluteExpression(ScaleVal))
585 // Validate the scale amount.
586 if (ScaleVal != 1 && ScaleVal != 2 && ScaleVal != 4 && ScaleVal != 8){
587 Error(Loc, "scale factor in address must be 1, 2, 4 or 8");
590 Scale = (unsigned)ScaleVal;
593 } else if (getLexer().isNot(AsmToken::RParen)) {
594 // A scale amount without an index is ignored.
596 SMLoc Loc = Parser.getTok().getLoc();
599 if (getParser().ParseAbsoluteExpression(Value))
603 Warning(Loc, "scale factor without index register is ignored");
608 // Ok, we've eaten the memory operand, verify we have a ')' and eat it too.
609 if (getLexer().isNot(AsmToken::RParen)) {
610 Error(Parser.getTok().getLoc(), "unexpected token in memory operand");
613 SMLoc MemEnd = Parser.getTok().getLoc();
614 Parser.Lex(); // Eat the ')'.
616 return X86Operand::CreateMem(SegReg, Disp, BaseReg, IndexReg, Scale,
620 bool X86ATTAsmParser::
621 ParseInstruction(StringRef Name, SMLoc NameLoc,
622 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
623 // FIXME: Hack to recognize "sal..." and "rep..." for now. We need a way to
624 // represent alternative syntaxes in the .td file, without requiring
625 // instruction duplication.
626 StringRef PatchedName = StringSwitch<StringRef>(Name)
628 .Case("salb", "shlb")
629 .Case("sall", "shll")
630 .Case("salq", "shlq")
631 .Case("salw", "shlw")
634 .Case("repnz", "repne")
635 .Case("iret", "iretl")
636 .Case("sysret", "sysretl")
640 .Case("cwde", "cwtl")
641 .Case("cdqe", "cltq")
642 .Case("smovb", "movsb")
643 .Case("smovw", "movsw")
644 .Case("smovl", "movsl")
645 .Case("smovq", "movsq")
646 .Case("push", Is64Bit ? "pushq" : "pushl")
647 .Case("pop", Is64Bit ? "popq" : "popl")
648 .Case("pushf", Is64Bit ? "pushfq" : "pushfl")
649 .Case("popf", Is64Bit ? "popfq" : "popfl")
650 .Case("pushfd", "pushfl")
651 .Case("popfd", "popfl")
652 .Case("retl", Is64Bit ? "retl" : "ret")
653 .Case("retq", Is64Bit ? "ret" : "retq")
654 .Case("setz", "sete") .Case("setnz", "setne")
655 .Case("setc", "setb") .Case("setna", "setbe")
656 .Case("setnae", "setb").Case("setnb", "setae")
657 .Case("setnbe", "seta").Case("setnc", "setae")
658 .Case("setng", "setle").Case("setnge", "setl")
659 .Case("setnl", "setge").Case("setnle", "setg")
660 .Case("setpe", "setp") .Case("setpo", "setnp")
661 .Case("jz", "je") .Case("jnz", "jne")
662 .Case("jc", "jb") .Case("jna", "jbe")
663 .Case("jnae", "jb").Case("jnb", "jae")
664 .Case("jnbe", "ja").Case("jnc", "jae")
665 .Case("jng", "jle").Case("jnge", "jl")
666 .Case("jnl", "jge").Case("jnle", "jg")
667 .Case("jpe", "jp") .Case("jpo", "jnp")
668 // Condition code aliases for 16-bit, 32-bit, 64-bit and unspec operands.
669 .Case("cmovcw", "cmovbw") .Case("cmovcl", "cmovbl")
670 .Case("cmovcq", "cmovbq") .Case("cmovc", "cmovb")
671 .Case("cmovnaew","cmovbw") .Case("cmovnael","cmovbl")
672 .Case("cmovnaeq","cmovbq") .Case("cmovnae", "cmovb")
673 .Case("cmovnaw", "cmovbew").Case("cmovnal", "cmovbel")
674 .Case("cmovnaq", "cmovbeq").Case("cmovna", "cmovbe")
675 .Case("cmovnbw", "cmovaew").Case("cmovnbl", "cmovael")
676 .Case("cmovnbq", "cmovaeq").Case("cmovnb", "cmovae")
677 .Case("cmovnbew","cmovaw") .Case("cmovnbel","cmoval")
678 .Case("cmovnbeq","cmovaq") .Case("cmovnbe", "cmova")
679 .Case("cmovncw", "cmovaew").Case("cmovncl", "cmovael")
680 .Case("cmovncq", "cmovaeq").Case("cmovnc", "cmovae")
681 .Case("cmovngw", "cmovlew").Case("cmovngl", "cmovlel")
682 .Case("cmovngq", "cmovleq").Case("cmovng", "cmovle")
683 .Case("cmovnw", "cmovgew").Case("cmovnl", "cmovgel")
684 .Case("cmovnq", "cmovgeq").Case("cmovn", "cmovge")
685 .Case("cmovngw", "cmovlew").Case("cmovngl", "cmovlel")
686 .Case("cmovngq", "cmovleq").Case("cmovng", "cmovle")
687 .Case("cmovngew","cmovlw") .Case("cmovngel","cmovll")
688 .Case("cmovngeq","cmovlq") .Case("cmovnge", "cmovl")
689 .Case("cmovnlw", "cmovgew").Case("cmovnll", "cmovgel")
690 .Case("cmovnlq", "cmovgeq").Case("cmovnl", "cmovge")
691 .Case("cmovnlew","cmovgw") .Case("cmovnlel","cmovgl")
692 .Case("cmovnleq","cmovgq") .Case("cmovnle", "cmovg")
693 .Case("cmovnzw", "cmovnew").Case("cmovnzl", "cmovnel")
694 .Case("cmovnzq", "cmovneq").Case("cmovnz", "cmovne")
695 .Case("cmovzw", "cmovew") .Case("cmovzl", "cmovel")
696 .Case("cmovzq", "cmoveq") .Case("cmovz", "cmove")
697 // Floating point stack cmov aliases.
698 .Case("fcmovz", "fcmove")
699 .Case("fcmova", "fcmovnbe")
700 .Case("fcmovnae", "fcmovb")
701 .Case("fcmovna", "fcmovbe")
702 .Case("fcmovae", "fcmovnb")
703 .Case("fwait", "wait")
704 .Case("movzx", "movzb") // FIXME: Not correct.
705 .Case("fildq", "fildll")
709 // FIXME: Hack to recognize cmp<comparison code>{ss,sd,ps,pd}.
710 const MCExpr *ExtraImmOp = 0;
711 if ((PatchedName.startswith("cmp") || PatchedName.startswith("vcmp")) &&
712 (PatchedName.endswith("ss") || PatchedName.endswith("sd") ||
713 PatchedName.endswith("ps") || PatchedName.endswith("pd"))) {
714 bool IsVCMP = PatchedName.startswith("vcmp");
715 unsigned SSECCIdx = IsVCMP ? 4 : 3;
716 unsigned SSEComparisonCode = StringSwitch<unsigned>(
717 PatchedName.slice(SSECCIdx, PatchedName.size() - 2))
730 .Case("neq_oq", 0x0C)
737 .Case("unord_s", 0x13)
738 .Case("neq_us", 0x14)
739 .Case("nlt_uq", 0x15)
740 .Case("nle_uq", 0x16)
743 .Case("nge_uq", 0x19)
744 .Case("ngt_uq", 0x1A)
745 .Case("false_os", 0x1B)
746 .Case("neq_os", 0x1C)
749 .Case("true_us", 0x1F)
751 if (SSEComparisonCode != ~0U) {
752 ExtraImmOp = MCConstantExpr::Create(SSEComparisonCode,
753 getParser().getContext());
754 if (PatchedName.endswith("ss")) {
755 PatchedName = IsVCMP ? "vcmpss" : "cmpss";
756 } else if (PatchedName.endswith("sd")) {
757 PatchedName = IsVCMP ? "vcmpsd" : "cmpsd";
758 } else if (PatchedName.endswith("ps")) {
759 PatchedName = IsVCMP ? "vcmpps" : "cmpps";
761 assert(PatchedName.endswith("pd") && "Unexpected mnemonic!");
762 PatchedName = IsVCMP ? "vcmppd" : "cmppd";
767 // FIXME: Hack to recognize vpclmul<src1_quadword, src2_quadword>dq
768 if (PatchedName.startswith("vpclmul")) {
769 unsigned CLMULQuadWordSelect = StringSwitch<unsigned>(
770 PatchedName.slice(7, PatchedName.size() - 2))
771 .Case("lqlq", 0x00) // src1[63:0], src2[63:0]
772 .Case("hqlq", 0x01) // src1[127:64], src2[63:0]
773 .Case("lqhq", 0x10) // src1[63:0], src2[127:64]
774 .Case("hqhq", 0x11) // src1[127:64], src2[127:64]
776 if (CLMULQuadWordSelect != ~0U) {
777 ExtraImmOp = MCConstantExpr::Create(CLMULQuadWordSelect,
778 getParser().getContext());
779 assert(PatchedName.endswith("dq") && "Unexpected mnemonic!");
780 PatchedName = "vpclmulqdq";
784 Operands.push_back(X86Operand::CreateToken(PatchedName, NameLoc));
787 Operands.push_back(X86Operand::CreateImm(ExtraImmOp, NameLoc, NameLoc));
790 // Determine whether this is an instruction prefix.
792 PatchedName == "lock" || PatchedName == "rep" ||
793 PatchedName == "repne";
796 // This does the actual operand parsing. Don't parse any more if we have a
797 // prefix juxtaposed with an operation like "lock incl 4(%rax)", because we
798 // just want to parse the "lock" as the first instruction and the "incl" as
800 if (getLexer().isNot(AsmToken::EndOfStatement) && !isPrefix) {
802 // Parse '*' modifier.
803 if (getLexer().is(AsmToken::Star)) {
804 SMLoc Loc = Parser.getTok().getLoc();
805 Operands.push_back(X86Operand::CreateToken("*", Loc));
806 Parser.Lex(); // Eat the star.
809 // Read the first operand.
810 if (X86Operand *Op = ParseOperand())
811 Operands.push_back(Op);
813 Parser.EatToEndOfStatement();
817 while (getLexer().is(AsmToken::Comma)) {
818 Parser.Lex(); // Eat the comma.
820 // Parse and remember the operand.
821 if (X86Operand *Op = ParseOperand())
822 Operands.push_back(Op);
824 Parser.EatToEndOfStatement();
829 if (getLexer().isNot(AsmToken::EndOfStatement)) {
830 Parser.EatToEndOfStatement();
831 return TokError("unexpected token in argument list");
835 if (getLexer().is(AsmToken::EndOfStatement))
836 Parser.Lex(); // Consume the EndOfStatement
838 // Hack to allow 'movq <largeimm>, <reg>' as an alias for movabsq.
839 if ((Name == "movq" || Name == "mov") && Operands.size() == 3 &&
840 static_cast<X86Operand*>(Operands[2])->isReg() &&
841 static_cast<X86Operand*>(Operands[1])->isImm() &&
842 !static_cast<X86Operand*>(Operands[1])->isImmSExti64i32()) {
844 Operands[0] = X86Operand::CreateToken("movabsq", NameLoc);
847 // FIXME: Hack to handle recognize s{hr,ar,hl} $1, <op>. Canonicalize to
849 if ((Name.startswith("shr") || Name.startswith("sar") ||
850 Name.startswith("shl")) &&
851 Operands.size() == 3) {
852 X86Operand *Op1 = static_cast<X86Operand*>(Operands[1]);
853 if (Op1->isImm() && isa<MCConstantExpr>(Op1->getImm()) &&
854 cast<MCConstantExpr>(Op1->getImm())->getValue() == 1) {
856 Operands.erase(Operands.begin() + 1);
860 // FIXME: Hack to handle recognize "rc[lr] <op>" -> "rcl $1, <op>".
861 if ((Name.startswith("rcl") || Name.startswith("rcr")) &&
862 Operands.size() == 2) {
863 const MCExpr *One = MCConstantExpr::Create(1, getParser().getContext());
864 Operands.push_back(X86Operand::CreateImm(One, NameLoc, NameLoc));
865 std::swap(Operands[1], Operands[2]);
868 // FIXME: Hack to handle recognize "sh[lr]d op,op" -> "shld $1, op,op".
869 if ((Name.startswith("shld") || Name.startswith("shrd")) &&
870 Operands.size() == 3) {
871 const MCExpr *One = MCConstantExpr::Create(1, getParser().getContext());
872 Operands.insert(Operands.begin()+1,
873 X86Operand::CreateImm(One, NameLoc, NameLoc));
877 // FIXME: Hack to handle recognize "in[bwl] <op>". Canonicalize it to
879 if ((Name == "inb" || Name == "inw" || Name == "inl") &&
880 Operands.size() == 2) {
883 Reg = MatchRegisterName("al");
884 else if (Name[2] == 'w')
885 Reg = MatchRegisterName("ax");
887 Reg = MatchRegisterName("eax");
888 SMLoc Loc = Operands.back()->getEndLoc();
889 Operands.push_back(X86Operand::CreateReg(Reg, Loc, Loc));
892 // FIXME: Hack to handle recognize "out[bwl] <op>". Canonicalize it to
894 if ((Name == "outb" || Name == "outw" || Name == "outl") &&
895 Operands.size() == 2) {
898 Reg = MatchRegisterName("al");
899 else if (Name[3] == 'w')
900 Reg = MatchRegisterName("ax");
902 Reg = MatchRegisterName("eax");
903 SMLoc Loc = Operands.back()->getEndLoc();
904 Operands.push_back(X86Operand::CreateReg(Reg, Loc, Loc));
905 std::swap(Operands[1], Operands[2]);
908 // FIXME: Hack to handle "out[bwl]? %al, (%dx)" -> "outb %al, %dx".
909 if ((Name == "outb" || Name == "outw" || Name == "outl" || Name == "out") &&
910 Operands.size() == 3) {
911 X86Operand &Op = *(X86Operand*)Operands.back();
912 if (Op.isMem() && Op.Mem.SegReg == 0 &&
913 isa<MCConstantExpr>(Op.Mem.Disp) &&
914 cast<MCConstantExpr>(Op.Mem.Disp)->getValue() == 0 &&
915 Op.Mem.BaseReg == MatchRegisterName("dx") && Op.Mem.IndexReg == 0) {
916 SMLoc Loc = Op.getEndLoc();
917 Operands.back() = X86Operand::CreateReg(Op.Mem.BaseReg, Loc, Loc);
922 // FIXME: Hack to handle "f{mul*,add*,sub*,div*} $op, st(0)" the same as
923 // "f{mul*,add*,sub*,div*} $op"
924 if ((Name.startswith("fmul") || Name.startswith("fadd") ||
925 Name.startswith("fsub") || Name.startswith("fdiv")) &&
926 Operands.size() == 3 &&
927 static_cast<X86Operand*>(Operands[2])->isReg() &&
928 static_cast<X86Operand*>(Operands[2])->getReg() == X86::ST0) {
930 Operands.erase(Operands.begin() + 2);
933 // FIXME: Hack to handle "f{mulp,addp} st(0), $op" the same as
934 // "f{mulp,addp} $op", since they commute. We also allow fdivrp/fsubrp even
935 // though they don't commute, solely because gas does support this.
936 if ((Name=="fmulp" || Name=="faddp" || Name=="fsubrp" || Name=="fdivrp") &&
937 Operands.size() == 3 &&
938 static_cast<X86Operand*>(Operands[1])->isReg() &&
939 static_cast<X86Operand*>(Operands[1])->getReg() == X86::ST0) {
941 Operands.erase(Operands.begin() + 1);
944 // FIXME: Hack to handle "imul <imm>, B" which is an alias for "imul <imm>, B,
946 if (Name.startswith("imul") && Operands.size() == 3 &&
947 static_cast<X86Operand*>(Operands[1])->isImm() &&
948 static_cast<X86Operand*>(Operands.back())->isReg()) {
949 X86Operand *Op = static_cast<X86Operand*>(Operands.back());
950 Operands.push_back(X86Operand::CreateReg(Op->getReg(), Op->getStartLoc(),
954 // 'sldt <mem>' can be encoded with either sldtw or sldtq with the same
955 // effect (both store to a 16-bit mem). Force to sldtw to avoid ambiguity
956 // errors, since its encoding is the most compact.
957 if (Name == "sldt" && Operands.size() == 2 &&
958 static_cast<X86Operand*>(Operands[1])->isMem()) {
960 Operands[0] = X86Operand::CreateToken("sldtw", NameLoc);
963 // The assembler accepts "xchgX <reg>, <mem>" and "xchgX <mem>, <reg>" as
964 // synonyms. Our tables only have the "<reg>, <mem>" form, so if we see the
965 // other operand order, swap them.
966 if (Name == "xchgb" || Name == "xchgw" || Name == "xchgl" || Name == "xchgq"||
968 if (Operands.size() == 3 &&
969 static_cast<X86Operand*>(Operands[1])->isMem() &&
970 static_cast<X86Operand*>(Operands[2])->isReg()) {
971 std::swap(Operands[1], Operands[2]);
974 // The assembler accepts "testX <reg>, <mem>" and "testX <mem>, <reg>" as
975 // synonyms. Our tables only have the "<mem>, <reg>" form, so if we see the
976 // other operand order, swap them.
977 if (Name == "testb" || Name == "testw" || Name == "testl" || Name == "testq"||
979 if (Operands.size() == 3 &&
980 static_cast<X86Operand*>(Operands[1])->isReg() &&
981 static_cast<X86Operand*>(Operands[2])->isMem()) {
982 std::swap(Operands[1], Operands[2]);
985 // The assembler accepts these instructions with no operand as a synonym for
986 // an instruction acting on st(1). e.g. "fxch" -> "fxch %st(1)".
987 if ((Name == "fxch" || Name == "fucom" || Name == "fucomp" ||
988 Name == "faddp" || Name == "fsubp" || Name == "fsubrp" ||
989 Name == "fmulp" || Name == "fdivp" || Name == "fdivrp") &&
990 Operands.size() == 1) {
991 Operands.push_back(X86Operand::CreateReg(MatchRegisterName("st(1)"),
995 // The assembler accepts these instructions with two few operands as a synonym
996 // for taking %st(1),%st(0) or X, %st(0).
997 if ((Name == "fcomi" || Name == "fucomi") && Operands.size() < 3) {
998 if (Operands.size() == 1)
999 Operands.push_back(X86Operand::CreateReg(MatchRegisterName("st(1)"),
1001 Operands.push_back(X86Operand::CreateReg(MatchRegisterName("st(0)"),
1005 // The assembler accepts various amounts of brokenness for fnstsw.
1006 if (Name == "fnstsw") {
1007 if (Operands.size() == 2 &&
1008 static_cast<X86Operand*>(Operands[1])->isReg()) {
1009 // "fnstsw al" and "fnstsw eax" -> "fnstw"
1010 unsigned Reg = static_cast<X86Operand*>(Operands[1])->Reg.RegNo;
1011 if (Reg == MatchRegisterName("eax") ||
1012 Reg == MatchRegisterName("al")) {
1014 Operands.pop_back();
1018 // "fnstw" -> "fnstw %ax"
1019 if (Operands.size() == 1)
1020 Operands.push_back(X86Operand::CreateReg(MatchRegisterName("ax"),
1024 // jmp $42,$5 -> ljmp, similarly for call.
1025 if ((Name.startswith("call") || Name.startswith("jmp")) &&
1026 Operands.size() == 3 &&
1027 static_cast<X86Operand*>(Operands[1])->isImm() &&
1028 static_cast<X86Operand*>(Operands[2])->isImm()) {
1029 const char *NewOpName = StringSwitch<const char *>(Name)
1030 .Case("jmp", "ljmp")
1031 .Case("jmpw", "ljmpw")
1032 .Case("jmpl", "ljmpl")
1033 .Case("jmpq", "ljmpq")
1034 .Case("call", "lcall")
1035 .Case("callw", "lcallw")
1036 .Case("calll", "lcalll")
1037 .Case("callq", "lcallq")
1041 Operands[0] = X86Operand::CreateToken(NewOpName, NameLoc);
1046 // lcall and ljmp -> lcalll and ljmpl
1047 if ((Name == "lcall" || Name == "ljmp") && Operands.size() == 3) {
1049 Operands[0] = X86Operand::CreateToken(Name == "lcall" ? "lcalll" : "ljmpl",
1053 // call foo is not ambiguous with callw.
1054 if (Name == "call" && Operands.size() == 2) {
1055 const char *NewName = Is64Bit ? "callq" : "calll";
1057 Operands[0] = X86Operand::CreateToken(NewName, NameLoc);
1061 // movsd -> movsl (when no operands are specified).
1062 if (Name == "movsd" && Operands.size() == 1) {
1064 Operands[0] = X86Operand::CreateToken("movsl", NameLoc);
1067 // fstp <mem> -> fstps <mem>. Without this, we'll default to fstpl due to
1068 // suffix searching.
1069 if (Name == "fstp" && Operands.size() == 2 &&
1070 static_cast<X86Operand*>(Operands[1])->isMem()) {
1072 Operands[0] = X86Operand::CreateToken("fstps", NameLoc);
1076 // "clr <reg>" -> "xor <reg>, <reg>".
1077 if ((Name == "clrb" || Name == "clrw" || Name == "clrl" || Name == "clrq" ||
1078 Name == "clr") && Operands.size() == 2 &&
1079 static_cast<X86Operand*>(Operands[1])->isReg()) {
1080 unsigned RegNo = static_cast<X86Operand*>(Operands[1])->getReg();
1081 Operands.push_back(X86Operand::CreateReg(RegNo, NameLoc, NameLoc));
1083 Operands[0] = X86Operand::CreateToken("xor", NameLoc);
1086 // FIXME: Hack to handle recognize "aa[dm]" -> "aa[dm] $0xA".
1087 if ((Name.startswith("aad") || Name.startswith("aam")) &&
1088 Operands.size() == 1) {
1089 const MCExpr *A = MCConstantExpr::Create(0xA, getParser().getContext());
1090 Operands.push_back(X86Operand::CreateImm(A, NameLoc, NameLoc));
1093 // "lgdtl" is not ambiguous 32-bit mode and is the same as "lgdt".
1094 // "lgdtq" is not ambiguous 64-bit mode and is the same as "lgdt".
1095 if ((Name == "lgdtl" && Is64Bit == false) ||
1096 (Name == "lgdtq" && Is64Bit == true)) {
1097 const char *NewName = "lgdt";
1099 Operands[0] = X86Operand::CreateToken(NewName, NameLoc);
1103 // "lidtl" is not ambiguous 32-bit mode and is the same as "lidt".
1104 // "lidtq" is not ambiguous 64-bit mode and is the same as "lidt".
1105 if ((Name == "lidtl" && Is64Bit == false) ||
1106 (Name == "lidtq" && Is64Bit == true)) {
1107 const char *NewName = "lidt";
1109 Operands[0] = X86Operand::CreateToken(NewName, NameLoc);
1113 // "sgdtl" is not ambiguous 32-bit mode and is the same as "sgdt".
1114 // "sgdtq" is not ambiguous 64-bit mode and is the same as "sgdt".
1115 if ((Name == "sgdtl" && Is64Bit == false) ||
1116 (Name == "sgdtq" && Is64Bit == true)) {
1117 const char *NewName = "sgdt";
1119 Operands[0] = X86Operand::CreateToken(NewName, NameLoc);
1123 // "sidtl" is not ambiguous 32-bit mode and is the same as "sidt".
1124 // "sidtq" is not ambiguous 64-bit mode and is the same as "sidt".
1125 if ((Name == "sidtl" && Is64Bit == false) ||
1126 (Name == "sidtq" && Is64Bit == true)) {
1127 const char *NewName = "sidt";
1129 Operands[0] = X86Operand::CreateToken(NewName, NameLoc);
1136 bool X86ATTAsmParser::ParseDirective(AsmToken DirectiveID) {
1137 StringRef IDVal = DirectiveID.getIdentifier();
1138 if (IDVal == ".word")
1139 return ParseDirectiveWord(2, DirectiveID.getLoc());
1143 /// ParseDirectiveWord
1144 /// ::= .word [ expression (, expression)* ]
1145 bool X86ATTAsmParser::ParseDirectiveWord(unsigned Size, SMLoc L) {
1146 if (getLexer().isNot(AsmToken::EndOfStatement)) {
1148 const MCExpr *Value;
1149 if (getParser().ParseExpression(Value))
1152 getParser().getStreamer().EmitValue(Value, Size, 0 /*addrspace*/);
1154 if (getLexer().is(AsmToken::EndOfStatement))
1157 // FIXME: Improve diagnostic.
1158 if (getLexer().isNot(AsmToken::Comma))
1159 return Error(L, "unexpected token in directive");
1169 bool X86ATTAsmParser::
1170 MatchAndEmitInstruction(SMLoc IDLoc,
1171 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
1173 assert(!Operands.empty() && "Unexpect empty operand list!");
1174 X86Operand *Op = static_cast<X86Operand*>(Operands[0]);
1175 assert(Op->isToken() && "Leading operand should always be a mnemonic!");
1177 // First, handle aliases that expand to multiple instructions.
1178 // FIXME: This should be replaced with a real .td file alias mechanism.
1179 if (Op->getToken() == "fstsw" || Op->getToken() == "fstsww" ||
1180 Op->getToken() == "fstcw" || Op->getToken() == "fstcww" ||
1181 Op->getToken() == "finit" || Op->getToken() == "fsave" ||
1182 Op->getToken() == "fstenv" || Op->getToken() == "fclex") {
1184 Inst.setOpcode(X86::WAIT);
1185 Out.EmitInstruction(Inst);
1188 StringSwitch<const char*>(Op->getToken())
1189 .Case("finit", "fninit")
1190 .Case("fsave", "fnsave")
1191 .Case("fstcw", "fnstcw")
1192 .Case("fstcww", "fnstcw")
1193 .Case("fstenv", "fnstenv")
1194 .Case("fstsw", "fnstsw")
1195 .Case("fstsww", "fnstsw")
1196 .Case("fclex", "fnclex")
1198 assert(Repl && "Unknown wait-prefixed instruction");
1200 Operands[0] = X86Operand::CreateToken(Repl, IDLoc);
1203 bool WasOriginallyInvalidOperand = false;
1204 unsigned OrigErrorInfo;
1207 // First, try a direct match.
1208 switch (MatchInstructionImpl(Operands, Inst, OrigErrorInfo)) {
1210 Out.EmitInstruction(Inst);
1212 case Match_MissingFeature:
1213 Error(IDLoc, "instruction requires a CPU feature not currently enabled");
1215 case Match_InvalidOperand:
1216 WasOriginallyInvalidOperand = true;
1218 case Match_MnemonicFail:
1222 // FIXME: Ideally, we would only attempt suffix matches for things which are
1223 // valid prefixes, and we could just infer the right unambiguous
1224 // type. However, that requires substantially more matcher support than the
1227 // Change the operand to point to a temporary token.
1228 StringRef Base = Op->getToken();
1229 SmallString<16> Tmp;
1232 Op->setTokenValue(Tmp.str());
1234 // Check for the various suffix matches.
1235 Tmp[Base.size()] = 'b';
1236 unsigned BErrorInfo, WErrorInfo, LErrorInfo, QErrorInfo;
1237 MatchResultTy MatchB = MatchInstructionImpl(Operands, Inst, BErrorInfo);
1238 Tmp[Base.size()] = 'w';
1239 MatchResultTy MatchW = MatchInstructionImpl(Operands, Inst, WErrorInfo);
1240 Tmp[Base.size()] = 'l';
1241 MatchResultTy MatchL = MatchInstructionImpl(Operands, Inst, LErrorInfo);
1242 Tmp[Base.size()] = 'q';
1243 MatchResultTy MatchQ = MatchInstructionImpl(Operands, Inst, QErrorInfo);
1245 // Restore the old token.
1246 Op->setTokenValue(Base);
1248 // If exactly one matched, then we treat that as a successful match (and the
1249 // instruction will already have been filled in correctly, since the failing
1250 // matches won't have modified it).
1251 unsigned NumSuccessfulMatches =
1252 (MatchB == Match_Success) + (MatchW == Match_Success) +
1253 (MatchL == Match_Success) + (MatchQ == Match_Success);
1254 if (NumSuccessfulMatches == 1) {
1255 Out.EmitInstruction(Inst);
1259 // Otherwise, the match failed, try to produce a decent error message.
1261 // If we had multiple suffix matches, then identify this as an ambiguous
1263 if (NumSuccessfulMatches > 1) {
1265 unsigned NumMatches = 0;
1266 if (MatchB == Match_Success)
1267 MatchChars[NumMatches++] = 'b';
1268 if (MatchW == Match_Success)
1269 MatchChars[NumMatches++] = 'w';
1270 if (MatchL == Match_Success)
1271 MatchChars[NumMatches++] = 'l';
1272 if (MatchQ == Match_Success)
1273 MatchChars[NumMatches++] = 'q';
1275 SmallString<126> Msg;
1276 raw_svector_ostream OS(Msg);
1277 OS << "ambiguous instructions require an explicit suffix (could be ";
1278 for (unsigned i = 0; i != NumMatches; ++i) {
1281 if (i + 1 == NumMatches)
1283 OS << "'" << Base << MatchChars[i] << "'";
1286 Error(IDLoc, OS.str());
1290 // Okay, we know that none of the variants matched successfully.
1292 // If all of the instructions reported an invalid mnemonic, then the original
1293 // mnemonic was invalid.
1294 if ((MatchB == Match_MnemonicFail) && (MatchW == Match_MnemonicFail) &&
1295 (MatchL == Match_MnemonicFail) && (MatchQ == Match_MnemonicFail)) {
1296 if (!WasOriginallyInvalidOperand) {
1297 Error(IDLoc, "invalid instruction mnemonic '" + Base + "'");
1301 // Recover location info for the operand if we know which was the problem.
1302 SMLoc ErrorLoc = IDLoc;
1303 if (OrigErrorInfo != ~0U) {
1304 if (OrigErrorInfo >= Operands.size())
1305 return Error(IDLoc, "too few operands for instruction");
1307 ErrorLoc = ((X86Operand*)Operands[OrigErrorInfo])->getStartLoc();
1308 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
1311 return Error(ErrorLoc, "invalid operand for instruction");
1314 // If one instruction matched with a missing feature, report this as a
1316 if ((MatchB == Match_MissingFeature) + (MatchW == Match_MissingFeature) +
1317 (MatchL == Match_MissingFeature) + (MatchQ == Match_MissingFeature) == 1){
1318 Error(IDLoc, "instruction requires a CPU feature not currently enabled");
1322 // If one instruction matched with an invalid operand, report this as an
1324 if ((MatchB == Match_InvalidOperand) + (MatchW == Match_InvalidOperand) +
1325 (MatchL == Match_InvalidOperand) + (MatchQ == Match_InvalidOperand) == 1){
1326 Error(IDLoc, "invalid operand for instruction");
1330 // If all of these were an outright failure, report it in a useless way.
1331 // FIXME: We should give nicer diagnostics about the exact failure.
1332 Error(IDLoc, "unknown use of instruction mnemonic without a size suffix");
1337 extern "C" void LLVMInitializeX86AsmLexer();
1339 // Force static initialization.
1340 extern "C" void LLVMInitializeX86AsmParser() {
1341 RegisterAsmParser<X86_32ATTAsmParser> X(TheX86_32Target);
1342 RegisterAsmParser<X86_64ATTAsmParser> Y(TheX86_64Target);
1343 LLVMInitializeX86AsmLexer();
1346 #define GET_REGISTER_MATCHER
1347 #define GET_MATCHER_IMPLEMENTATION
1348 #include "X86GenAsmMatcher.inc"