1 //===-- X86AsmParser.cpp - Parse X86 assembly to MCInst instructions ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "llvm/Target/TargetAsmParser.h"
12 #include "llvm/ADT/SmallVector.h"
13 #include "llvm/ADT/Twine.h"
14 #include "llvm/MC/MCAsmLexer.h"
15 #include "llvm/MC/MCAsmParser.h"
16 #include "llvm/MC/MCStreamer.h"
17 #include "llvm/MC/MCExpr.h"
18 #include "llvm/MC/MCInst.h"
19 #include "llvm/MC/MCParsedAsmOperand.h"
20 #include "llvm/Support/SourceMgr.h"
21 #include "llvm/Target/TargetRegistry.h"
22 #include "llvm/Target/TargetAsmParser.h"
28 class X86ATTAsmParser : public TargetAsmParser {
32 MCAsmParser &getParser() const { return Parser; }
34 MCAsmLexer &getLexer() const { return Parser.getLexer(); }
36 void Warning(SMLoc L, const Twine &Msg) { Parser.Warning(L, Msg); }
38 bool Error(SMLoc L, const Twine &Msg) { return Parser.Error(L, Msg); }
40 bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc);
42 X86Operand *ParseOperand();
43 X86Operand *ParseMemOperand();
45 bool ParseDirectiveWord(unsigned Size, SMLoc L);
47 /// @name Auto-generated Match Functions
50 bool MatchInstruction(const SmallVectorImpl<MCParsedAsmOperand*> &Operands,
53 /// MatchRegisterName - Match the given string to a register name, or 0 if
54 /// there is no match.
55 unsigned MatchRegisterName(const StringRef &Name);
60 X86ATTAsmParser(const Target &T, MCAsmParser &_Parser)
61 : TargetAsmParser(T), Parser(_Parser) {}
63 virtual bool ParseInstruction(const StringRef &Name, SMLoc NameLoc,
64 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
66 virtual bool ParseDirective(AsmToken DirectiveID);
69 } // end anonymous namespace
74 /// X86Operand - Instances of this class represent a parsed X86 machine
76 struct X86Operand : public MCParsedAsmOperand {
84 SMLoc StartLoc, EndLoc;
109 X86Operand(KindTy K, SMLoc Start = SMLoc(), SMLoc End = SMLoc())
110 : Kind(K), StartLoc(Start), EndLoc(End) {}
112 /// getStartLoc - Get the location of the first token of this operand.
113 SMLoc getStartLoc() const { return StartLoc; }
114 /// getEndLoc - Get the location of the last token of this operand.
115 SMLoc getEndLoc() const { return EndLoc; }
117 StringRef getToken() const {
118 assert(Kind == Token && "Invalid access!");
119 return StringRef(Tok.Data, Tok.Length);
122 unsigned getReg() const {
123 assert(Kind == Register && "Invalid access!");
127 const MCExpr *getImm() const {
128 assert(Kind == Immediate && "Invalid access!");
132 const MCExpr *getMemDisp() const {
133 assert(Kind == Memory && "Invalid access!");
136 unsigned getMemSegReg() const {
137 assert(Kind == Memory && "Invalid access!");
140 unsigned getMemBaseReg() const {
141 assert(Kind == Memory && "Invalid access!");
144 unsigned getMemIndexReg() const {
145 assert(Kind == Memory && "Invalid access!");
148 unsigned getMemScale() const {
149 assert(Kind == Memory && "Invalid access!");
153 bool isToken() const {return Kind == Token; }
155 bool isImm() const { return Kind == Immediate; }
157 bool isImmSExt8() const {
158 // Accept immediates which fit in 8 bits when sign extended, and
159 // non-absolute immediates.
163 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm())) {
164 int64_t Value = CE->getValue();
165 return Value == (int64_t) (int8_t) Value;
171 bool isMem() const { return Kind == Memory; }
173 bool isReg() const { return Kind == Register; }
175 void addRegOperands(MCInst &Inst, unsigned N) const {
176 assert(N == 1 && "Invalid number of operands!");
177 Inst.addOperand(MCOperand::CreateReg(getReg()));
180 void addImmOperands(MCInst &Inst, unsigned N) const {
181 assert(N == 1 && "Invalid number of operands!");
182 Inst.addOperand(MCOperand::CreateExpr(getImm()));
185 void addImmSExt8Operands(MCInst &Inst, unsigned N) const {
186 // FIXME: Support user customization of the render method.
187 assert(N == 1 && "Invalid number of operands!");
188 Inst.addOperand(MCOperand::CreateExpr(getImm()));
191 void addMemOperands(MCInst &Inst, unsigned N) const {
192 assert((N == 4 || N == 5) && "Invalid number of operands!");
194 Inst.addOperand(MCOperand::CreateReg(getMemBaseReg()));
195 Inst.addOperand(MCOperand::CreateImm(getMemScale()));
196 Inst.addOperand(MCOperand::CreateReg(getMemIndexReg()));
197 Inst.addOperand(MCOperand::CreateExpr(getMemDisp()));
199 // FIXME: What a hack.
201 Inst.addOperand(MCOperand::CreateReg(getMemSegReg()));
204 static X86Operand *CreateToken(StringRef Str) {
205 X86Operand *Res = new X86Operand(Token);
206 Res->Tok.Data = Str.data();
207 Res->Tok.Length = Str.size();
211 static X86Operand *CreateReg(unsigned RegNo, SMLoc StartLoc, SMLoc EndLoc) {
212 X86Operand *Res = new X86Operand(Register, StartLoc, EndLoc);
213 Res->Reg.RegNo = RegNo;
217 static X86Operand *CreateImm(const MCExpr *Val) {
218 X86Operand *Res = new X86Operand(Immediate);
223 static X86Operand *CreateMem(unsigned SegReg, const MCExpr *Disp,
224 unsigned BaseReg, unsigned IndexReg,
226 // We should never just have a displacement, that would be an immediate.
227 assert((SegReg || BaseReg || IndexReg) && "Invalid memory operand!");
229 // The scale should always be one of {1,2,4,8}.
230 assert(((Scale == 1 || Scale == 2 || Scale == 4 || Scale == 8)) &&
232 X86Operand *Res = new X86Operand(Memory);
233 Res->Mem.SegReg = SegReg;
234 Res->Mem.Disp = Disp;
235 Res->Mem.BaseReg = BaseReg;
236 Res->Mem.IndexReg = IndexReg;
237 Res->Mem.Scale = Scale;
242 } // end anonymous namespace.
245 bool X86ATTAsmParser::ParseRegister(unsigned &RegNo,
246 SMLoc &StartLoc, SMLoc &EndLoc) {
248 const AsmToken &TokPercent = getLexer().getTok();
249 assert(TokPercent.is(AsmToken::Percent) && "Invalid token kind!");
250 StartLoc = TokPercent.getLoc();
251 getLexer().Lex(); // Eat percent token.
253 const AsmToken &Tok = getLexer().getTok();
254 if (Tok.isNot(AsmToken::Identifier))
255 return Error(Tok.getLoc(), "invalid register name");
257 // FIXME: Validate register for the current architecture; we have to do
258 // validation later, so maybe there is no need for this here.
259 RegNo = MatchRegisterName(Tok.getString());
261 return Error(Tok.getLoc(), "invalid register name");
263 EndLoc = Tok.getLoc();
264 getLexer().Lex(); // Eat identifier token.
268 X86Operand *X86ATTAsmParser::ParseOperand() {
269 switch (getLexer().getKind()) {
271 return ParseMemOperand();
272 case AsmToken::Percent: {
273 // FIXME: if a segment register, this could either be just the seg reg, or
274 // the start of a memory operand.
277 if (ParseRegister(RegNo, Start, End)) return 0;
278 return X86Operand::CreateReg(RegNo, Start, End);
280 case AsmToken::Dollar: {
284 if (getParser().ParseExpression(Val))
286 return X86Operand::CreateImm(Val);
291 /// ParseMemOperand: segment: disp(basereg, indexreg, scale)
292 X86Operand *X86ATTAsmParser::ParseMemOperand() {
293 // FIXME: If SegReg ':' (e.g. %gs:), eat and remember.
296 // We have to disambiguate a parenthesized expression "(4+5)" from the start
297 // of a memory operand with a missing displacement "(%ebx)" or "(,%eax)". The
298 // only way to do this without lookahead is to eat the ( and see what is after
300 const MCExpr *Disp = MCConstantExpr::Create(0, getParser().getContext());
301 if (getLexer().isNot(AsmToken::LParen)) {
302 if (getParser().ParseExpression(Disp)) return 0;
304 // After parsing the base expression we could either have a parenthesized
305 // memory address or not. If not, return now. If so, eat the (.
306 if (getLexer().isNot(AsmToken::LParen)) {
307 // Unless we have a segment register, treat this as an immediate.
309 return X86Operand::CreateImm(Disp);
310 return X86Operand::CreateMem(SegReg, Disp, 0, 0, 1);
316 // Okay, we have a '('. We don't know if this is an expression or not, but
317 // so we have to eat the ( to see beyond it.
318 getLexer().Lex(); // Eat the '('.
320 if (getLexer().is(AsmToken::Percent) || getLexer().is(AsmToken::Comma)) {
321 // Nothing to do here, fall into the code below with the '(' part of the
322 // memory operand consumed.
324 // It must be an parenthesized expression, parse it now.
325 if (getParser().ParseParenExpression(Disp))
328 // After parsing the base expression we could either have a parenthesized
329 // memory address or not. If not, return now. If so, eat the (.
330 if (getLexer().isNot(AsmToken::LParen)) {
331 // Unless we have a segment register, treat this as an immediate.
333 return X86Operand::CreateImm(Disp);
334 return X86Operand::CreateMem(SegReg, Disp, 0, 0, 1);
342 // If we reached here, then we just ate the ( of the memory operand. Process
343 // the rest of the memory operand.
344 unsigned BaseReg = 0, IndexReg = 0, Scale = 1;
346 if (getLexer().is(AsmToken::Percent)) {
348 if (ParseRegister(BaseReg, L, L)) return 0;
351 if (getLexer().is(AsmToken::Comma)) {
352 getLexer().Lex(); // Eat the comma.
354 // Following the comma we should have either an index register, or a scale
355 // value. We don't support the later form, but we want to parse it
358 // Not that even though it would be completely consistent to support syntax
359 // like "1(%eax,,1)", the assembler doesn't.
360 if (getLexer().is(AsmToken::Percent)) {
362 if (ParseRegister(IndexReg, L, L)) return 0;
364 if (getLexer().isNot(AsmToken::RParen)) {
365 // Parse the scale amount:
366 // ::= ',' [scale-expression]
367 if (getLexer().isNot(AsmToken::Comma)) {
368 Error(getLexer().getTok().getLoc(),
369 "expected comma in scale expression");
372 getLexer().Lex(); // Eat the comma.
374 if (getLexer().isNot(AsmToken::RParen)) {
375 SMLoc Loc = getLexer().getTok().getLoc();
378 if (getParser().ParseAbsoluteExpression(ScaleVal))
381 // Validate the scale amount.
382 if (ScaleVal != 1 && ScaleVal != 2 && ScaleVal != 4 && ScaleVal != 8){
383 Error(Loc, "scale factor in address must be 1, 2, 4 or 8");
386 Scale = (unsigned)ScaleVal;
389 } else if (getLexer().isNot(AsmToken::RParen)) {
390 // Otherwise we have the unsupported form of a scale amount without an
392 SMLoc Loc = getLexer().getTok().getLoc();
395 if (getParser().ParseAbsoluteExpression(Value))
398 Error(Loc, "cannot have scale factor without index register");
403 // Ok, we've eaten the memory operand, verify we have a ')' and eat it too.
404 if (getLexer().isNot(AsmToken::RParen)) {
405 Error(getLexer().getTok().getLoc(), "unexpected token in memory operand");
408 getLexer().Lex(); // Eat the ')'.
410 return X86Operand::CreateMem(SegReg, Disp, BaseReg, IndexReg, Scale);
413 bool X86ATTAsmParser::
414 ParseInstruction(const StringRef &Name, SMLoc NameLoc,
415 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
417 Operands.push_back(X86Operand::CreateToken(Name));
419 SMLoc Loc = getLexer().getTok().getLoc();
420 if (getLexer().isNot(AsmToken::EndOfStatement)) {
422 // Parse '*' modifier.
423 if (getLexer().is(AsmToken::Star)) {
424 getLexer().Lex(); // Eat the star.
425 Operands.push_back(X86Operand::CreateToken("*"));
428 // Read the first operand.
429 if (X86Operand *Op = ParseOperand())
430 Operands.push_back(Op);
434 while (getLexer().is(AsmToken::Comma)) {
435 getLexer().Lex(); // Eat the comma.
437 // Parse and remember the operand.
438 if (X86Operand *Op = ParseOperand())
439 Operands.push_back(Op);
448 bool X86ATTAsmParser::ParseDirective(AsmToken DirectiveID) {
449 StringRef IDVal = DirectiveID.getIdentifier();
450 if (IDVal == ".word")
451 return ParseDirectiveWord(2, DirectiveID.getLoc());
455 /// ParseDirectiveWord
456 /// ::= .word [ expression (, expression)* ]
457 bool X86ATTAsmParser::ParseDirectiveWord(unsigned Size, SMLoc L) {
458 if (getLexer().isNot(AsmToken::EndOfStatement)) {
461 if (getParser().ParseExpression(Value))
464 getParser().getStreamer().EmitValue(Value, Size);
466 if (getLexer().is(AsmToken::EndOfStatement))
469 // FIXME: Improve diagnostic.
470 if (getLexer().isNot(AsmToken::Comma))
471 return Error(L, "unexpected token in directive");
480 // Force static initialization.
481 extern "C" void LLVMInitializeX86AsmParser() {
482 RegisterAsmParser<X86ATTAsmParser> X(TheX86_32Target);
483 RegisterAsmParser<X86ATTAsmParser> Y(TheX86_64Target);
486 #include "X86GenAsmMatcher.inc"