1 //===-- X86AsmParser.cpp - Parse X86 assembly to MCInst instructions ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "llvm/Target/TargetAsmParser.h"
12 #include "llvm/ADT/SmallVector.h"
13 #include "llvm/ADT/StringSwitch.h"
14 #include "llvm/ADT/Twine.h"
15 #include "llvm/MC/MCStreamer.h"
16 #include "llvm/MC/MCExpr.h"
17 #include "llvm/MC/MCInst.h"
18 #include "llvm/MC/MCParser/MCAsmLexer.h"
19 #include "llvm/MC/MCParser/MCAsmParser.h"
20 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
21 #include "llvm/Support/SourceMgr.h"
22 #include "llvm/Target/TargetRegistry.h"
23 #include "llvm/Target/TargetAsmParser.h"
29 class X86ATTAsmParser : public TargetAsmParser {
36 MCAsmParser &getParser() const { return Parser; }
38 MCAsmLexer &getLexer() const { return Parser.getLexer(); }
40 void Warning(SMLoc L, const Twine &Msg) { Parser.Warning(L, Msg); }
42 bool Error(SMLoc L, const Twine &Msg) { return Parser.Error(L, Msg); }
44 bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc);
46 X86Operand *ParseOperand();
47 X86Operand *ParseMemOperand(unsigned SegReg, SMLoc StartLoc);
49 bool ParseDirectiveWord(unsigned Size, SMLoc L);
51 void InstructionCleanup(MCInst &Inst);
53 /// @name Auto-generated Match Functions
56 bool MatchInstruction(const SmallVectorImpl<MCParsedAsmOperand*> &Operands,
59 bool MatchInstructionImpl(
60 const SmallVectorImpl<MCParsedAsmOperand*> &Operands, MCInst &Inst);
65 X86ATTAsmParser(const Target &T, MCAsmParser &_Parser)
66 : TargetAsmParser(T), Parser(_Parser) {}
68 virtual bool ParseInstruction(const StringRef &Name, SMLoc NameLoc,
69 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
71 virtual bool ParseDirective(AsmToken DirectiveID);
74 class X86_32ATTAsmParser : public X86ATTAsmParser {
76 X86_32ATTAsmParser(const Target &T, MCAsmParser &_Parser)
77 : X86ATTAsmParser(T, _Parser) {
82 class X86_64ATTAsmParser : public X86ATTAsmParser {
84 X86_64ATTAsmParser(const Target &T, MCAsmParser &_Parser)
85 : X86ATTAsmParser(T, _Parser) {
90 } // end anonymous namespace
92 /// @name Auto-generated Match Functions
95 static unsigned MatchRegisterName(StringRef Name);
101 /// X86Operand - Instances of this class represent a parsed X86 machine
103 struct X86Operand : public MCParsedAsmOperand {
111 SMLoc StartLoc, EndLoc;
136 X86Operand(KindTy K, SMLoc Start, SMLoc End)
137 : Kind(K), StartLoc(Start), EndLoc(End) {}
139 /// getStartLoc - Get the location of the first token of this operand.
140 SMLoc getStartLoc() const { return StartLoc; }
141 /// getEndLoc - Get the location of the last token of this operand.
142 SMLoc getEndLoc() const { return EndLoc; }
144 StringRef getToken() const {
145 assert(Kind == Token && "Invalid access!");
146 return StringRef(Tok.Data, Tok.Length);
148 void setTokenValue(StringRef Value) {
149 assert(Kind == Token && "Invalid access!");
150 Tok.Data = Value.data();
151 Tok.Length = Value.size();
154 unsigned getReg() const {
155 assert(Kind == Register && "Invalid access!");
159 const MCExpr *getImm() const {
160 assert(Kind == Immediate && "Invalid access!");
164 const MCExpr *getMemDisp() const {
165 assert(Kind == Memory && "Invalid access!");
168 unsigned getMemSegReg() const {
169 assert(Kind == Memory && "Invalid access!");
172 unsigned getMemBaseReg() const {
173 assert(Kind == Memory && "Invalid access!");
176 unsigned getMemIndexReg() const {
177 assert(Kind == Memory && "Invalid access!");
180 unsigned getMemScale() const {
181 assert(Kind == Memory && "Invalid access!");
185 bool isToken() const {return Kind == Token; }
187 bool isImm() const { return Kind == Immediate; }
189 bool isImmSExti16i8() const {
193 // If this isn't a constant expr, just assume it fits and let relaxation
195 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
199 // Otherwise, check the value is in a range that makes sense for this
201 uint64_t Value = CE->getValue();
202 return (( Value <= 0x000000000000007FULL)||
203 (0x000000000000FF80ULL <= Value && Value <= 0x000000000000FFFFULL)||
204 (0xFFFFFFFFFFFFFF80ULL <= Value && Value <= 0xFFFFFFFFFFFFFFFFULL));
206 bool isImmSExti32i8() const {
210 // If this isn't a constant expr, just assume it fits and let relaxation
212 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
216 // Otherwise, check the value is in a range that makes sense for this
218 uint64_t Value = CE->getValue();
219 return (( Value <= 0x000000000000007FULL)||
220 (0x00000000FFFFFF80ULL <= Value && Value <= 0x00000000FFFFFFFFULL)||
221 (0xFFFFFFFFFFFFFF80ULL <= Value && Value <= 0xFFFFFFFFFFFFFFFFULL));
223 bool isImmSExti64i8() const {
227 // If this isn't a constant expr, just assume it fits and let relaxation
229 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
233 // Otherwise, check the value is in a range that makes sense for this
235 uint64_t Value = CE->getValue();
236 return (( Value <= 0x000000000000007FULL)||
237 (0xFFFFFFFFFFFFFF80ULL <= Value && Value <= 0xFFFFFFFFFFFFFFFFULL));
239 bool isImmSExti64i32() const {
243 // If this isn't a constant expr, just assume it fits and let relaxation
245 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
249 // Otherwise, check the value is in a range that makes sense for this
251 uint64_t Value = CE->getValue();
252 return (( Value <= 0x000000007FFFFFFFULL)||
253 (0xFFFFFFFF80000000ULL <= Value && Value <= 0xFFFFFFFFFFFFFFFFULL));
256 bool isMem() const { return Kind == Memory; }
258 bool isAbsMem() const {
259 return Kind == Memory && !getMemSegReg() && !getMemBaseReg() &&
260 !getMemIndexReg() && getMemScale() == 1;
263 bool isNoSegMem() const {
264 return Kind == Memory && !getMemSegReg();
267 bool isReg() const { return Kind == Register; }
269 void addExpr(MCInst &Inst, const MCExpr *Expr) const {
270 // Add as immediates when possible.
271 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
272 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
274 Inst.addOperand(MCOperand::CreateExpr(Expr));
277 void addRegOperands(MCInst &Inst, unsigned N) const {
278 assert(N == 1 && "Invalid number of operands!");
279 Inst.addOperand(MCOperand::CreateReg(getReg()));
282 void addImmOperands(MCInst &Inst, unsigned N) const {
283 assert(N == 1 && "Invalid number of operands!");
284 addExpr(Inst, getImm());
287 void addMemOperands(MCInst &Inst, unsigned N) const {
288 assert((N == 5) && "Invalid number of operands!");
289 Inst.addOperand(MCOperand::CreateReg(getMemBaseReg()));
290 Inst.addOperand(MCOperand::CreateImm(getMemScale()));
291 Inst.addOperand(MCOperand::CreateReg(getMemIndexReg()));
292 addExpr(Inst, getMemDisp());
293 Inst.addOperand(MCOperand::CreateReg(getMemSegReg()));
296 void addAbsMemOperands(MCInst &Inst, unsigned N) const {
297 assert((N == 1) && "Invalid number of operands!");
298 Inst.addOperand(MCOperand::CreateExpr(getMemDisp()));
301 void addNoSegMemOperands(MCInst &Inst, unsigned N) const {
302 assert((N == 4) && "Invalid number of operands!");
303 Inst.addOperand(MCOperand::CreateReg(getMemBaseReg()));
304 Inst.addOperand(MCOperand::CreateImm(getMemScale()));
305 Inst.addOperand(MCOperand::CreateReg(getMemIndexReg()));
306 addExpr(Inst, getMemDisp());
309 static X86Operand *CreateToken(StringRef Str, SMLoc Loc) {
310 X86Operand *Res = new X86Operand(Token, Loc, Loc);
311 Res->Tok.Data = Str.data();
312 Res->Tok.Length = Str.size();
316 static X86Operand *CreateReg(unsigned RegNo, SMLoc StartLoc, SMLoc EndLoc) {
317 X86Operand *Res = new X86Operand(Register, StartLoc, EndLoc);
318 Res->Reg.RegNo = RegNo;
322 static X86Operand *CreateImm(const MCExpr *Val, SMLoc StartLoc, SMLoc EndLoc){
323 X86Operand *Res = new X86Operand(Immediate, StartLoc, EndLoc);
328 /// Create an absolute memory operand.
329 static X86Operand *CreateMem(const MCExpr *Disp, SMLoc StartLoc,
331 X86Operand *Res = new X86Operand(Memory, StartLoc, EndLoc);
333 Res->Mem.Disp = Disp;
334 Res->Mem.BaseReg = 0;
335 Res->Mem.IndexReg = 0;
340 /// Create a generalized memory operand.
341 static X86Operand *CreateMem(unsigned SegReg, const MCExpr *Disp,
342 unsigned BaseReg, unsigned IndexReg,
343 unsigned Scale, SMLoc StartLoc, SMLoc EndLoc) {
344 // We should never just have a displacement, that should be parsed as an
345 // absolute memory operand.
346 assert((SegReg || BaseReg || IndexReg) && "Invalid memory operand!");
348 // The scale should always be one of {1,2,4,8}.
349 assert(((Scale == 1 || Scale == 2 || Scale == 4 || Scale == 8)) &&
351 X86Operand *Res = new X86Operand(Memory, StartLoc, EndLoc);
352 Res->Mem.SegReg = SegReg;
353 Res->Mem.Disp = Disp;
354 Res->Mem.BaseReg = BaseReg;
355 Res->Mem.IndexReg = IndexReg;
356 Res->Mem.Scale = Scale;
361 } // end anonymous namespace.
364 bool X86ATTAsmParser::ParseRegister(unsigned &RegNo,
365 SMLoc &StartLoc, SMLoc &EndLoc) {
367 const AsmToken &TokPercent = Parser.getTok();
368 assert(TokPercent.is(AsmToken::Percent) && "Invalid token kind!");
369 StartLoc = TokPercent.getLoc();
370 Parser.Lex(); // Eat percent token.
372 const AsmToken &Tok = Parser.getTok();
373 if (Tok.isNot(AsmToken::Identifier))
374 return Error(Tok.getLoc(), "invalid register name");
376 // FIXME: Validate register for the current architecture; we have to do
377 // validation later, so maybe there is no need for this here.
378 RegNo = MatchRegisterName(Tok.getString());
380 // Parse %st(1) and "%st" as "%st(0)"
381 if (RegNo == 0 && Tok.getString() == "st") {
383 EndLoc = Tok.getLoc();
384 Parser.Lex(); // Eat 'st'
386 // Check to see if we have '(4)' after %st.
387 if (getLexer().isNot(AsmToken::LParen))
392 const AsmToken &IntTok = Parser.getTok();
393 if (IntTok.isNot(AsmToken::Integer))
394 return Error(IntTok.getLoc(), "expected stack index");
395 switch (IntTok.getIntVal()) {
396 case 0: RegNo = X86::ST0; break;
397 case 1: RegNo = X86::ST1; break;
398 case 2: RegNo = X86::ST2; break;
399 case 3: RegNo = X86::ST3; break;
400 case 4: RegNo = X86::ST4; break;
401 case 5: RegNo = X86::ST5; break;
402 case 6: RegNo = X86::ST6; break;
403 case 7: RegNo = X86::ST7; break;
404 default: return Error(IntTok.getLoc(), "invalid stack index");
407 if (getParser().Lex().isNot(AsmToken::RParen))
408 return Error(Parser.getTok().getLoc(), "expected ')'");
410 EndLoc = Tok.getLoc();
411 Parser.Lex(); // Eat ')'
416 return Error(Tok.getLoc(), "invalid register name");
418 EndLoc = Tok.getLoc();
419 Parser.Lex(); // Eat identifier token.
423 X86Operand *X86ATTAsmParser::ParseOperand() {
424 switch (getLexer().getKind()) {
426 // Parse a memory operand with no segment register.
427 return ParseMemOperand(0, Parser.getTok().getLoc());
428 case AsmToken::Percent: {
429 // Read the register.
432 if (ParseRegister(RegNo, Start, End)) return 0;
434 // If this is a segment register followed by a ':', then this is the start
435 // of a memory reference, otherwise this is a normal register reference.
436 if (getLexer().isNot(AsmToken::Colon))
437 return X86Operand::CreateReg(RegNo, Start, End);
440 getParser().Lex(); // Eat the colon.
441 return ParseMemOperand(RegNo, Start);
443 case AsmToken::Dollar: {
445 SMLoc Start = Parser.getTok().getLoc(), End;
448 if (getParser().ParseExpression(Val, End))
450 return X86Operand::CreateImm(Val, Start, End);
455 /// ParseMemOperand: segment: disp(basereg, indexreg, scale). The '%ds:' prefix
456 /// has already been parsed if present.
457 X86Operand *X86ATTAsmParser::ParseMemOperand(unsigned SegReg, SMLoc MemStart) {
459 // We have to disambiguate a parenthesized expression "(4+5)" from the start
460 // of a memory operand with a missing displacement "(%ebx)" or "(,%eax)". The
461 // only way to do this without lookahead is to eat the '(' and see what is
463 const MCExpr *Disp = MCConstantExpr::Create(0, getParser().getContext());
464 if (getLexer().isNot(AsmToken::LParen)) {
466 if (getParser().ParseExpression(Disp, ExprEnd)) return 0;
468 // After parsing the base expression we could either have a parenthesized
469 // memory address or not. If not, return now. If so, eat the (.
470 if (getLexer().isNot(AsmToken::LParen)) {
471 // Unless we have a segment register, treat this as an immediate.
473 return X86Operand::CreateMem(Disp, MemStart, ExprEnd);
474 return X86Operand::CreateMem(SegReg, Disp, 0, 0, 1, MemStart, ExprEnd);
480 // Okay, we have a '('. We don't know if this is an expression or not, but
481 // so we have to eat the ( to see beyond it.
482 SMLoc LParenLoc = Parser.getTok().getLoc();
483 Parser.Lex(); // Eat the '('.
485 if (getLexer().is(AsmToken::Percent) || getLexer().is(AsmToken::Comma)) {
486 // Nothing to do here, fall into the code below with the '(' part of the
487 // memory operand consumed.
491 // It must be an parenthesized expression, parse it now.
492 if (getParser().ParseParenExpression(Disp, ExprEnd))
495 // After parsing the base expression we could either have a parenthesized
496 // memory address or not. If not, return now. If so, eat the (.
497 if (getLexer().isNot(AsmToken::LParen)) {
498 // Unless we have a segment register, treat this as an immediate.
500 return X86Operand::CreateMem(Disp, LParenLoc, ExprEnd);
501 return X86Operand::CreateMem(SegReg, Disp, 0, 0, 1, MemStart, ExprEnd);
509 // If we reached here, then we just ate the ( of the memory operand. Process
510 // the rest of the memory operand.
511 unsigned BaseReg = 0, IndexReg = 0, Scale = 1;
513 if (getLexer().is(AsmToken::Percent)) {
515 if (ParseRegister(BaseReg, L, L)) return 0;
518 if (getLexer().is(AsmToken::Comma)) {
519 Parser.Lex(); // Eat the comma.
521 // Following the comma we should have either an index register, or a scale
522 // value. We don't support the later form, but we want to parse it
525 // Not that even though it would be completely consistent to support syntax
526 // like "1(%eax,,1)", the assembler doesn't.
527 if (getLexer().is(AsmToken::Percent)) {
529 if (ParseRegister(IndexReg, L, L)) return 0;
531 if (getLexer().isNot(AsmToken::RParen)) {
532 // Parse the scale amount:
533 // ::= ',' [scale-expression]
534 if (getLexer().isNot(AsmToken::Comma)) {
535 Error(Parser.getTok().getLoc(),
536 "expected comma in scale expression");
539 Parser.Lex(); // Eat the comma.
541 if (getLexer().isNot(AsmToken::RParen)) {
542 SMLoc Loc = Parser.getTok().getLoc();
545 if (getParser().ParseAbsoluteExpression(ScaleVal))
548 // Validate the scale amount.
549 if (ScaleVal != 1 && ScaleVal != 2 && ScaleVal != 4 && ScaleVal != 8){
550 Error(Loc, "scale factor in address must be 1, 2, 4 or 8");
553 Scale = (unsigned)ScaleVal;
556 } else if (getLexer().isNot(AsmToken::RParen)) {
557 // Otherwise we have the unsupported form of a scale amount without an
559 SMLoc Loc = Parser.getTok().getLoc();
562 if (getParser().ParseAbsoluteExpression(Value))
565 Error(Loc, "cannot have scale factor without index register");
570 // Ok, we've eaten the memory operand, verify we have a ')' and eat it too.
571 if (getLexer().isNot(AsmToken::RParen)) {
572 Error(Parser.getTok().getLoc(), "unexpected token in memory operand");
575 SMLoc MemEnd = Parser.getTok().getLoc();
576 Parser.Lex(); // Eat the ')'.
578 return X86Operand::CreateMem(SegReg, Disp, BaseReg, IndexReg, Scale,
582 bool X86ATTAsmParser::
583 ParseInstruction(const StringRef &Name, SMLoc NameLoc,
584 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
585 // The various flavors of pushf and popf use Requires<In32BitMode> and
586 // Requires<In64BitMode>, but the assembler doesn't yet implement that.
587 // For now, just do a manual check to prevent silent misencoding.
590 return Error(NameLoc, "popfl cannot be encoded in 64-bit mode");
591 else if (Name == "pushfl")
592 return Error(NameLoc, "pushfl cannot be encoded in 64-bit mode");
595 return Error(NameLoc, "popfq cannot be encoded in 32-bit mode");
596 else if (Name == "pushfq")
597 return Error(NameLoc, "pushfq cannot be encoded in 32-bit mode");
600 // FIXME: Hack to recognize "sal..." and "rep..." for now. We need a way to
601 // represent alternative syntaxes in the .td file, without requiring
602 // instruction duplication.
603 StringRef PatchedName = StringSwitch<StringRef>(Name)
605 .Case("salb", "shlb")
606 .Case("sall", "shll")
607 .Case("salq", "shlq")
608 .Case("salw", "shlw")
611 .Case("repnz", "repne")
612 .Case("pushf", Is64Bit ? "pushfq" : "pushfl")
613 .Case("popf", Is64Bit ? "popfq" : "popfl")
614 .Case("retl", Is64Bit ? "retl" : "ret")
615 .Case("retq", Is64Bit ? "ret" : "retq")
616 .Case("setz", "sete")
617 .Case("setnz", "setne")
621 Operands.push_back(X86Operand::CreateToken(PatchedName, NameLoc));
623 if (getLexer().isNot(AsmToken::EndOfStatement)) {
625 // Parse '*' modifier.
626 if (getLexer().is(AsmToken::Star)) {
627 SMLoc Loc = Parser.getTok().getLoc();
628 Operands.push_back(X86Operand::CreateToken("*", Loc));
629 Parser.Lex(); // Eat the star.
632 // Read the first operand.
633 if (X86Operand *Op = ParseOperand())
634 Operands.push_back(Op);
638 while (getLexer().is(AsmToken::Comma)) {
639 Parser.Lex(); // Eat the comma.
641 // Parse and remember the operand.
642 if (X86Operand *Op = ParseOperand())
643 Operands.push_back(Op);
649 // FIXME: Hack to handle recognizing s{hr,ar,hl}? $1.
650 if ((Name.startswith("shr") || Name.startswith("sar") ||
651 Name.startswith("shl")) &&
652 Operands.size() == 3 &&
653 static_cast<X86Operand*>(Operands[1])->isImm() &&
654 isa<MCConstantExpr>(static_cast<X86Operand*>(Operands[1])->getImm()) &&
655 cast<MCConstantExpr>(static_cast<X86Operand*>(Operands[1])->getImm())->getValue() == 1) {
657 Operands.erase(Operands.begin() + 1);
663 bool X86ATTAsmParser::ParseDirective(AsmToken DirectiveID) {
664 StringRef IDVal = DirectiveID.getIdentifier();
665 if (IDVal == ".word")
666 return ParseDirectiveWord(2, DirectiveID.getLoc());
670 /// ParseDirectiveWord
671 /// ::= .word [ expression (, expression)* ]
672 bool X86ATTAsmParser::ParseDirectiveWord(unsigned Size, SMLoc L) {
673 if (getLexer().isNot(AsmToken::EndOfStatement)) {
676 if (getParser().ParseExpression(Value))
679 getParser().getStreamer().EmitValue(Value, Size, 0 /*addrspace*/);
681 if (getLexer().is(AsmToken::EndOfStatement))
684 // FIXME: Improve diagnostic.
685 if (getLexer().isNot(AsmToken::Comma))
686 return Error(L, "unexpected token in directive");
695 /// LowerMOffset - Lower an 'moffset' form of an instruction, which just has a
696 /// imm operand, to having "rm" or "mr" operands with the offset in the disp
698 static void LowerMOffset(MCInst &Inst, unsigned Opc, unsigned RegNo,
700 MCOperand Disp = Inst.getOperand(0);
702 // Start over with an empty instruction.
707 Inst.addOperand(MCOperand::CreateReg(RegNo));
709 // Add the mem operand.
710 Inst.addOperand(MCOperand::CreateReg(0)); // Segment
711 Inst.addOperand(MCOperand::CreateImm(1)); // Scale
712 Inst.addOperand(MCOperand::CreateReg(0)); // IndexReg
713 Inst.addOperand(Disp); // Displacement
714 Inst.addOperand(MCOperand::CreateReg(0)); // BaseReg
717 Inst.addOperand(MCOperand::CreateReg(RegNo));
720 // FIXME: Custom X86 cleanup function to implement a temporary hack to handle
721 // matching INCL/DECL correctly for x86_64. This needs to be replaced by a
722 // proper mechanism for supporting (ambiguous) feature dependent instructions.
723 void X86ATTAsmParser::InstructionCleanup(MCInst &Inst) {
724 if (!Is64Bit) return;
726 switch (Inst.getOpcode()) {
727 case X86::DEC16r: Inst.setOpcode(X86::DEC64_16r); break;
728 case X86::DEC16m: Inst.setOpcode(X86::DEC64_16m); break;
729 case X86::DEC32r: Inst.setOpcode(X86::DEC64_32r); break;
730 case X86::DEC32m: Inst.setOpcode(X86::DEC64_32m); break;
731 case X86::INC16r: Inst.setOpcode(X86::INC64_16r); break;
732 case X86::INC16m: Inst.setOpcode(X86::INC64_16m); break;
733 case X86::INC32r: Inst.setOpcode(X86::INC64_32r); break;
734 case X86::INC32m: Inst.setOpcode(X86::INC64_32m); break;
736 // moffset instructions are x86-32 only.
737 case X86::MOV8o8a: LowerMOffset(Inst, X86::MOV8rm , X86::AL , false); break;
738 case X86::MOV16o16a: LowerMOffset(Inst, X86::MOV16rm, X86::AX , false); break;
739 case X86::MOV32o32a: LowerMOffset(Inst, X86::MOV32rm, X86::EAX, false); break;
740 case X86::MOV8ao8: LowerMOffset(Inst, X86::MOV8mr , X86::AL , true); break;
741 case X86::MOV16ao16: LowerMOffset(Inst, X86::MOV16mr, X86::AX , true); break;
742 case X86::MOV32ao32: LowerMOffset(Inst, X86::MOV32mr, X86::EAX, true); break;
747 X86ATTAsmParser::MatchInstruction(const SmallVectorImpl<MCParsedAsmOperand*>
750 // First, try a direct match.
751 if (!MatchInstructionImpl(Operands, Inst))
754 // Ignore anything which is obviously not a suffix match.
755 if (Operands.size() == 0)
757 X86Operand *Op = static_cast<X86Operand*>(Operands[0]);
758 if (!Op->isToken() || Op->getToken().size() > 15)
761 // FIXME: Ideally, we would only attempt suffix matches for things which are
762 // valid prefixes, and we could just infer the right unambiguous
763 // type. However, that requires substantially more matcher support than the
766 // Change the operand to point to a temporary token.
768 StringRef Base = Op->getToken();
769 memcpy(Tmp, Base.data(), Base.size());
770 Op->setTokenValue(StringRef(Tmp, Base.size() + 1));
772 // Check for the various suffix matches.
773 Tmp[Base.size()] = 'b';
774 bool MatchB = MatchInstructionImpl(Operands, Inst);
775 Tmp[Base.size()] = 'w';
776 bool MatchW = MatchInstructionImpl(Operands, Inst);
777 Tmp[Base.size()] = 'l';
778 bool MatchL = MatchInstructionImpl(Operands, Inst);
779 Tmp[Base.size()] = 'q';
780 bool MatchQ = MatchInstructionImpl(Operands, Inst);
782 // Restore the old token.
783 Op->setTokenValue(Base);
785 // If exactly one matched, then we treat that as a successful match (and the
786 // instruction will already have been filled in correctly, since the failing
787 // matches won't have modified it).
788 if (MatchB + MatchW + MatchL + MatchQ == 3)
791 // Otherwise, the match failed.
796 extern "C" void LLVMInitializeX86AsmLexer();
798 // Force static initialization.
799 extern "C" void LLVMInitializeX86AsmParser() {
800 RegisterAsmParser<X86_32ATTAsmParser> X(TheX86_32Target);
801 RegisterAsmParser<X86_64ATTAsmParser> Y(TheX86_64Target);
802 LLVMInitializeX86AsmLexer();
805 #include "X86GenAsmMatcher.inc"