1 //===-- X86AsmParser.cpp - Parse X86 assembly to MCInst instructions ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "llvm/Target/TargetAsmParser.h"
12 #include "X86Subtarget.h"
13 #include "llvm/Target/TargetRegistry.h"
14 #include "llvm/Target/TargetAsmParser.h"
15 #include "llvm/MC/MCStreamer.h"
16 #include "llvm/MC/MCExpr.h"
17 #include "llvm/MC/MCInst.h"
18 #include "llvm/MC/MCParser/MCAsmLexer.h"
19 #include "llvm/MC/MCParser/MCAsmParser.h"
20 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
21 #include "llvm/ADT/SmallString.h"
22 #include "llvm/ADT/SmallVector.h"
23 #include "llvm/ADT/StringExtras.h"
24 #include "llvm/ADT/StringSwitch.h"
25 #include "llvm/ADT/Twine.h"
26 #include "llvm/Support/SourceMgr.h"
27 #include "llvm/Support/raw_ostream.h"
33 class X86ATTAsmParser : public TargetAsmParser {
41 MCAsmParser &getParser() const { return Parser; }
43 MCAsmLexer &getLexer() const { return Parser.getLexer(); }
45 bool Error(SMLoc L, const Twine &Msg) { return Parser.Error(L, Msg); }
47 bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc);
49 X86Operand *ParseOperand();
50 X86Operand *ParseMemOperand(unsigned SegReg, SMLoc StartLoc);
52 bool ParseDirectiveWord(unsigned Size, SMLoc L);
54 bool MatchAndEmitInstruction(SMLoc IDLoc,
55 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
58 /// @name Auto-generated Matcher Functions
61 #define GET_ASSEMBLER_HEADER
62 #include "X86GenAsmMatcher.inc"
67 X86ATTAsmParser(const Target &T, MCAsmParser &parser, TargetMachine &TM)
68 : TargetAsmParser(T), Parser(parser), TM(TM) {
70 // Initialize the set of available features.
71 setAvailableFeatures(ComputeAvailableFeatures(
72 &TM.getSubtarget<X86Subtarget>()));
75 virtual bool ParseInstruction(StringRef Name, SMLoc NameLoc,
76 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
78 virtual bool ParseDirective(AsmToken DirectiveID);
81 class X86_32ATTAsmParser : public X86ATTAsmParser {
83 X86_32ATTAsmParser(const Target &T, MCAsmParser &Parser, TargetMachine &TM)
84 : X86ATTAsmParser(T, Parser, TM) {
89 class X86_64ATTAsmParser : public X86ATTAsmParser {
91 X86_64ATTAsmParser(const Target &T, MCAsmParser &Parser, TargetMachine &TM)
92 : X86ATTAsmParser(T, Parser, TM) {
97 } // end anonymous namespace
99 /// @name Auto-generated Match Functions
102 static unsigned MatchRegisterName(StringRef Name);
108 /// X86Operand - Instances of this class represent a parsed X86 machine
110 struct X86Operand : public MCParsedAsmOperand {
118 SMLoc StartLoc, EndLoc;
143 X86Operand(KindTy K, SMLoc Start, SMLoc End)
144 : Kind(K), StartLoc(Start), EndLoc(End) {}
146 /// getStartLoc - Get the location of the first token of this operand.
147 SMLoc getStartLoc() const { return StartLoc; }
148 /// getEndLoc - Get the location of the last token of this operand.
149 SMLoc getEndLoc() const { return EndLoc; }
151 virtual void dump(raw_ostream &OS) const {}
153 StringRef getToken() const {
154 assert(Kind == Token && "Invalid access!");
155 return StringRef(Tok.Data, Tok.Length);
157 void setTokenValue(StringRef Value) {
158 assert(Kind == Token && "Invalid access!");
159 Tok.Data = Value.data();
160 Tok.Length = Value.size();
163 unsigned getReg() const {
164 assert(Kind == Register && "Invalid access!");
168 const MCExpr *getImm() const {
169 assert(Kind == Immediate && "Invalid access!");
173 const MCExpr *getMemDisp() const {
174 assert(Kind == Memory && "Invalid access!");
177 unsigned getMemSegReg() const {
178 assert(Kind == Memory && "Invalid access!");
181 unsigned getMemBaseReg() const {
182 assert(Kind == Memory && "Invalid access!");
185 unsigned getMemIndexReg() const {
186 assert(Kind == Memory && "Invalid access!");
189 unsigned getMemScale() const {
190 assert(Kind == Memory && "Invalid access!");
194 bool isToken() const {return Kind == Token; }
196 bool isImm() const { return Kind == Immediate; }
198 bool isImmSExti16i8() const {
202 // If this isn't a constant expr, just assume it fits and let relaxation
204 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
208 // Otherwise, check the value is in a range that makes sense for this
210 uint64_t Value = CE->getValue();
211 return (( Value <= 0x000000000000007FULL)||
212 (0x000000000000FF80ULL <= Value && Value <= 0x000000000000FFFFULL)||
213 (0xFFFFFFFFFFFFFF80ULL <= Value && Value <= 0xFFFFFFFFFFFFFFFFULL));
215 bool isImmSExti32i8() const {
219 // If this isn't a constant expr, just assume it fits and let relaxation
221 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
225 // Otherwise, check the value is in a range that makes sense for this
227 uint64_t Value = CE->getValue();
228 return (( Value <= 0x000000000000007FULL)||
229 (0x00000000FFFFFF80ULL <= Value && Value <= 0x00000000FFFFFFFFULL)||
230 (0xFFFFFFFFFFFFFF80ULL <= Value && Value <= 0xFFFFFFFFFFFFFFFFULL));
232 bool isImmSExti64i8() const {
236 // If this isn't a constant expr, just assume it fits and let relaxation
238 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
242 // Otherwise, check the value is in a range that makes sense for this
244 uint64_t Value = CE->getValue();
245 return (( Value <= 0x000000000000007FULL)||
246 (0xFFFFFFFFFFFFFF80ULL <= Value && Value <= 0xFFFFFFFFFFFFFFFFULL));
248 bool isImmSExti64i32() const {
252 // If this isn't a constant expr, just assume it fits and let relaxation
254 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
258 // Otherwise, check the value is in a range that makes sense for this
260 uint64_t Value = CE->getValue();
261 return (( Value <= 0x000000007FFFFFFFULL)||
262 (0xFFFFFFFF80000000ULL <= Value && Value <= 0xFFFFFFFFFFFFFFFFULL));
265 bool isMem() const { return Kind == Memory; }
267 bool isAbsMem() const {
268 return Kind == Memory && !getMemSegReg() && !getMemBaseReg() &&
269 !getMemIndexReg() && getMemScale() == 1;
272 bool isReg() const { return Kind == Register; }
274 void addExpr(MCInst &Inst, const MCExpr *Expr) const {
275 // Add as immediates when possible.
276 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
277 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
279 Inst.addOperand(MCOperand::CreateExpr(Expr));
282 void addRegOperands(MCInst &Inst, unsigned N) const {
283 assert(N == 1 && "Invalid number of operands!");
284 Inst.addOperand(MCOperand::CreateReg(getReg()));
287 void addImmOperands(MCInst &Inst, unsigned N) const {
288 assert(N == 1 && "Invalid number of operands!");
289 addExpr(Inst, getImm());
292 void addMemOperands(MCInst &Inst, unsigned N) const {
293 assert((N == 5) && "Invalid number of operands!");
294 Inst.addOperand(MCOperand::CreateReg(getMemBaseReg()));
295 Inst.addOperand(MCOperand::CreateImm(getMemScale()));
296 Inst.addOperand(MCOperand::CreateReg(getMemIndexReg()));
297 addExpr(Inst, getMemDisp());
298 Inst.addOperand(MCOperand::CreateReg(getMemSegReg()));
301 void addAbsMemOperands(MCInst &Inst, unsigned N) const {
302 assert((N == 1) && "Invalid number of operands!");
303 Inst.addOperand(MCOperand::CreateExpr(getMemDisp()));
306 static X86Operand *CreateToken(StringRef Str, SMLoc Loc) {
307 X86Operand *Res = new X86Operand(Token, Loc, Loc);
308 Res->Tok.Data = Str.data();
309 Res->Tok.Length = Str.size();
313 static X86Operand *CreateReg(unsigned RegNo, SMLoc StartLoc, SMLoc EndLoc) {
314 X86Operand *Res = new X86Operand(Register, StartLoc, EndLoc);
315 Res->Reg.RegNo = RegNo;
319 static X86Operand *CreateImm(const MCExpr *Val, SMLoc StartLoc, SMLoc EndLoc){
320 X86Operand *Res = new X86Operand(Immediate, StartLoc, EndLoc);
325 /// Create an absolute memory operand.
326 static X86Operand *CreateMem(const MCExpr *Disp, SMLoc StartLoc,
328 X86Operand *Res = new X86Operand(Memory, StartLoc, EndLoc);
330 Res->Mem.Disp = Disp;
331 Res->Mem.BaseReg = 0;
332 Res->Mem.IndexReg = 0;
337 /// Create a generalized memory operand.
338 static X86Operand *CreateMem(unsigned SegReg, const MCExpr *Disp,
339 unsigned BaseReg, unsigned IndexReg,
340 unsigned Scale, SMLoc StartLoc, SMLoc EndLoc) {
341 // We should never just have a displacement, that should be parsed as an
342 // absolute memory operand.
343 assert((SegReg || BaseReg || IndexReg) && "Invalid memory operand!");
345 // The scale should always be one of {1,2,4,8}.
346 assert(((Scale == 1 || Scale == 2 || Scale == 4 || Scale == 8)) &&
348 X86Operand *Res = new X86Operand(Memory, StartLoc, EndLoc);
349 Res->Mem.SegReg = SegReg;
350 Res->Mem.Disp = Disp;
351 Res->Mem.BaseReg = BaseReg;
352 Res->Mem.IndexReg = IndexReg;
353 Res->Mem.Scale = Scale;
358 } // end anonymous namespace.
361 bool X86ATTAsmParser::ParseRegister(unsigned &RegNo,
362 SMLoc &StartLoc, SMLoc &EndLoc) {
364 const AsmToken &TokPercent = Parser.getTok();
365 assert(TokPercent.is(AsmToken::Percent) && "Invalid token kind!");
366 StartLoc = TokPercent.getLoc();
367 Parser.Lex(); // Eat percent token.
369 const AsmToken &Tok = Parser.getTok();
370 if (Tok.isNot(AsmToken::Identifier))
371 return Error(Tok.getLoc(), "invalid register name");
373 // FIXME: Validate register for the current architecture; we have to do
374 // validation later, so maybe there is no need for this here.
375 RegNo = MatchRegisterName(Tok.getString());
377 // If the match failed, try the register name as lowercase.
379 RegNo = MatchRegisterName(LowercaseString(Tok.getString()));
381 // FIXME: This should be done using Requires<In32BitMode> and
382 // Requires<In64BitMode> so "eiz" usage in 64-bit instructions
383 // can be also checked.
384 if (RegNo == X86::RIZ && !Is64Bit)
385 return Error(Tok.getLoc(), "riz register in 64-bit mode only");
387 // Parse "%st" as "%st(0)" and "%st(1)", which is multiple tokens.
388 if (RegNo == 0 && (Tok.getString() == "st" || Tok.getString() == "ST")) {
390 EndLoc = Tok.getLoc();
391 Parser.Lex(); // Eat 'st'
393 // Check to see if we have '(4)' after %st.
394 if (getLexer().isNot(AsmToken::LParen))
399 const AsmToken &IntTok = Parser.getTok();
400 if (IntTok.isNot(AsmToken::Integer))
401 return Error(IntTok.getLoc(), "expected stack index");
402 switch (IntTok.getIntVal()) {
403 case 0: RegNo = X86::ST0; break;
404 case 1: RegNo = X86::ST1; break;
405 case 2: RegNo = X86::ST2; break;
406 case 3: RegNo = X86::ST3; break;
407 case 4: RegNo = X86::ST4; break;
408 case 5: RegNo = X86::ST5; break;
409 case 6: RegNo = X86::ST6; break;
410 case 7: RegNo = X86::ST7; break;
411 default: return Error(IntTok.getLoc(), "invalid stack index");
414 if (getParser().Lex().isNot(AsmToken::RParen))
415 return Error(Parser.getTok().getLoc(), "expected ')'");
417 EndLoc = Tok.getLoc();
418 Parser.Lex(); // Eat ')'
422 // If this is "db[0-7]", match it as an alias
424 if (RegNo == 0 && Tok.getString().size() == 3 &&
425 Tok.getString().startswith("db")) {
426 switch (Tok.getString()[2]) {
427 case '0': RegNo = X86::DR0; break;
428 case '1': RegNo = X86::DR1; break;
429 case '2': RegNo = X86::DR2; break;
430 case '3': RegNo = X86::DR3; break;
431 case '4': RegNo = X86::DR4; break;
432 case '5': RegNo = X86::DR5; break;
433 case '6': RegNo = X86::DR6; break;
434 case '7': RegNo = X86::DR7; break;
438 EndLoc = Tok.getLoc();
439 Parser.Lex(); // Eat it.
445 return Error(Tok.getLoc(), "invalid register name");
447 EndLoc = Tok.getLoc();
448 Parser.Lex(); // Eat identifier token.
452 X86Operand *X86ATTAsmParser::ParseOperand() {
453 switch (getLexer().getKind()) {
455 // Parse a memory operand with no segment register.
456 return ParseMemOperand(0, Parser.getTok().getLoc());
457 case AsmToken::Percent: {
458 // Read the register.
461 if (ParseRegister(RegNo, Start, End)) return 0;
462 if (RegNo == X86::EIZ || RegNo == X86::RIZ) {
463 Error(Start, "eiz and riz can only be used as index registers");
467 // If this is a segment register followed by a ':', then this is the start
468 // of a memory reference, otherwise this is a normal register reference.
469 if (getLexer().isNot(AsmToken::Colon))
470 return X86Operand::CreateReg(RegNo, Start, End);
473 getParser().Lex(); // Eat the colon.
474 return ParseMemOperand(RegNo, Start);
476 case AsmToken::Dollar: {
478 SMLoc Start = Parser.getTok().getLoc(), End;
481 if (getParser().ParseExpression(Val, End))
483 return X86Operand::CreateImm(Val, Start, End);
488 /// ParseMemOperand: segment: disp(basereg, indexreg, scale). The '%ds:' prefix
489 /// has already been parsed if present.
490 X86Operand *X86ATTAsmParser::ParseMemOperand(unsigned SegReg, SMLoc MemStart) {
492 // We have to disambiguate a parenthesized expression "(4+5)" from the start
493 // of a memory operand with a missing displacement "(%ebx)" or "(,%eax)". The
494 // only way to do this without lookahead is to eat the '(' and see what is
496 const MCExpr *Disp = MCConstantExpr::Create(0, getParser().getContext());
497 if (getLexer().isNot(AsmToken::LParen)) {
499 if (getParser().ParseExpression(Disp, ExprEnd)) return 0;
501 // After parsing the base expression we could either have a parenthesized
502 // memory address or not. If not, return now. If so, eat the (.
503 if (getLexer().isNot(AsmToken::LParen)) {
504 // Unless we have a segment register, treat this as an immediate.
506 return X86Operand::CreateMem(Disp, MemStart, ExprEnd);
507 return X86Operand::CreateMem(SegReg, Disp, 0, 0, 1, MemStart, ExprEnd);
513 // Okay, we have a '('. We don't know if this is an expression or not, but
514 // so we have to eat the ( to see beyond it.
515 SMLoc LParenLoc = Parser.getTok().getLoc();
516 Parser.Lex(); // Eat the '('.
518 if (getLexer().is(AsmToken::Percent) || getLexer().is(AsmToken::Comma)) {
519 // Nothing to do here, fall into the code below with the '(' part of the
520 // memory operand consumed.
524 // It must be an parenthesized expression, parse it now.
525 if (getParser().ParseParenExpression(Disp, ExprEnd))
528 // After parsing the base expression we could either have a parenthesized
529 // memory address or not. If not, return now. If so, eat the (.
530 if (getLexer().isNot(AsmToken::LParen)) {
531 // Unless we have a segment register, treat this as an immediate.
533 return X86Operand::CreateMem(Disp, LParenLoc, ExprEnd);
534 return X86Operand::CreateMem(SegReg, Disp, 0, 0, 1, MemStart, ExprEnd);
542 // If we reached here, then we just ate the ( of the memory operand. Process
543 // the rest of the memory operand.
544 unsigned BaseReg = 0, IndexReg = 0, Scale = 1;
546 if (getLexer().is(AsmToken::Percent)) {
548 if (ParseRegister(BaseReg, L, L)) return 0;
549 if (BaseReg == X86::EIZ || BaseReg == X86::RIZ) {
550 Error(L, "eiz and riz can only be used as index registers");
555 if (getLexer().is(AsmToken::Comma)) {
556 Parser.Lex(); // Eat the comma.
558 // Following the comma we should have either an index register, or a scale
559 // value. We don't support the later form, but we want to parse it
562 // Not that even though it would be completely consistent to support syntax
563 // like "1(%eax,,1)", the assembler doesn't. Use "eiz" or "riz" for this.
564 if (getLexer().is(AsmToken::Percent)) {
566 if (ParseRegister(IndexReg, L, L)) return 0;
568 if (getLexer().isNot(AsmToken::RParen)) {
569 // Parse the scale amount:
570 // ::= ',' [scale-expression]
571 if (getLexer().isNot(AsmToken::Comma)) {
572 Error(Parser.getTok().getLoc(),
573 "expected comma in scale expression");
576 Parser.Lex(); // Eat the comma.
578 if (getLexer().isNot(AsmToken::RParen)) {
579 SMLoc Loc = Parser.getTok().getLoc();
582 if (getParser().ParseAbsoluteExpression(ScaleVal))
585 // Validate the scale amount.
586 if (ScaleVal != 1 && ScaleVal != 2 && ScaleVal != 4 && ScaleVal != 8){
587 Error(Loc, "scale factor in address must be 1, 2, 4 or 8");
590 Scale = (unsigned)ScaleVal;
593 } else if (getLexer().isNot(AsmToken::RParen)) {
594 // A scale amount without an index is ignored.
596 SMLoc Loc = Parser.getTok().getLoc();
599 if (getParser().ParseAbsoluteExpression(Value))
603 Warning(Loc, "scale factor without index register is ignored");
608 // Ok, we've eaten the memory operand, verify we have a ')' and eat it too.
609 if (getLexer().isNot(AsmToken::RParen)) {
610 Error(Parser.getTok().getLoc(), "unexpected token in memory operand");
613 SMLoc MemEnd = Parser.getTok().getLoc();
614 Parser.Lex(); // Eat the ')'.
616 return X86Operand::CreateMem(SegReg, Disp, BaseReg, IndexReg, Scale,
620 bool X86ATTAsmParser::
621 ParseInstruction(StringRef Name, SMLoc NameLoc,
622 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
623 StringRef PatchedName = Name;
625 // FIXME: Hack to recognize cmp<comparison code>{ss,sd,ps,pd}.
626 const MCExpr *ExtraImmOp = 0;
627 if ((PatchedName.startswith("cmp") || PatchedName.startswith("vcmp")) &&
628 (PatchedName.endswith("ss") || PatchedName.endswith("sd") ||
629 PatchedName.endswith("ps") || PatchedName.endswith("pd"))) {
630 bool IsVCMP = PatchedName.startswith("vcmp");
631 unsigned SSECCIdx = IsVCMP ? 4 : 3;
632 unsigned SSEComparisonCode = StringSwitch<unsigned>(
633 PatchedName.slice(SSECCIdx, PatchedName.size() - 2))
646 .Case("neq_oq", 0x0C)
653 .Case("unord_s", 0x13)
654 .Case("neq_us", 0x14)
655 .Case("nlt_uq", 0x15)
656 .Case("nle_uq", 0x16)
659 .Case("nge_uq", 0x19)
660 .Case("ngt_uq", 0x1A)
661 .Case("false_os", 0x1B)
662 .Case("neq_os", 0x1C)
665 .Case("true_us", 0x1F)
667 if (SSEComparisonCode != ~0U) {
668 ExtraImmOp = MCConstantExpr::Create(SSEComparisonCode,
669 getParser().getContext());
670 if (PatchedName.endswith("ss")) {
671 PatchedName = IsVCMP ? "vcmpss" : "cmpss";
672 } else if (PatchedName.endswith("sd")) {
673 PatchedName = IsVCMP ? "vcmpsd" : "cmpsd";
674 } else if (PatchedName.endswith("ps")) {
675 PatchedName = IsVCMP ? "vcmpps" : "cmpps";
677 assert(PatchedName.endswith("pd") && "Unexpected mnemonic!");
678 PatchedName = IsVCMP ? "vcmppd" : "cmppd";
683 // FIXME: Hack to recognize vpclmul<src1_quadword, src2_quadword>dq
684 if (PatchedName.startswith("vpclmul")) {
685 unsigned CLMULQuadWordSelect = StringSwitch<unsigned>(
686 PatchedName.slice(7, PatchedName.size() - 2))
687 .Case("lqlq", 0x00) // src1[63:0], src2[63:0]
688 .Case("hqlq", 0x01) // src1[127:64], src2[63:0]
689 .Case("lqhq", 0x10) // src1[63:0], src2[127:64]
690 .Case("hqhq", 0x11) // src1[127:64], src2[127:64]
692 if (CLMULQuadWordSelect != ~0U) {
693 ExtraImmOp = MCConstantExpr::Create(CLMULQuadWordSelect,
694 getParser().getContext());
695 assert(PatchedName.endswith("dq") && "Unexpected mnemonic!");
696 PatchedName = "vpclmulqdq";
700 Operands.push_back(X86Operand::CreateToken(PatchedName, NameLoc));
703 Operands.push_back(X86Operand::CreateImm(ExtraImmOp, NameLoc, NameLoc));
706 // Determine whether this is an instruction prefix.
708 Name == "lock" || Name == "rep" ||
709 Name == "repe" || Name == "repz" ||
710 Name == "repne" || Name == "repnz";
713 // This does the actual operand parsing. Don't parse any more if we have a
714 // prefix juxtaposed with an operation like "lock incl 4(%rax)", because we
715 // just want to parse the "lock" as the first instruction and the "incl" as
717 if (getLexer().isNot(AsmToken::EndOfStatement) && !isPrefix) {
719 // Parse '*' modifier.
720 if (getLexer().is(AsmToken::Star)) {
721 SMLoc Loc = Parser.getTok().getLoc();
722 Operands.push_back(X86Operand::CreateToken("*", Loc));
723 Parser.Lex(); // Eat the star.
726 // Read the first operand.
727 if (X86Operand *Op = ParseOperand())
728 Operands.push_back(Op);
730 Parser.EatToEndOfStatement();
734 while (getLexer().is(AsmToken::Comma)) {
735 Parser.Lex(); // Eat the comma.
737 // Parse and remember the operand.
738 if (X86Operand *Op = ParseOperand())
739 Operands.push_back(Op);
741 Parser.EatToEndOfStatement();
746 if (getLexer().isNot(AsmToken::EndOfStatement)) {
747 Parser.EatToEndOfStatement();
748 return TokError("unexpected token in argument list");
752 if (getLexer().is(AsmToken::EndOfStatement))
753 Parser.Lex(); // Consume the EndOfStatement
755 // This is a terrible hack to handle "out[bwl]? %al, (%dx)" ->
756 // "outb %al, %dx". Out doesn't take a memory form, but this is a widely
757 // documented form in various unofficial manuals, so a lot of code uses it.
758 if ((Name == "outb" || Name == "outw" || Name == "outl" || Name == "out") &&
759 Operands.size() == 3) {
760 X86Operand &Op = *(X86Operand*)Operands.back();
761 if (Op.isMem() && Op.Mem.SegReg == 0 &&
762 isa<MCConstantExpr>(Op.Mem.Disp) &&
763 cast<MCConstantExpr>(Op.Mem.Disp)->getValue() == 0 &&
764 Op.Mem.BaseReg == MatchRegisterName("dx") && Op.Mem.IndexReg == 0) {
765 SMLoc Loc = Op.getEndLoc();
766 Operands.back() = X86Operand::CreateReg(Op.Mem.BaseReg, Loc, Loc);
771 // FIXME: Hack to handle recognize s{hr,ar,hl} $1, <op>. Canonicalize to
773 if ((Name.startswith("shr") || Name.startswith("sar") ||
774 Name.startswith("shl") || Name.startswith("sal") ||
775 Name.startswith("rcl") || Name.startswith("rcr") ||
776 Name.startswith("rol") || Name.startswith("ror")) &&
777 Operands.size() == 3) {
778 X86Operand *Op1 = static_cast<X86Operand*>(Operands[1]);
779 if (Op1->isImm() && isa<MCConstantExpr>(Op1->getImm()) &&
780 cast<MCConstantExpr>(Op1->getImm())->getValue() == 1) {
782 Operands.erase(Operands.begin() + 1);
786 // FIXME: Hack to handle recognize "sh[lr]d op,op" -> "shld $1, op,op".
787 if ((Name.startswith("shld") || Name.startswith("shrd")) &&
788 Operands.size() == 3) {
789 const MCExpr *One = MCConstantExpr::Create(1, getParser().getContext());
790 Operands.insert(Operands.begin()+1,
791 X86Operand::CreateImm(One, NameLoc, NameLoc));
797 bool X86ATTAsmParser::
798 MatchAndEmitInstruction(SMLoc IDLoc,
799 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
801 assert(!Operands.empty() && "Unexpect empty operand list!");
802 X86Operand *Op = static_cast<X86Operand*>(Operands[0]);
803 assert(Op->isToken() && "Leading operand should always be a mnemonic!");
805 // First, handle aliases that expand to multiple instructions.
806 // FIXME: This should be replaced with a real .td file alias mechanism.
807 // Also, MatchInstructionImpl should do actually *do* the EmitInstruction
809 if (Op->getToken() == "fstsw" || Op->getToken() == "fstcw" ||
810 Op->getToken() == "fstsww" || Op->getToken() == "fstcww" ||
811 Op->getToken() == "finit" || Op->getToken() == "fsave" ||
812 Op->getToken() == "fstenv" || Op->getToken() == "fclex") {
814 Inst.setOpcode(X86::WAIT);
815 Out.EmitInstruction(Inst);
818 StringSwitch<const char*>(Op->getToken())
819 .Case("finit", "fninit")
820 .Case("fsave", "fnsave")
821 .Case("fstcw", "fnstcw")
822 .Case("fstcww", "fnstcw")
823 .Case("fstenv", "fnstenv")
824 .Case("fstsw", "fnstsw")
825 .Case("fstsww", "fnstsw")
826 .Case("fclex", "fnclex")
828 assert(Repl && "Unknown wait-prefixed instruction");
830 Operands[0] = X86Operand::CreateToken(Repl, IDLoc);
833 bool WasOriginallyInvalidOperand = false;
834 unsigned OrigErrorInfo;
837 // First, try a direct match.
838 switch (MatchInstructionImpl(Operands, Inst, OrigErrorInfo)) {
840 Out.EmitInstruction(Inst);
842 case Match_MissingFeature:
843 Error(IDLoc, "instruction requires a CPU feature not currently enabled");
845 case Match_InvalidOperand:
846 WasOriginallyInvalidOperand = true;
848 case Match_MnemonicFail:
852 // FIXME: Ideally, we would only attempt suffix matches for things which are
853 // valid prefixes, and we could just infer the right unambiguous
854 // type. However, that requires substantially more matcher support than the
857 // Change the operand to point to a temporary token.
858 StringRef Base = Op->getToken();
862 Op->setTokenValue(Tmp.str());
864 // If this instruction starts with an 'f', then it is a floating point stack
865 // instruction. These come in up to three forms for 32-bit, 64-bit, and
866 // 80-bit floating point, which use the suffixes s,l,t respectively.
868 // Otherwise, we assume that this may be an integer instruction, which comes
869 // in 8/16/32/64-bit forms using the b,w,l,q suffixes respectively.
870 const char *Suffixes = Base[0] != 'f' ? "bwlq" : "slt\0";
872 // Check for the various suffix matches.
873 Tmp[Base.size()] = Suffixes[0];
874 unsigned ErrorInfoIgnore;
875 MatchResultTy Match1, Match2, Match3, Match4;
877 Match1 = MatchInstructionImpl(Operands, Inst, ErrorInfoIgnore);
878 Tmp[Base.size()] = Suffixes[1];
879 Match2 = MatchInstructionImpl(Operands, Inst, ErrorInfoIgnore);
880 Tmp[Base.size()] = Suffixes[2];
881 Match3 = MatchInstructionImpl(Operands, Inst, ErrorInfoIgnore);
882 Tmp[Base.size()] = Suffixes[3];
883 Match4 = MatchInstructionImpl(Operands, Inst, ErrorInfoIgnore);
885 // Restore the old token.
886 Op->setTokenValue(Base);
888 // If exactly one matched, then we treat that as a successful match (and the
889 // instruction will already have been filled in correctly, since the failing
890 // matches won't have modified it).
891 unsigned NumSuccessfulMatches =
892 (Match1 == Match_Success) + (Match2 == Match_Success) +
893 (Match3 == Match_Success) + (Match4 == Match_Success);
894 if (NumSuccessfulMatches == 1) {
895 Out.EmitInstruction(Inst);
899 // Otherwise, the match failed, try to produce a decent error message.
901 // If we had multiple suffix matches, then identify this as an ambiguous
903 if (NumSuccessfulMatches > 1) {
905 unsigned NumMatches = 0;
906 if (Match1 == Match_Success) MatchChars[NumMatches++] = Suffixes[0];
907 if (Match2 == Match_Success) MatchChars[NumMatches++] = Suffixes[1];
908 if (Match3 == Match_Success) MatchChars[NumMatches++] = Suffixes[2];
909 if (Match4 == Match_Success) MatchChars[NumMatches++] = Suffixes[3];
911 SmallString<126> Msg;
912 raw_svector_ostream OS(Msg);
913 OS << "ambiguous instructions require an explicit suffix (could be ";
914 for (unsigned i = 0; i != NumMatches; ++i) {
917 if (i + 1 == NumMatches)
919 OS << "'" << Base << MatchChars[i] << "'";
922 Error(IDLoc, OS.str());
926 // Okay, we know that none of the variants matched successfully.
928 // If all of the instructions reported an invalid mnemonic, then the original
929 // mnemonic was invalid.
930 if ((Match1 == Match_MnemonicFail) && (Match2 == Match_MnemonicFail) &&
931 (Match3 == Match_MnemonicFail) && (Match4 == Match_MnemonicFail)) {
932 if (!WasOriginallyInvalidOperand) {
933 Error(IDLoc, "invalid instruction mnemonic '" + Base + "'");
937 // Recover location info for the operand if we know which was the problem.
938 SMLoc ErrorLoc = IDLoc;
939 if (OrigErrorInfo != ~0U) {
940 if (OrigErrorInfo >= Operands.size())
941 return Error(IDLoc, "too few operands for instruction");
943 ErrorLoc = ((X86Operand*)Operands[OrigErrorInfo])->getStartLoc();
944 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
947 return Error(ErrorLoc, "invalid operand for instruction");
950 // If one instruction matched with a missing feature, report this as a
952 if ((Match1 == Match_MissingFeature) + (Match2 == Match_MissingFeature) +
953 (Match3 == Match_MissingFeature) + (Match4 == Match_MissingFeature) == 1){
954 Error(IDLoc, "instruction requires a CPU feature not currently enabled");
958 // If one instruction matched with an invalid operand, report this as an
960 if ((Match1 == Match_InvalidOperand) + (Match2 == Match_InvalidOperand) +
961 (Match3 == Match_InvalidOperand) + (Match4 == Match_InvalidOperand) == 1){
962 Error(IDLoc, "invalid operand for instruction");
966 // If all of these were an outright failure, report it in a useless way.
967 // FIXME: We should give nicer diagnostics about the exact failure.
968 Error(IDLoc, "unknown use of instruction mnemonic without a size suffix");
973 bool X86ATTAsmParser::ParseDirective(AsmToken DirectiveID) {
974 StringRef IDVal = DirectiveID.getIdentifier();
975 if (IDVal == ".word")
976 return ParseDirectiveWord(2, DirectiveID.getLoc());
980 /// ParseDirectiveWord
981 /// ::= .word [ expression (, expression)* ]
982 bool X86ATTAsmParser::ParseDirectiveWord(unsigned Size, SMLoc L) {
983 if (getLexer().isNot(AsmToken::EndOfStatement)) {
986 if (getParser().ParseExpression(Value))
989 getParser().getStreamer().EmitValue(Value, Size, 0 /*addrspace*/);
991 if (getLexer().is(AsmToken::EndOfStatement))
994 // FIXME: Improve diagnostic.
995 if (getLexer().isNot(AsmToken::Comma))
996 return Error(L, "unexpected token in directive");
1008 extern "C" void LLVMInitializeX86AsmLexer();
1010 // Force static initialization.
1011 extern "C" void LLVMInitializeX86AsmParser() {
1012 RegisterAsmParser<X86_32ATTAsmParser> X(TheX86_32Target);
1013 RegisterAsmParser<X86_64ATTAsmParser> Y(TheX86_64Target);
1014 LLVMInitializeX86AsmLexer();
1017 #define GET_REGISTER_MATCHER
1018 #define GET_MATCHER_IMPLEMENTATION
1019 #include "X86GenAsmMatcher.inc"