1 //===-- X86AsmParser.cpp - Parse X86 assembly to MCInst instructions ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "MCTargetDesc/X86BaseInfo.h"
11 #include "llvm/MC/MCTargetAsmParser.h"
12 #include "llvm/MC/MCStreamer.h"
13 #include "llvm/MC/MCExpr.h"
14 #include "llvm/MC/MCInst.h"
15 #include "llvm/MC/MCRegisterInfo.h"
16 #include "llvm/MC/MCSubtargetInfo.h"
17 #include "llvm/MC/MCParser/MCAsmLexer.h"
18 #include "llvm/MC/MCParser/MCAsmParser.h"
19 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
20 #include "llvm/ADT/OwningPtr.h"
21 #include "llvm/ADT/SmallString.h"
22 #include "llvm/ADT/SmallVector.h"
23 #include "llvm/ADT/StringSwitch.h"
24 #include "llvm/ADT/Twine.h"
25 #include "llvm/Support/SourceMgr.h"
26 #include "llvm/Support/TargetRegistry.h"
27 #include "llvm/Support/raw_ostream.h"
34 class X86AsmParser : public MCTargetAsmParser {
39 MCAsmParser &getParser() const { return Parser; }
41 MCAsmLexer &getLexer() const { return Parser.getLexer(); }
43 bool Error(SMLoc L, const Twine &Msg,
44 ArrayRef<SMRange> Ranges = ArrayRef<SMRange>()) {
45 return Parser.Error(L, Msg, Ranges);
48 X86Operand *ErrorOperand(SMLoc Loc, StringRef Msg) {
53 X86Operand *ParseOperand();
54 X86Operand *ParseATTOperand();
55 X86Operand *ParseIntelOperand();
56 X86Operand *ParseIntelMemOperand();
57 X86Operand *ParseIntelBracExpression(unsigned Size);
58 X86Operand *ParseMemOperand(unsigned SegReg, SMLoc StartLoc);
60 bool ParseDirectiveWord(unsigned Size, SMLoc L);
61 bool ParseDirectiveCode(StringRef IDVal, SMLoc L);
63 bool processInstruction(MCInst &Inst,
64 const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
66 bool MatchAndEmitInstruction(SMLoc IDLoc,
67 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
70 /// isSrcOp - Returns true if operand is either (%rsi) or %ds:%(rsi)
71 /// in 64bit mode or (%edi) or %es:(%edi) in 32bit mode.
72 bool isSrcOp(X86Operand &Op);
74 /// isDstOp - Returns true if operand is either %es:(%rdi) in 64bit mode
75 /// or %es:(%edi) in 32bit mode.
76 bool isDstOp(X86Operand &Op);
78 bool is64BitMode() const {
79 // FIXME: Can tablegen auto-generate this?
80 return (STI.getFeatureBits() & X86::Mode64Bit) != 0;
83 unsigned FB = ComputeAvailableFeatures(STI.ToggleFeature(X86::Mode64Bit));
84 setAvailableFeatures(FB);
87 /// @name Auto-generated Matcher Functions
90 #define GET_ASSEMBLER_HEADER
91 #include "X86GenAsmMatcher.inc"
96 X86AsmParser(MCSubtargetInfo &sti, MCAsmParser &parser)
97 : MCTargetAsmParser(), STI(sti), Parser(parser) {
99 // Initialize the set of available features.
100 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
102 virtual bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc);
104 virtual bool ParseInstruction(StringRef Name, SMLoc NameLoc,
105 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
107 virtual bool ParseDirective(AsmToken DirectiveID);
109 } // end anonymous namespace
111 /// @name Auto-generated Match Functions
114 static unsigned MatchRegisterName(StringRef Name);
118 static bool isImmSExti16i8Value(uint64_t Value) {
119 return (( Value <= 0x000000000000007FULL)||
120 (0x000000000000FF80ULL <= Value && Value <= 0x000000000000FFFFULL)||
121 (0xFFFFFFFFFFFFFF80ULL <= Value && Value <= 0xFFFFFFFFFFFFFFFFULL));
124 static bool isImmSExti32i8Value(uint64_t Value) {
125 return (( Value <= 0x000000000000007FULL)||
126 (0x00000000FFFFFF80ULL <= Value && Value <= 0x00000000FFFFFFFFULL)||
127 (0xFFFFFFFFFFFFFF80ULL <= Value && Value <= 0xFFFFFFFFFFFFFFFFULL));
130 static bool isImmZExtu32u8Value(uint64_t Value) {
131 return (Value <= 0x00000000000000FFULL);
134 static bool isImmSExti64i8Value(uint64_t Value) {
135 return (( Value <= 0x000000000000007FULL)||
136 (0xFFFFFFFFFFFFFF80ULL <= Value && Value <= 0xFFFFFFFFFFFFFFFFULL));
139 static bool isImmSExti64i32Value(uint64_t Value) {
140 return (( Value <= 0x000000007FFFFFFFULL)||
141 (0xFFFFFFFF80000000ULL <= Value && Value <= 0xFFFFFFFFFFFFFFFFULL));
145 /// X86Operand - Instances of this class represent a parsed X86 machine
147 struct X86Operand : public MCParsedAsmOperand {
155 SMLoc StartLoc, EndLoc;
181 X86Operand(KindTy K, SMLoc Start, SMLoc End)
182 : Kind(K), StartLoc(Start), EndLoc(End) {}
184 /// getStartLoc - Get the location of the first token of this operand.
185 SMLoc getStartLoc() const { return StartLoc; }
186 /// getEndLoc - Get the location of the last token of this operand.
187 SMLoc getEndLoc() const { return EndLoc; }
189 SMRange getLocRange() const { return SMRange(StartLoc, EndLoc); }
191 virtual void print(raw_ostream &OS) const {}
193 StringRef getToken() const {
194 assert(Kind == Token && "Invalid access!");
195 return StringRef(Tok.Data, Tok.Length);
197 void setTokenValue(StringRef Value) {
198 assert(Kind == Token && "Invalid access!");
199 Tok.Data = Value.data();
200 Tok.Length = Value.size();
203 unsigned getReg() const {
204 assert(Kind == Register && "Invalid access!");
208 const MCExpr *getImm() const {
209 assert(Kind == Immediate && "Invalid access!");
213 const MCExpr *getMemDisp() const {
214 assert(Kind == Memory && "Invalid access!");
217 unsigned getMemSegReg() const {
218 assert(Kind == Memory && "Invalid access!");
221 unsigned getMemBaseReg() const {
222 assert(Kind == Memory && "Invalid access!");
225 unsigned getMemIndexReg() const {
226 assert(Kind == Memory && "Invalid access!");
229 unsigned getMemScale() const {
230 assert(Kind == Memory && "Invalid access!");
234 bool isToken() const {return Kind == Token; }
236 bool isImm() const { return Kind == Immediate; }
238 bool isImmSExti16i8() const {
242 // If this isn't a constant expr, just assume it fits and let relaxation
244 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
248 // Otherwise, check the value is in a range that makes sense for this
250 return isImmSExti16i8Value(CE->getValue());
252 bool isImmSExti32i8() const {
256 // If this isn't a constant expr, just assume it fits and let relaxation
258 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
262 // Otherwise, check the value is in a range that makes sense for this
264 return isImmSExti32i8Value(CE->getValue());
266 bool isImmZExtu32u8() const {
270 // If this isn't a constant expr, just assume it fits and let relaxation
272 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
276 // Otherwise, check the value is in a range that makes sense for this
278 return isImmZExtu32u8Value(CE->getValue());
280 bool isImmSExti64i8() const {
284 // If this isn't a constant expr, just assume it fits and let relaxation
286 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
290 // Otherwise, check the value is in a range that makes sense for this
292 return isImmSExti64i8Value(CE->getValue());
294 bool isImmSExti64i32() const {
298 // If this isn't a constant expr, just assume it fits and let relaxation
300 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
304 // Otherwise, check the value is in a range that makes sense for this
306 return isImmSExti64i32Value(CE->getValue());
309 bool isMem() const { return Kind == Memory; }
310 bool isMem8() const {
311 return Kind == Memory && (!Mem.Size || Mem.Size == 8);
313 bool isMem16() const {
314 return Kind == Memory && (!Mem.Size || Mem.Size == 16);
316 bool isMem32() const {
317 return Kind == Memory && (!Mem.Size || Mem.Size == 32);
319 bool isMem64() const {
320 return Kind == Memory && (!Mem.Size || Mem.Size == 64);
322 bool isMem80() const {
323 return Kind == Memory && (!Mem.Size || Mem.Size == 80);
325 bool isMem128() const {
326 return Kind == Memory && (!Mem.Size || Mem.Size == 128);
328 bool isMem256() const {
329 return Kind == Memory && (!Mem.Size || Mem.Size == 256);
332 bool isAbsMem() const {
333 return Kind == Memory && !getMemSegReg() && !getMemBaseReg() &&
334 !getMemIndexReg() && getMemScale() == 1;
337 bool isReg() const { return Kind == Register; }
339 void addExpr(MCInst &Inst, const MCExpr *Expr) const {
340 // Add as immediates when possible.
341 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
342 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
344 Inst.addOperand(MCOperand::CreateExpr(Expr));
347 void addRegOperands(MCInst &Inst, unsigned N) const {
348 assert(N == 1 && "Invalid number of operands!");
349 Inst.addOperand(MCOperand::CreateReg(getReg()));
352 void addImmOperands(MCInst &Inst, unsigned N) const {
353 assert(N == 1 && "Invalid number of operands!");
354 addExpr(Inst, getImm());
357 void addMem8Operands(MCInst &Inst, unsigned N) const {
358 addMemOperands(Inst, N);
360 void addMem16Operands(MCInst &Inst, unsigned N) const {
361 addMemOperands(Inst, N);
363 void addMem32Operands(MCInst &Inst, unsigned N) const {
364 addMemOperands(Inst, N);
366 void addMem64Operands(MCInst &Inst, unsigned N) const {
367 addMemOperands(Inst, N);
369 void addMem80Operands(MCInst &Inst, unsigned N) const {
370 addMemOperands(Inst, N);
372 void addMem128Operands(MCInst &Inst, unsigned N) const {
373 addMemOperands(Inst, N);
375 void addMem256Operands(MCInst &Inst, unsigned N) const {
376 addMemOperands(Inst, N);
379 void addMemOperands(MCInst &Inst, unsigned N) const {
380 assert((N == 5) && "Invalid number of operands!");
381 Inst.addOperand(MCOperand::CreateReg(getMemBaseReg()));
382 Inst.addOperand(MCOperand::CreateImm(getMemScale()));
383 Inst.addOperand(MCOperand::CreateReg(getMemIndexReg()));
384 addExpr(Inst, getMemDisp());
385 Inst.addOperand(MCOperand::CreateReg(getMemSegReg()));
388 void addAbsMemOperands(MCInst &Inst, unsigned N) const {
389 assert((N == 1) && "Invalid number of operands!");
390 Inst.addOperand(MCOperand::CreateExpr(getMemDisp()));
393 static X86Operand *CreateToken(StringRef Str, SMLoc Loc) {
394 SMLoc EndLoc = SMLoc::getFromPointer(Loc.getPointer() + Str.size() - 1);
395 X86Operand *Res = new X86Operand(Token, Loc, EndLoc);
396 Res->Tok.Data = Str.data();
397 Res->Tok.Length = Str.size();
401 static X86Operand *CreateReg(unsigned RegNo, SMLoc StartLoc, SMLoc EndLoc) {
402 X86Operand *Res = new X86Operand(Register, StartLoc, EndLoc);
403 Res->Reg.RegNo = RegNo;
407 static X86Operand *CreateImm(const MCExpr *Val, SMLoc StartLoc, SMLoc EndLoc){
408 X86Operand *Res = new X86Operand(Immediate, StartLoc, EndLoc);
413 /// Create an absolute memory operand.
414 static X86Operand *CreateMem(const MCExpr *Disp, SMLoc StartLoc,
415 SMLoc EndLoc, unsigned Size = 0) {
416 X86Operand *Res = new X86Operand(Memory, StartLoc, EndLoc);
418 Res->Mem.Disp = Disp;
419 Res->Mem.BaseReg = 0;
420 Res->Mem.IndexReg = 0;
422 Res->Mem.Size = Size;
426 /// Create a generalized memory operand.
427 static X86Operand *CreateMem(unsigned SegReg, const MCExpr *Disp,
428 unsigned BaseReg, unsigned IndexReg,
429 unsigned Scale, SMLoc StartLoc, SMLoc EndLoc,
431 // We should never just have a displacement, that should be parsed as an
432 // absolute memory operand.
433 assert((SegReg || BaseReg || IndexReg) && "Invalid memory operand!");
435 // The scale should always be one of {1,2,4,8}.
436 assert(((Scale == 1 || Scale == 2 || Scale == 4 || Scale == 8)) &&
438 X86Operand *Res = new X86Operand(Memory, StartLoc, EndLoc);
439 Res->Mem.SegReg = SegReg;
440 Res->Mem.Disp = Disp;
441 Res->Mem.BaseReg = BaseReg;
442 Res->Mem.IndexReg = IndexReg;
443 Res->Mem.Scale = Scale;
444 Res->Mem.Size = Size;
449 } // end anonymous namespace.
451 bool X86AsmParser::isSrcOp(X86Operand &Op) {
452 unsigned basereg = is64BitMode() ? X86::RSI : X86::ESI;
454 return (Op.isMem() &&
455 (Op.Mem.SegReg == 0 || Op.Mem.SegReg == X86::DS) &&
456 isa<MCConstantExpr>(Op.Mem.Disp) &&
457 cast<MCConstantExpr>(Op.Mem.Disp)->getValue() == 0 &&
458 Op.Mem.BaseReg == basereg && Op.Mem.IndexReg == 0);
461 bool X86AsmParser::isDstOp(X86Operand &Op) {
462 unsigned basereg = is64BitMode() ? X86::RDI : X86::EDI;
464 return Op.isMem() && Op.Mem.SegReg == X86::ES &&
465 isa<MCConstantExpr>(Op.Mem.Disp) &&
466 cast<MCConstantExpr>(Op.Mem.Disp)->getValue() == 0 &&
467 Op.Mem.BaseReg == basereg && Op.Mem.IndexReg == 0;
470 bool X86AsmParser::ParseRegister(unsigned &RegNo,
471 SMLoc &StartLoc, SMLoc &EndLoc) {
473 const AsmToken &TokPercent = Parser.getTok();
474 if (!getParser().getAssemblerDialect()) {
475 assert(TokPercent.is(AsmToken::Percent) && "Invalid token kind!");
476 StartLoc = TokPercent.getLoc();
477 Parser.Lex(); // Eat percent token.
480 const AsmToken &Tok = Parser.getTok();
481 if (Tok.isNot(AsmToken::Identifier))
482 return Error(StartLoc, "invalid register name",
483 SMRange(StartLoc, Tok.getEndLoc()));
485 RegNo = MatchRegisterName(Tok.getString());
487 // If the match failed, try the register name as lowercase.
489 RegNo = MatchRegisterName(Tok.getString().lower());
491 if (!is64BitMode()) {
492 // FIXME: This should be done using Requires<In32BitMode> and
493 // Requires<In64BitMode> so "eiz" usage in 64-bit instructions can be also
495 // FIXME: Check AH, CH, DH, BH cannot be used in an instruction requiring a
497 if (RegNo == X86::RIZ ||
498 X86MCRegisterClasses[X86::GR64RegClassID].contains(RegNo) ||
499 X86II::isX86_64NonExtLowByteReg(RegNo) ||
500 X86II::isX86_64ExtendedReg(RegNo))
501 return Error(StartLoc, "register %"
502 + Tok.getString() + " is only available in 64-bit mode",
503 SMRange(StartLoc, Tok.getEndLoc()));
506 // Parse "%st" as "%st(0)" and "%st(1)", which is multiple tokens.
507 if (RegNo == 0 && (Tok.getString() == "st" || Tok.getString() == "ST")) {
509 EndLoc = Tok.getLoc();
510 Parser.Lex(); // Eat 'st'
512 // Check to see if we have '(4)' after %st.
513 if (getLexer().isNot(AsmToken::LParen))
518 const AsmToken &IntTok = Parser.getTok();
519 if (IntTok.isNot(AsmToken::Integer))
520 return Error(IntTok.getLoc(), "expected stack index");
521 switch (IntTok.getIntVal()) {
522 case 0: RegNo = X86::ST0; break;
523 case 1: RegNo = X86::ST1; break;
524 case 2: RegNo = X86::ST2; break;
525 case 3: RegNo = X86::ST3; break;
526 case 4: RegNo = X86::ST4; break;
527 case 5: RegNo = X86::ST5; break;
528 case 6: RegNo = X86::ST6; break;
529 case 7: RegNo = X86::ST7; break;
530 default: return Error(IntTok.getLoc(), "invalid stack index");
533 if (getParser().Lex().isNot(AsmToken::RParen))
534 return Error(Parser.getTok().getLoc(), "expected ')'");
536 EndLoc = Tok.getLoc();
537 Parser.Lex(); // Eat ')'
541 // If this is "db[0-7]", match it as an alias
543 if (RegNo == 0 && Tok.getString().size() == 3 &&
544 Tok.getString().startswith("db")) {
545 switch (Tok.getString()[2]) {
546 case '0': RegNo = X86::DR0; break;
547 case '1': RegNo = X86::DR1; break;
548 case '2': RegNo = X86::DR2; break;
549 case '3': RegNo = X86::DR3; break;
550 case '4': RegNo = X86::DR4; break;
551 case '5': RegNo = X86::DR5; break;
552 case '6': RegNo = X86::DR6; break;
553 case '7': RegNo = X86::DR7; break;
557 EndLoc = Tok.getLoc();
558 Parser.Lex(); // Eat it.
564 return Error(StartLoc, "invalid register name",
565 SMRange(StartLoc, Tok.getEndLoc()));
567 EndLoc = Tok.getEndLoc();
568 Parser.Lex(); // Eat identifier token.
572 X86Operand *X86AsmParser::ParseOperand() {
573 if (getParser().getAssemblerDialect())
574 return ParseIntelOperand();
575 return ParseATTOperand();
578 /// getIntelRegister - If this is an intel register operand
579 /// then return register number, otherwise return 0;
580 static unsigned getIntelRegisterOperand(StringRef Str) {
581 unsigned RegNo = MatchRegisterName(Str);
582 // If the match failed, try the register name as lowercase.
584 RegNo = MatchRegisterName(Str.lower());
588 /// getIntelMemOperandSize - Return intel memory operand size.
589 static unsigned getIntelMemOperandSize(StringRef OpStr) {
591 if (OpStr == "BYTE") Size = 8;
592 if (OpStr == "WORD") Size = 16;
593 if (OpStr == "DWORD") Size = 32;
594 if (OpStr == "QWORD") Size = 64;
595 if (OpStr == "XWORD") Size = 80;
596 if (OpStr == "XMMWORD") Size = 128;
597 if (OpStr == "YMMWORD") Size = 256;
601 X86Operand *X86AsmParser::ParseIntelBracExpression(unsigned Size) {
602 unsigned SegReg = 0, BaseReg = 0, IndexReg = 0, Scale = 1;
603 const AsmToken &Tok = Parser.getTok();
604 SMLoc Start = Parser.getTok().getLoc(), End;
606 const MCExpr *Disp = MCConstantExpr::Create(0, getParser().getContext());
607 // Parse [ BaseReg + Scale*IndexReg + Disp ] or [ symbol ]
610 if (getLexer().isNot(AsmToken::LBrac))
611 return ErrorOperand(Start, "Expected '[' token!");
614 if (getLexer().is(AsmToken::Identifier)) {
616 BaseReg = getIntelRegisterOperand(Tok.getString());
620 // Handle '[' 'symbol' ']'
621 const MCExpr *Disp = MCConstantExpr::Create(0, getParser().getContext());
622 if (getParser().ParseExpression(Disp, End)) return 0;
623 if (getLexer().isNot(AsmToken::RBrac))
624 return ErrorOperand(Start, "Expected ']' token!");
626 return X86Operand::CreateMem(Disp, Start, End, Size);
628 } else if (getLexer().is(AsmToken::Integer)) {
629 // Handle '[' number ']'
630 const MCExpr *Disp = MCConstantExpr::Create(0, getParser().getContext());
631 if (getParser().ParseExpression(Disp, End)) return 0;
632 if (getLexer().isNot(AsmToken::RBrac))
633 return ErrorOperand(Start, "Expected ']' token!");
635 return X86Operand::CreateMem(Disp, Start, End, Size);
638 if (getLexer().is(AsmToken::Plus) || getLexer().is(AsmToken::Minus)) {
639 bool isPlus = getLexer().is(AsmToken::Plus);
641 SMLoc PlusLoc = Parser.getTok().getLoc();
642 if (getLexer().is(AsmToken::Integer)) {
643 int64_t Val = Parser.getTok().getIntVal();
645 if (getLexer().is(AsmToken::Star)) {
647 SMLoc IdxRegLoc = Parser.getTok().getLoc();
648 IndexReg = getIntelRegisterOperand(Parser.getTok().getString());
649 if (!IndexReg) return ErrorOperand(IdxRegLoc, "Expected register");
650 Parser.Lex(); // Eat register
652 } else if (getLexer().is(AsmToken::RBrac)) {
653 const MCExpr *ValExpr = MCConstantExpr::Create(Val, getContext());
654 Disp = isPlus ? ValExpr : MCConstantExpr::Create(0-Val, getContext());
656 return ErrorOperand(PlusLoc, "unexpected token after +");
657 } else if (getLexer().is(AsmToken::Identifier)) {
658 IndexReg = getIntelRegisterOperand(Tok.getString());
664 if (getLexer().isNot(AsmToken::RBrac))
665 if (getParser().ParseExpression(Disp, End)) return 0;
667 End = Parser.getTok().getLoc();
668 if (getLexer().isNot(AsmToken::RBrac))
669 return ErrorOperand(End, "expected ']' token!");
671 End = Parser.getTok().getLoc();
672 return X86Operand::CreateMem(SegReg, Disp, BaseReg, IndexReg, Scale,
676 /// ParseIntelMemOperand - Parse intel style memory operand.
677 X86Operand *X86AsmParser::ParseIntelMemOperand() {
678 const AsmToken &Tok = Parser.getTok();
679 SMLoc Start = Parser.getTok().getLoc(), End;
681 unsigned Size = getIntelMemOperandSize(Tok.getString());
684 assert (Tok.getString() == "PTR" && "Unexpected token!");
688 if (getLexer().is(AsmToken::LBrac))
689 return ParseIntelBracExpression(Size);
691 const MCExpr *Disp = MCConstantExpr::Create(0, getParser().getContext());
692 if (getParser().ParseExpression(Disp, End)) return 0;
693 return X86Operand::CreateMem(Disp, Start, End, Size);
696 X86Operand *X86AsmParser::ParseIntelOperand() {
697 StringRef TokenString = Parser.getTok().getString();
698 SMLoc Start = Parser.getTok().getLoc(), End;
701 if (getLexer().is(AsmToken::Integer) || getLexer().is(AsmToken::Real) ||
702 getLexer().is(AsmToken::Minus)) {
704 if (!getParser().ParseExpression(Val, End)) {
705 End = Parser.getTok().getLoc();
706 return X86Operand::CreateImm(Val, Start, End);
711 if(unsigned RegNo = getIntelRegisterOperand(TokenString)) {
713 End = Parser.getTok().getLoc();
714 return X86Operand::CreateReg(RegNo, Start, End);
718 return ParseIntelMemOperand();
721 X86Operand *X86AsmParser::ParseATTOperand() {
722 switch (getLexer().getKind()) {
724 // Parse a memory operand with no segment register.
725 return ParseMemOperand(0, Parser.getTok().getLoc());
726 case AsmToken::Percent: {
727 // Read the register.
730 if (ParseRegister(RegNo, Start, End)) return 0;
731 if (RegNo == X86::EIZ || RegNo == X86::RIZ) {
732 Error(Start, "%eiz and %riz can only be used as index registers",
733 SMRange(Start, End));
737 // If this is a segment register followed by a ':', then this is the start
738 // of a memory reference, otherwise this is a normal register reference.
739 if (getLexer().isNot(AsmToken::Colon))
740 return X86Operand::CreateReg(RegNo, Start, End);
743 getParser().Lex(); // Eat the colon.
744 return ParseMemOperand(RegNo, Start);
746 case AsmToken::Dollar: {
748 SMLoc Start = Parser.getTok().getLoc(), End;
751 if (getParser().ParseExpression(Val, End))
753 return X86Operand::CreateImm(Val, Start, End);
758 /// ParseMemOperand: segment: disp(basereg, indexreg, scale). The '%ds:' prefix
759 /// has already been parsed if present.
760 X86Operand *X86AsmParser::ParseMemOperand(unsigned SegReg, SMLoc MemStart) {
762 // We have to disambiguate a parenthesized expression "(4+5)" from the start
763 // of a memory operand with a missing displacement "(%ebx)" or "(,%eax)". The
764 // only way to do this without lookahead is to eat the '(' and see what is
766 const MCExpr *Disp = MCConstantExpr::Create(0, getParser().getContext());
767 if (getLexer().isNot(AsmToken::LParen)) {
769 if (getParser().ParseExpression(Disp, ExprEnd)) return 0;
771 // After parsing the base expression we could either have a parenthesized
772 // memory address or not. If not, return now. If so, eat the (.
773 if (getLexer().isNot(AsmToken::LParen)) {
774 // Unless we have a segment register, treat this as an immediate.
776 return X86Operand::CreateMem(Disp, MemStart, ExprEnd);
777 return X86Operand::CreateMem(SegReg, Disp, 0, 0, 1, MemStart, ExprEnd);
783 // Okay, we have a '('. We don't know if this is an expression or not, but
784 // so we have to eat the ( to see beyond it.
785 SMLoc LParenLoc = Parser.getTok().getLoc();
786 Parser.Lex(); // Eat the '('.
788 if (getLexer().is(AsmToken::Percent) || getLexer().is(AsmToken::Comma)) {
789 // Nothing to do here, fall into the code below with the '(' part of the
790 // memory operand consumed.
794 // It must be an parenthesized expression, parse it now.
795 if (getParser().ParseParenExpression(Disp, ExprEnd))
798 // After parsing the base expression we could either have a parenthesized
799 // memory address or not. If not, return now. If so, eat the (.
800 if (getLexer().isNot(AsmToken::LParen)) {
801 // Unless we have a segment register, treat this as an immediate.
803 return X86Operand::CreateMem(Disp, LParenLoc, ExprEnd);
804 return X86Operand::CreateMem(SegReg, Disp, 0, 0, 1, MemStart, ExprEnd);
812 // If we reached here, then we just ate the ( of the memory operand. Process
813 // the rest of the memory operand.
814 unsigned BaseReg = 0, IndexReg = 0, Scale = 1;
816 if (getLexer().is(AsmToken::Percent)) {
817 SMLoc StartLoc, EndLoc;
818 if (ParseRegister(BaseReg, StartLoc, EndLoc)) return 0;
819 if (BaseReg == X86::EIZ || BaseReg == X86::RIZ) {
820 Error(StartLoc, "eiz and riz can only be used as index registers",
821 SMRange(StartLoc, EndLoc));
826 if (getLexer().is(AsmToken::Comma)) {
827 Parser.Lex(); // Eat the comma.
829 // Following the comma we should have either an index register, or a scale
830 // value. We don't support the later form, but we want to parse it
833 // Not that even though it would be completely consistent to support syntax
834 // like "1(%eax,,1)", the assembler doesn't. Use "eiz" or "riz" for this.
835 if (getLexer().is(AsmToken::Percent)) {
837 if (ParseRegister(IndexReg, L, L)) return 0;
839 if (getLexer().isNot(AsmToken::RParen)) {
840 // Parse the scale amount:
841 // ::= ',' [scale-expression]
842 if (getLexer().isNot(AsmToken::Comma)) {
843 Error(Parser.getTok().getLoc(),
844 "expected comma in scale expression");
847 Parser.Lex(); // Eat the comma.
849 if (getLexer().isNot(AsmToken::RParen)) {
850 SMLoc Loc = Parser.getTok().getLoc();
853 if (getParser().ParseAbsoluteExpression(ScaleVal))
856 // Validate the scale amount.
857 if (ScaleVal != 1 && ScaleVal != 2 && ScaleVal != 4 && ScaleVal != 8){
858 Error(Loc, "scale factor in address must be 1, 2, 4 or 8");
861 Scale = (unsigned)ScaleVal;
864 } else if (getLexer().isNot(AsmToken::RParen)) {
865 // A scale amount without an index is ignored.
867 SMLoc Loc = Parser.getTok().getLoc();
870 if (getParser().ParseAbsoluteExpression(Value))
874 Warning(Loc, "scale factor without index register is ignored");
879 // Ok, we've eaten the memory operand, verify we have a ')' and eat it too.
880 if (getLexer().isNot(AsmToken::RParen)) {
881 Error(Parser.getTok().getLoc(), "unexpected token in memory operand");
884 SMLoc MemEnd = Parser.getTok().getLoc();
885 Parser.Lex(); // Eat the ')'.
887 return X86Operand::CreateMem(SegReg, Disp, BaseReg, IndexReg, Scale,
892 ParseInstruction(StringRef Name, SMLoc NameLoc,
893 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
894 StringRef PatchedName = Name;
896 // FIXME: Hack to recognize setneb as setne.
897 if (PatchedName.startswith("set") && PatchedName.endswith("b") &&
898 PatchedName != "setb" && PatchedName != "setnb")
899 PatchedName = PatchedName.substr(0, Name.size()-1);
901 // FIXME: Hack to recognize cmp<comparison code>{ss,sd,ps,pd}.
902 const MCExpr *ExtraImmOp = 0;
903 if ((PatchedName.startswith("cmp") || PatchedName.startswith("vcmp")) &&
904 (PatchedName.endswith("ss") || PatchedName.endswith("sd") ||
905 PatchedName.endswith("ps") || PatchedName.endswith("pd"))) {
906 bool IsVCMP = PatchedName.startswith("vcmp");
907 unsigned SSECCIdx = IsVCMP ? 4 : 3;
908 unsigned SSEComparisonCode = StringSwitch<unsigned>(
909 PatchedName.slice(SSECCIdx, PatchedName.size() - 2))
922 .Case("neq_oq", 0x0C)
929 .Case("unord_s", 0x13)
930 .Case("neq_us", 0x14)
931 .Case("nlt_uq", 0x15)
932 .Case("nle_uq", 0x16)
935 .Case("nge_uq", 0x19)
936 .Case("ngt_uq", 0x1A)
937 .Case("false_os", 0x1B)
938 .Case("neq_os", 0x1C)
941 .Case("true_us", 0x1F)
943 if (SSEComparisonCode != ~0U) {
944 ExtraImmOp = MCConstantExpr::Create(SSEComparisonCode,
945 getParser().getContext());
946 if (PatchedName.endswith("ss")) {
947 PatchedName = IsVCMP ? "vcmpss" : "cmpss";
948 } else if (PatchedName.endswith("sd")) {
949 PatchedName = IsVCMP ? "vcmpsd" : "cmpsd";
950 } else if (PatchedName.endswith("ps")) {
951 PatchedName = IsVCMP ? "vcmpps" : "cmpps";
953 assert(PatchedName.endswith("pd") && "Unexpected mnemonic!");
954 PatchedName = IsVCMP ? "vcmppd" : "cmppd";
959 Operands.push_back(X86Operand::CreateToken(PatchedName, NameLoc));
962 Operands.push_back(X86Operand::CreateImm(ExtraImmOp, NameLoc, NameLoc));
965 // Determine whether this is an instruction prefix.
967 Name == "lock" || Name == "rep" ||
968 Name == "repe" || Name == "repz" ||
969 Name == "repne" || Name == "repnz" ||
970 Name == "rex64" || Name == "data16";
973 // This does the actual operand parsing. Don't parse any more if we have a
974 // prefix juxtaposed with an operation like "lock incl 4(%rax)", because we
975 // just want to parse the "lock" as the first instruction and the "incl" as
977 if (getLexer().isNot(AsmToken::EndOfStatement) && !isPrefix) {
979 // Parse '*' modifier.
980 if (getLexer().is(AsmToken::Star)) {
981 SMLoc Loc = Parser.getTok().getLoc();
982 Operands.push_back(X86Operand::CreateToken("*", Loc));
983 Parser.Lex(); // Eat the star.
986 // Read the first operand.
987 if (X86Operand *Op = ParseOperand())
988 Operands.push_back(Op);
990 Parser.EatToEndOfStatement();
994 while (getLexer().is(AsmToken::Comma)) {
995 Parser.Lex(); // Eat the comma.
997 // Parse and remember the operand.
998 if (X86Operand *Op = ParseOperand())
999 Operands.push_back(Op);
1001 Parser.EatToEndOfStatement();
1006 if (getLexer().isNot(AsmToken::EndOfStatement)) {
1007 SMLoc Loc = getLexer().getLoc();
1008 Parser.EatToEndOfStatement();
1009 return Error(Loc, "unexpected token in argument list");
1013 if (getLexer().is(AsmToken::EndOfStatement))
1014 Parser.Lex(); // Consume the EndOfStatement
1015 else if (isPrefix && getLexer().is(AsmToken::Slash))
1016 Parser.Lex(); // Consume the prefix separator Slash
1018 // This is a terrible hack to handle "out[bwl]? %al, (%dx)" ->
1019 // "outb %al, %dx". Out doesn't take a memory form, but this is a widely
1020 // documented form in various unofficial manuals, so a lot of code uses it.
1021 if ((Name == "outb" || Name == "outw" || Name == "outl" || Name == "out") &&
1022 Operands.size() == 3) {
1023 X86Operand &Op = *(X86Operand*)Operands.back();
1024 if (Op.isMem() && Op.Mem.SegReg == 0 &&
1025 isa<MCConstantExpr>(Op.Mem.Disp) &&
1026 cast<MCConstantExpr>(Op.Mem.Disp)->getValue() == 0 &&
1027 Op.Mem.BaseReg == MatchRegisterName("dx") && Op.Mem.IndexReg == 0) {
1028 SMLoc Loc = Op.getEndLoc();
1029 Operands.back() = X86Operand::CreateReg(Op.Mem.BaseReg, Loc, Loc);
1033 // Same hack for "in[bwl]? (%dx), %al" -> "inb %dx, %al".
1034 if ((Name == "inb" || Name == "inw" || Name == "inl" || Name == "in") &&
1035 Operands.size() == 3) {
1036 X86Operand &Op = *(X86Operand*)Operands.begin()[1];
1037 if (Op.isMem() && Op.Mem.SegReg == 0 &&
1038 isa<MCConstantExpr>(Op.Mem.Disp) &&
1039 cast<MCConstantExpr>(Op.Mem.Disp)->getValue() == 0 &&
1040 Op.Mem.BaseReg == MatchRegisterName("dx") && Op.Mem.IndexReg == 0) {
1041 SMLoc Loc = Op.getEndLoc();
1042 Operands.begin()[1] = X86Operand::CreateReg(Op.Mem.BaseReg, Loc, Loc);
1046 // Transform "ins[bwl] %dx, %es:(%edi)" into "ins[bwl]"
1047 if (Name.startswith("ins") && Operands.size() == 3 &&
1048 (Name == "insb" || Name == "insw" || Name == "insl")) {
1049 X86Operand &Op = *(X86Operand*)Operands.begin()[1];
1050 X86Operand &Op2 = *(X86Operand*)Operands.begin()[2];
1051 if (Op.isReg() && Op.getReg() == X86::DX && isDstOp(Op2)) {
1052 Operands.pop_back();
1053 Operands.pop_back();
1059 // Transform "outs[bwl] %ds:(%esi), %dx" into "out[bwl]"
1060 if (Name.startswith("outs") && Operands.size() == 3 &&
1061 (Name == "outsb" || Name == "outsw" || Name == "outsl")) {
1062 X86Operand &Op = *(X86Operand*)Operands.begin()[1];
1063 X86Operand &Op2 = *(X86Operand*)Operands.begin()[2];
1064 if (isSrcOp(Op) && Op2.isReg() && Op2.getReg() == X86::DX) {
1065 Operands.pop_back();
1066 Operands.pop_back();
1072 // Transform "movs[bwl] %ds:(%esi), %es:(%edi)" into "movs[bwl]"
1073 if (Name.startswith("movs") && Operands.size() == 3 &&
1074 (Name == "movsb" || Name == "movsw" || Name == "movsl" ||
1075 (is64BitMode() && Name == "movsq"))) {
1076 X86Operand &Op = *(X86Operand*)Operands.begin()[1];
1077 X86Operand &Op2 = *(X86Operand*)Operands.begin()[2];
1078 if (isSrcOp(Op) && isDstOp(Op2)) {
1079 Operands.pop_back();
1080 Operands.pop_back();
1085 // Transform "lods[bwl] %ds:(%esi),{%al,%ax,%eax,%rax}" into "lods[bwl]"
1086 if (Name.startswith("lods") && Operands.size() == 3 &&
1087 (Name == "lods" || Name == "lodsb" || Name == "lodsw" ||
1088 Name == "lodsl" || (is64BitMode() && Name == "lodsq"))) {
1089 X86Operand *Op1 = static_cast<X86Operand*>(Operands[1]);
1090 X86Operand *Op2 = static_cast<X86Operand*>(Operands[2]);
1091 if (isSrcOp(*Op1) && Op2->isReg()) {
1093 unsigned reg = Op2->getReg();
1094 bool isLods = Name == "lods";
1095 if (reg == X86::AL && (isLods || Name == "lodsb"))
1097 else if (reg == X86::AX && (isLods || Name == "lodsw"))
1099 else if (reg == X86::EAX && (isLods || Name == "lodsl"))
1101 else if (reg == X86::RAX && (isLods || Name == "lodsq"))
1106 Operands.pop_back();
1107 Operands.pop_back();
1111 static_cast<X86Operand*>(Operands[0])->setTokenValue(ins);
1115 // Transform "stos[bwl] {%al,%ax,%eax,%rax},%es:(%edi)" into "stos[bwl]"
1116 if (Name.startswith("stos") && Operands.size() == 3 &&
1117 (Name == "stos" || Name == "stosb" || Name == "stosw" ||
1118 Name == "stosl" || (is64BitMode() && Name == "stosq"))) {
1119 X86Operand *Op1 = static_cast<X86Operand*>(Operands[1]);
1120 X86Operand *Op2 = static_cast<X86Operand*>(Operands[2]);
1121 if (isDstOp(*Op2) && Op1->isReg()) {
1123 unsigned reg = Op1->getReg();
1124 bool isStos = Name == "stos";
1125 if (reg == X86::AL && (isStos || Name == "stosb"))
1127 else if (reg == X86::AX && (isStos || Name == "stosw"))
1129 else if (reg == X86::EAX && (isStos || Name == "stosl"))
1131 else if (reg == X86::RAX && (isStos || Name == "stosq"))
1136 Operands.pop_back();
1137 Operands.pop_back();
1141 static_cast<X86Operand*>(Operands[0])->setTokenValue(ins);
1146 // FIXME: Hack to handle recognize s{hr,ar,hl} $1, <op>. Canonicalize to
1148 if ((Name.startswith("shr") || Name.startswith("sar") ||
1149 Name.startswith("shl") || Name.startswith("sal") ||
1150 Name.startswith("rcl") || Name.startswith("rcr") ||
1151 Name.startswith("rol") || Name.startswith("ror")) &&
1152 Operands.size() == 3) {
1153 X86Operand *Op1 = static_cast<X86Operand*>(Operands[1]);
1154 if (Op1->isImm() && isa<MCConstantExpr>(Op1->getImm()) &&
1155 cast<MCConstantExpr>(Op1->getImm())->getValue() == 1) {
1157 Operands.erase(Operands.begin() + 1);
1161 // Transforms "int $3" into "int3" as a size optimization. We can't write an
1162 // instalias with an immediate operand yet.
1163 if (Name == "int" && Operands.size() == 2) {
1164 X86Operand *Op1 = static_cast<X86Operand*>(Operands[1]);
1165 if (Op1->isImm() && isa<MCConstantExpr>(Op1->getImm()) &&
1166 cast<MCConstantExpr>(Op1->getImm())->getValue() == 3) {
1168 Operands.erase(Operands.begin() + 1);
1169 static_cast<X86Operand*>(Operands[0])->setTokenValue("int3");
1177 processInstruction(MCInst &Inst,
1178 const SmallVectorImpl<MCParsedAsmOperand*> &Ops) {
1179 switch (Inst.getOpcode()) {
1180 default: return false;
1181 case X86::AND16i16: {
1182 if (!Inst.getOperand(0).isImm() ||
1183 !isImmSExti16i8Value(Inst.getOperand(0).getImm()))
1187 TmpInst.setOpcode(X86::AND16ri8);
1188 TmpInst.addOperand(MCOperand::CreateReg(X86::AX));
1189 TmpInst.addOperand(MCOperand::CreateReg(X86::AX));
1190 TmpInst.addOperand(Inst.getOperand(0));
1194 case X86::AND32i32: {
1195 if (!Inst.getOperand(0).isImm() ||
1196 !isImmSExti32i8Value(Inst.getOperand(0).getImm()))
1200 TmpInst.setOpcode(X86::AND32ri8);
1201 TmpInst.addOperand(MCOperand::CreateReg(X86::EAX));
1202 TmpInst.addOperand(MCOperand::CreateReg(X86::EAX));
1203 TmpInst.addOperand(Inst.getOperand(0));
1207 case X86::AND64i32: {
1208 if (!Inst.getOperand(0).isImm() ||
1209 !isImmSExti64i8Value(Inst.getOperand(0).getImm()))
1213 TmpInst.setOpcode(X86::AND64ri8);
1214 TmpInst.addOperand(MCOperand::CreateReg(X86::RAX));
1215 TmpInst.addOperand(MCOperand::CreateReg(X86::RAX));
1216 TmpInst.addOperand(Inst.getOperand(0));
1220 case X86::XOR16i16: {
1221 if (!Inst.getOperand(0).isImm() ||
1222 !isImmSExti16i8Value(Inst.getOperand(0).getImm()))
1226 TmpInst.setOpcode(X86::XOR16ri8);
1227 TmpInst.addOperand(MCOperand::CreateReg(X86::AX));
1228 TmpInst.addOperand(MCOperand::CreateReg(X86::AX));
1229 TmpInst.addOperand(Inst.getOperand(0));
1233 case X86::XOR32i32: {
1234 if (!Inst.getOperand(0).isImm() ||
1235 !isImmSExti32i8Value(Inst.getOperand(0).getImm()))
1239 TmpInst.setOpcode(X86::XOR32ri8);
1240 TmpInst.addOperand(MCOperand::CreateReg(X86::EAX));
1241 TmpInst.addOperand(MCOperand::CreateReg(X86::EAX));
1242 TmpInst.addOperand(Inst.getOperand(0));
1246 case X86::XOR64i32: {
1247 if (!Inst.getOperand(0).isImm() ||
1248 !isImmSExti64i8Value(Inst.getOperand(0).getImm()))
1252 TmpInst.setOpcode(X86::XOR64ri8);
1253 TmpInst.addOperand(MCOperand::CreateReg(X86::RAX));
1254 TmpInst.addOperand(MCOperand::CreateReg(X86::RAX));
1255 TmpInst.addOperand(Inst.getOperand(0));
1259 case X86::OR16i16: {
1260 if (!Inst.getOperand(0).isImm() ||
1261 !isImmSExti16i8Value(Inst.getOperand(0).getImm()))
1265 TmpInst.setOpcode(X86::OR16ri8);
1266 TmpInst.addOperand(MCOperand::CreateReg(X86::AX));
1267 TmpInst.addOperand(MCOperand::CreateReg(X86::AX));
1268 TmpInst.addOperand(Inst.getOperand(0));
1272 case X86::OR32i32: {
1273 if (!Inst.getOperand(0).isImm() ||
1274 !isImmSExti32i8Value(Inst.getOperand(0).getImm()))
1278 TmpInst.setOpcode(X86::OR32ri8);
1279 TmpInst.addOperand(MCOperand::CreateReg(X86::EAX));
1280 TmpInst.addOperand(MCOperand::CreateReg(X86::EAX));
1281 TmpInst.addOperand(Inst.getOperand(0));
1285 case X86::OR64i32: {
1286 if (!Inst.getOperand(0).isImm() ||
1287 !isImmSExti64i8Value(Inst.getOperand(0).getImm()))
1291 TmpInst.setOpcode(X86::OR64ri8);
1292 TmpInst.addOperand(MCOperand::CreateReg(X86::RAX));
1293 TmpInst.addOperand(MCOperand::CreateReg(X86::RAX));
1294 TmpInst.addOperand(Inst.getOperand(0));
1298 case X86::CMP16i16: {
1299 if (!Inst.getOperand(0).isImm() ||
1300 !isImmSExti16i8Value(Inst.getOperand(0).getImm()))
1304 TmpInst.setOpcode(X86::CMP16ri8);
1305 TmpInst.addOperand(MCOperand::CreateReg(X86::AX));
1306 TmpInst.addOperand(Inst.getOperand(0));
1310 case X86::CMP32i32: {
1311 if (!Inst.getOperand(0).isImm() ||
1312 !isImmSExti32i8Value(Inst.getOperand(0).getImm()))
1316 TmpInst.setOpcode(X86::CMP32ri8);
1317 TmpInst.addOperand(MCOperand::CreateReg(X86::EAX));
1318 TmpInst.addOperand(Inst.getOperand(0));
1322 case X86::CMP64i32: {
1323 if (!Inst.getOperand(0).isImm() ||
1324 !isImmSExti64i8Value(Inst.getOperand(0).getImm()))
1328 TmpInst.setOpcode(X86::CMP64ri8);
1329 TmpInst.addOperand(MCOperand::CreateReg(X86::RAX));
1330 TmpInst.addOperand(Inst.getOperand(0));
1334 case X86::ADD16i16: {
1335 if (!Inst.getOperand(0).isImm() ||
1336 !isImmSExti16i8Value(Inst.getOperand(0).getImm()))
1340 TmpInst.setOpcode(X86::ADD16ri8);
1341 TmpInst.addOperand(MCOperand::CreateReg(X86::AX));
1342 TmpInst.addOperand(MCOperand::CreateReg(X86::AX));
1343 TmpInst.addOperand(Inst.getOperand(0));
1347 case X86::ADD32i32: {
1348 if (!Inst.getOperand(0).isImm() ||
1349 !isImmSExti32i8Value(Inst.getOperand(0).getImm()))
1353 TmpInst.setOpcode(X86::ADD32ri8);
1354 TmpInst.addOperand(MCOperand::CreateReg(X86::EAX));
1355 TmpInst.addOperand(MCOperand::CreateReg(X86::EAX));
1356 TmpInst.addOperand(Inst.getOperand(0));
1360 case X86::ADD64i32: {
1361 if (!Inst.getOperand(0).isImm() ||
1362 !isImmSExti64i8Value(Inst.getOperand(0).getImm()))
1366 TmpInst.setOpcode(X86::ADD64ri8);
1367 TmpInst.addOperand(MCOperand::CreateReg(X86::RAX));
1368 TmpInst.addOperand(MCOperand::CreateReg(X86::RAX));
1369 TmpInst.addOperand(Inst.getOperand(0));
1373 case X86::SUB16i16: {
1374 if (!Inst.getOperand(0).isImm() ||
1375 !isImmSExti16i8Value(Inst.getOperand(0).getImm()))
1379 TmpInst.setOpcode(X86::SUB16ri8);
1380 TmpInst.addOperand(MCOperand::CreateReg(X86::AX));
1381 TmpInst.addOperand(MCOperand::CreateReg(X86::AX));
1382 TmpInst.addOperand(Inst.getOperand(0));
1386 case X86::SUB32i32: {
1387 if (!Inst.getOperand(0).isImm() ||
1388 !isImmSExti32i8Value(Inst.getOperand(0).getImm()))
1392 TmpInst.setOpcode(X86::SUB32ri8);
1393 TmpInst.addOperand(MCOperand::CreateReg(X86::EAX));
1394 TmpInst.addOperand(MCOperand::CreateReg(X86::EAX));
1395 TmpInst.addOperand(Inst.getOperand(0));
1399 case X86::SUB64i32: {
1400 if (!Inst.getOperand(0).isImm() ||
1401 !isImmSExti64i8Value(Inst.getOperand(0).getImm()))
1405 TmpInst.setOpcode(X86::SUB64ri8);
1406 TmpInst.addOperand(MCOperand::CreateReg(X86::RAX));
1407 TmpInst.addOperand(MCOperand::CreateReg(X86::RAX));
1408 TmpInst.addOperand(Inst.getOperand(0));
1417 MatchAndEmitInstruction(SMLoc IDLoc,
1418 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
1420 assert(!Operands.empty() && "Unexpect empty operand list!");
1421 X86Operand *Op = static_cast<X86Operand*>(Operands[0]);
1422 assert(Op->isToken() && "Leading operand should always be a mnemonic!");
1424 // First, handle aliases that expand to multiple instructions.
1425 // FIXME: This should be replaced with a real .td file alias mechanism.
1426 // Also, MatchInstructionImpl should do actually *do* the EmitInstruction
1428 if (Op->getToken() == "fstsw" || Op->getToken() == "fstcw" ||
1429 Op->getToken() == "fstsww" || Op->getToken() == "fstcww" ||
1430 Op->getToken() == "finit" || Op->getToken() == "fsave" ||
1431 Op->getToken() == "fstenv" || Op->getToken() == "fclex") {
1433 Inst.setOpcode(X86::WAIT);
1434 Out.EmitInstruction(Inst);
1437 StringSwitch<const char*>(Op->getToken())
1438 .Case("finit", "fninit")
1439 .Case("fsave", "fnsave")
1440 .Case("fstcw", "fnstcw")
1441 .Case("fstcww", "fnstcw")
1442 .Case("fstenv", "fnstenv")
1443 .Case("fstsw", "fnstsw")
1444 .Case("fstsww", "fnstsw")
1445 .Case("fclex", "fnclex")
1447 assert(Repl && "Unknown wait-prefixed instruction");
1449 Operands[0] = X86Operand::CreateToken(Repl, IDLoc);
1452 bool WasOriginallyInvalidOperand = false;
1453 unsigned OrigErrorInfo;
1456 // First, try a direct match.
1457 switch (MatchInstructionImpl(Operands, Inst, OrigErrorInfo,
1458 getParser().getAssemblerDialect())) {
1461 // Some instructions need post-processing to, for example, tweak which
1462 // encoding is selected. Loop on it while changes happen so the
1463 // individual transformations can chain off each other.
1464 while (processInstruction(Inst, Operands))
1467 Out.EmitInstruction(Inst);
1469 case Match_MissingFeature:
1470 Error(IDLoc, "instruction requires a CPU feature not currently enabled");
1472 case Match_ConversionFail:
1473 return Error(IDLoc, "unable to convert operands to instruction");
1474 case Match_InvalidOperand:
1475 WasOriginallyInvalidOperand = true;
1477 case Match_MnemonicFail:
1481 // FIXME: Ideally, we would only attempt suffix matches for things which are
1482 // valid prefixes, and we could just infer the right unambiguous
1483 // type. However, that requires substantially more matcher support than the
1486 // Change the operand to point to a temporary token.
1487 StringRef Base = Op->getToken();
1488 SmallString<16> Tmp;
1491 Op->setTokenValue(Tmp.str());
1493 // If this instruction starts with an 'f', then it is a floating point stack
1494 // instruction. These come in up to three forms for 32-bit, 64-bit, and
1495 // 80-bit floating point, which use the suffixes s,l,t respectively.
1497 // Otherwise, we assume that this may be an integer instruction, which comes
1498 // in 8/16/32/64-bit forms using the b,w,l,q suffixes respectively.
1499 const char *Suffixes = Base[0] != 'f' ? "bwlq" : "slt\0";
1501 // Check for the various suffix matches.
1502 Tmp[Base.size()] = Suffixes[0];
1503 unsigned ErrorInfoIgnore;
1504 unsigned Match1, Match2, Match3, Match4;
1506 Match1 = MatchInstructionImpl(Operands, Inst, ErrorInfoIgnore);
1507 Tmp[Base.size()] = Suffixes[1];
1508 Match2 = MatchInstructionImpl(Operands, Inst, ErrorInfoIgnore);
1509 Tmp[Base.size()] = Suffixes[2];
1510 Match3 = MatchInstructionImpl(Operands, Inst, ErrorInfoIgnore);
1511 Tmp[Base.size()] = Suffixes[3];
1512 Match4 = MatchInstructionImpl(Operands, Inst, ErrorInfoIgnore);
1514 // Restore the old token.
1515 Op->setTokenValue(Base);
1517 // If exactly one matched, then we treat that as a successful match (and the
1518 // instruction will already have been filled in correctly, since the failing
1519 // matches won't have modified it).
1520 unsigned NumSuccessfulMatches =
1521 (Match1 == Match_Success) + (Match2 == Match_Success) +
1522 (Match3 == Match_Success) + (Match4 == Match_Success);
1523 if (NumSuccessfulMatches == 1) {
1524 Out.EmitInstruction(Inst);
1528 // Otherwise, the match failed, try to produce a decent error message.
1530 // If we had multiple suffix matches, then identify this as an ambiguous
1532 if (NumSuccessfulMatches > 1) {
1534 unsigned NumMatches = 0;
1535 if (Match1 == Match_Success) MatchChars[NumMatches++] = Suffixes[0];
1536 if (Match2 == Match_Success) MatchChars[NumMatches++] = Suffixes[1];
1537 if (Match3 == Match_Success) MatchChars[NumMatches++] = Suffixes[2];
1538 if (Match4 == Match_Success) MatchChars[NumMatches++] = Suffixes[3];
1540 SmallString<126> Msg;
1541 raw_svector_ostream OS(Msg);
1542 OS << "ambiguous instructions require an explicit suffix (could be ";
1543 for (unsigned i = 0; i != NumMatches; ++i) {
1546 if (i + 1 == NumMatches)
1548 OS << "'" << Base << MatchChars[i] << "'";
1551 Error(IDLoc, OS.str());
1555 // Okay, we know that none of the variants matched successfully.
1557 // If all of the instructions reported an invalid mnemonic, then the original
1558 // mnemonic was invalid.
1559 if ((Match1 == Match_MnemonicFail) && (Match2 == Match_MnemonicFail) &&
1560 (Match3 == Match_MnemonicFail) && (Match4 == Match_MnemonicFail)) {
1561 if (!WasOriginallyInvalidOperand) {
1562 return Error(IDLoc, "invalid instruction mnemonic '" + Base + "'",
1566 // Recover location info for the operand if we know which was the problem.
1567 if (OrigErrorInfo != ~0U) {
1568 if (OrigErrorInfo >= Operands.size())
1569 return Error(IDLoc, "too few operands for instruction");
1571 X86Operand *Operand = (X86Operand*)Operands[OrigErrorInfo];
1572 if (Operand->getStartLoc().isValid()) {
1573 SMRange OperandRange = Operand->getLocRange();
1574 return Error(Operand->getStartLoc(), "invalid operand for instruction",
1579 return Error(IDLoc, "invalid operand for instruction");
1582 // If one instruction matched with a missing feature, report this as a
1584 if ((Match1 == Match_MissingFeature) + (Match2 == Match_MissingFeature) +
1585 (Match3 == Match_MissingFeature) + (Match4 == Match_MissingFeature) == 1){
1586 Error(IDLoc, "instruction requires a CPU feature not currently enabled");
1590 // If one instruction matched with an invalid operand, report this as an
1592 if ((Match1 == Match_InvalidOperand) + (Match2 == Match_InvalidOperand) +
1593 (Match3 == Match_InvalidOperand) + (Match4 == Match_InvalidOperand) == 1){
1594 Error(IDLoc, "invalid operand for instruction");
1598 // If all of these were an outright failure, report it in a useless way.
1599 Error(IDLoc, "unknown use of instruction mnemonic without a size suffix");
1604 bool X86AsmParser::ParseDirective(AsmToken DirectiveID) {
1605 StringRef IDVal = DirectiveID.getIdentifier();
1606 if (IDVal == ".word")
1607 return ParseDirectiveWord(2, DirectiveID.getLoc());
1608 else if (IDVal.startswith(".code"))
1609 return ParseDirectiveCode(IDVal, DirectiveID.getLoc());
1613 /// ParseDirectiveWord
1614 /// ::= .word [ expression (, expression)* ]
1615 bool X86AsmParser::ParseDirectiveWord(unsigned Size, SMLoc L) {
1616 if (getLexer().isNot(AsmToken::EndOfStatement)) {
1618 const MCExpr *Value;
1619 if (getParser().ParseExpression(Value))
1622 getParser().getStreamer().EmitValue(Value, Size, 0 /*addrspace*/);
1624 if (getLexer().is(AsmToken::EndOfStatement))
1627 // FIXME: Improve diagnostic.
1628 if (getLexer().isNot(AsmToken::Comma))
1629 return Error(L, "unexpected token in directive");
1638 /// ParseDirectiveCode
1639 /// ::= .code32 | .code64
1640 bool X86AsmParser::ParseDirectiveCode(StringRef IDVal, SMLoc L) {
1641 if (IDVal == ".code32") {
1643 if (is64BitMode()) {
1645 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
1647 } else if (IDVal == ".code64") {
1649 if (!is64BitMode()) {
1651 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code64);
1654 return Error(L, "unexpected directive " + IDVal);
1661 extern "C" void LLVMInitializeX86AsmLexer();
1663 // Force static initialization.
1664 extern "C" void LLVMInitializeX86AsmParser() {
1665 RegisterMCAsmParser<X86AsmParser> X(TheX86_32Target);
1666 RegisterMCAsmParser<X86AsmParser> Y(TheX86_64Target);
1667 LLVMInitializeX86AsmLexer();
1670 #define GET_REGISTER_MATCHER
1671 #define GET_MATCHER_IMPLEMENTATION
1672 #include "X86GenAsmMatcher.inc"