1 //===-- X86AsmParser.cpp - Parse X86 assembly to MCInst instructions ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "MCTargetDesc/X86BaseInfo.h"
11 #include "llvm/MC/MCTargetAsmParser.h"
12 #include "llvm/MC/MCStreamer.h"
13 #include "llvm/MC/MCExpr.h"
14 #include "llvm/MC/MCSymbol.h"
15 #include "llvm/MC/MCInst.h"
16 #include "llvm/MC/MCRegisterInfo.h"
17 #include "llvm/MC/MCSubtargetInfo.h"
18 #include "llvm/MC/MCParser/MCAsmLexer.h"
19 #include "llvm/MC/MCParser/MCAsmParser.h"
20 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
21 #include "llvm/ADT/APFloat.h"
22 #include "llvm/ADT/SmallString.h"
23 #include "llvm/ADT/SmallVector.h"
24 #include "llvm/ADT/StringSwitch.h"
25 #include "llvm/ADT/Twine.h"
26 #include "llvm/Support/SourceMgr.h"
27 #include "llvm/Support/TargetRegistry.h"
28 #include "llvm/Support/raw_ostream.h"
35 class X86AsmParser : public MCTargetAsmParser {
38 ParseInstructionInfo *InstInfo;
40 MCAsmParser &getParser() const { return Parser; }
42 MCAsmLexer &getLexer() const { return Parser.getLexer(); }
44 bool Error(SMLoc L, const Twine &Msg,
45 ArrayRef<SMRange> Ranges = ArrayRef<SMRange>(),
46 bool MatchingInlineAsm = false) {
47 if (MatchingInlineAsm) return true;
48 return Parser.Error(L, Msg, Ranges);
51 X86Operand *ErrorOperand(SMLoc Loc, StringRef Msg) {
56 X86Operand *ParseOperand();
57 X86Operand *ParseATTOperand();
58 X86Operand *ParseIntelOperand();
59 X86Operand *ParseIntelOffsetOfOperator(SMLoc StartLoc);
60 X86Operand *ParseIntelTypeOperator(SMLoc StartLoc);
61 X86Operand *ParseIntelMemOperand(unsigned SegReg, SMLoc StartLoc);
62 X86Operand *ParseIntelBracExpression(unsigned SegReg, unsigned Size);
63 X86Operand *ParseMemOperand(unsigned SegReg, SMLoc StartLoc);
65 bool ParseIntelDotOperator(const MCExpr *Disp, const MCExpr **NewDisp,
66 SmallString<64> &Err);
68 bool ParseDirectiveWord(unsigned Size, SMLoc L);
69 bool ParseDirectiveCode(StringRef IDVal, SMLoc L);
71 bool processInstruction(MCInst &Inst,
72 const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
74 bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
75 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
76 MCStreamer &Out, unsigned &ErrorInfo,
77 bool MatchingInlineAsm);
79 /// isSrcOp - Returns true if operand is either (%rsi) or %ds:%(rsi)
80 /// in 64bit mode or (%esi) or %es:(%esi) in 32bit mode.
81 bool isSrcOp(X86Operand &Op);
83 /// isDstOp - Returns true if operand is either (%rdi) or %es:(%rdi)
84 /// in 64bit mode or (%edi) or %es:(%edi) in 32bit mode.
85 bool isDstOp(X86Operand &Op);
87 bool is64BitMode() const {
88 // FIXME: Can tablegen auto-generate this?
89 return (STI.getFeatureBits() & X86::Mode64Bit) != 0;
92 unsigned FB = ComputeAvailableFeatures(STI.ToggleFeature(X86::Mode64Bit));
93 setAvailableFeatures(FB);
96 /// @name Auto-generated Matcher Functions
99 #define GET_ASSEMBLER_HEADER
100 #include "X86GenAsmMatcher.inc"
105 X86AsmParser(MCSubtargetInfo &sti, MCAsmParser &parser)
106 : MCTargetAsmParser(), STI(sti), Parser(parser), InstInfo(0) {
108 // Initialize the set of available features.
109 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
111 virtual bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc);
113 virtual bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
115 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
117 virtual bool ParseDirective(AsmToken DirectiveID);
119 bool isParsingIntelSyntax() {
120 return getParser().getAssemblerDialect();
123 } // end anonymous namespace
125 /// @name Auto-generated Match Functions
128 static unsigned MatchRegisterName(StringRef Name);
132 static bool isImmSExti16i8Value(uint64_t Value) {
133 return (( Value <= 0x000000000000007FULL)||
134 (0x000000000000FF80ULL <= Value && Value <= 0x000000000000FFFFULL)||
135 (0xFFFFFFFFFFFFFF80ULL <= Value && Value <= 0xFFFFFFFFFFFFFFFFULL));
138 static bool isImmSExti32i8Value(uint64_t Value) {
139 return (( Value <= 0x000000000000007FULL)||
140 (0x00000000FFFFFF80ULL <= Value && Value <= 0x00000000FFFFFFFFULL)||
141 (0xFFFFFFFFFFFFFF80ULL <= Value && Value <= 0xFFFFFFFFFFFFFFFFULL));
144 static bool isImmZExtu32u8Value(uint64_t Value) {
145 return (Value <= 0x00000000000000FFULL);
148 static bool isImmSExti64i8Value(uint64_t Value) {
149 return (( Value <= 0x000000000000007FULL)||
150 (0xFFFFFFFFFFFFFF80ULL <= Value && Value <= 0xFFFFFFFFFFFFFFFFULL));
153 static bool isImmSExti64i32Value(uint64_t Value) {
154 return (( Value <= 0x000000007FFFFFFFULL)||
155 (0xFFFFFFFF80000000ULL <= Value && Value <= 0xFFFFFFFFFFFFFFFFULL));
159 /// X86Operand - Instances of this class represent a parsed X86 machine
161 struct X86Operand : public MCParsedAsmOperand {
169 SMLoc StartLoc, EndLoc;
198 X86Operand(KindTy K, SMLoc Start, SMLoc End)
199 : Kind(K), StartLoc(Start), EndLoc(End) {}
201 /// getStartLoc - Get the location of the first token of this operand.
202 SMLoc getStartLoc() const { return StartLoc; }
203 /// getEndLoc - Get the location of the last token of this operand.
204 SMLoc getEndLoc() const { return EndLoc; }
205 /// getLocRange - Get the range between the first and last token of this
207 SMRange getLocRange() const { return SMRange(StartLoc, EndLoc); }
208 /// getOffsetOfLoc - Get the location of the offset operator.
209 SMLoc getOffsetOfLoc() const { return OffsetOfLoc; }
211 virtual void print(raw_ostream &OS) const {}
213 StringRef getToken() const {
214 assert(Kind == Token && "Invalid access!");
215 return StringRef(Tok.Data, Tok.Length);
217 void setTokenValue(StringRef Value) {
218 assert(Kind == Token && "Invalid access!");
219 Tok.Data = Value.data();
220 Tok.Length = Value.size();
223 unsigned getReg() const {
224 assert(Kind == Register && "Invalid access!");
228 const MCExpr *getImm() const {
229 assert(Kind == Immediate && "Invalid access!");
233 bool needAsmRewrite() const {
234 assert(Kind == Immediate && "Invalid access!");
235 return Imm.NeedAsmRewrite;
238 const MCExpr *getMemDisp() const {
239 assert(Kind == Memory && "Invalid access!");
242 unsigned getMemSegReg() const {
243 assert(Kind == Memory && "Invalid access!");
246 unsigned getMemBaseReg() const {
247 assert(Kind == Memory && "Invalid access!");
250 unsigned getMemIndexReg() const {
251 assert(Kind == Memory && "Invalid access!");
254 unsigned getMemScale() const {
255 assert(Kind == Memory && "Invalid access!");
259 bool isToken() const {return Kind == Token; }
261 bool isImm() const { return Kind == Immediate; }
263 bool isImmSExti16i8() const {
267 // If this isn't a constant expr, just assume it fits and let relaxation
269 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
273 // Otherwise, check the value is in a range that makes sense for this
275 return isImmSExti16i8Value(CE->getValue());
277 bool isImmSExti32i8() const {
281 // If this isn't a constant expr, just assume it fits and let relaxation
283 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
287 // Otherwise, check the value is in a range that makes sense for this
289 return isImmSExti32i8Value(CE->getValue());
291 bool isImmZExtu32u8() const {
295 // If this isn't a constant expr, just assume it fits and let relaxation
297 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
301 // Otherwise, check the value is in a range that makes sense for this
303 return isImmZExtu32u8Value(CE->getValue());
305 bool isImmSExti64i8() const {
309 // If this isn't a constant expr, just assume it fits and let relaxation
311 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
315 // Otherwise, check the value is in a range that makes sense for this
317 return isImmSExti64i8Value(CE->getValue());
319 bool isImmSExti64i32() const {
323 // If this isn't a constant expr, just assume it fits and let relaxation
325 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
329 // Otherwise, check the value is in a range that makes sense for this
331 return isImmSExti64i32Value(CE->getValue());
334 unsigned getMemSize() const {
335 assert(Kind == Memory && "Invalid access!");
339 bool isOffsetOf() const {
340 return OffsetOfLoc.getPointer();
343 bool needSizeDirective() const {
344 assert(Kind == Memory && "Invalid access!");
345 return Mem.NeedSizeDir;
348 bool isMem() const { return Kind == Memory; }
349 bool isMem8() const {
350 return Kind == Memory && (!Mem.Size || Mem.Size == 8);
352 bool isMem16() const {
353 return Kind == Memory && (!Mem.Size || Mem.Size == 16);
355 bool isMem32() const {
356 return Kind == Memory && (!Mem.Size || Mem.Size == 32);
358 bool isMem64() const {
359 return Kind == Memory && (!Mem.Size || Mem.Size == 64);
361 bool isMem80() const {
362 return Kind == Memory && (!Mem.Size || Mem.Size == 80);
364 bool isMem128() const {
365 return Kind == Memory && (!Mem.Size || Mem.Size == 128);
367 bool isMem256() const {
368 return Kind == Memory && (!Mem.Size || Mem.Size == 256);
371 bool isMemVX32() const {
372 return Kind == Memory && (!Mem.Size || Mem.Size == 32) &&
373 getMemIndexReg() >= X86::XMM0 && getMemIndexReg() <= X86::XMM15;
375 bool isMemVY32() const {
376 return Kind == Memory && (!Mem.Size || Mem.Size == 32) &&
377 getMemIndexReg() >= X86::YMM0 && getMemIndexReg() <= X86::YMM15;
379 bool isMemVX64() const {
380 return Kind == Memory && (!Mem.Size || Mem.Size == 64) &&
381 getMemIndexReg() >= X86::XMM0 && getMemIndexReg() <= X86::XMM15;
383 bool isMemVY64() const {
384 return Kind == Memory && (!Mem.Size || Mem.Size == 64) &&
385 getMemIndexReg() >= X86::YMM0 && getMemIndexReg() <= X86::YMM15;
388 bool isAbsMem() const {
389 return Kind == Memory && !getMemSegReg() && !getMemBaseReg() &&
390 !getMemIndexReg() && getMemScale() == 1;
393 bool isReg() const { return Kind == Register; }
395 void addExpr(MCInst &Inst, const MCExpr *Expr) const {
396 // Add as immediates when possible.
397 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
398 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
400 Inst.addOperand(MCOperand::CreateExpr(Expr));
403 void addRegOperands(MCInst &Inst, unsigned N) const {
404 assert(N == 1 && "Invalid number of operands!");
405 Inst.addOperand(MCOperand::CreateReg(getReg()));
408 void addImmOperands(MCInst &Inst, unsigned N) const {
409 assert(N == 1 && "Invalid number of operands!");
410 addExpr(Inst, getImm());
413 void addMem8Operands(MCInst &Inst, unsigned N) const {
414 addMemOperands(Inst, N);
416 void addMem16Operands(MCInst &Inst, unsigned N) const {
417 addMemOperands(Inst, N);
419 void addMem32Operands(MCInst &Inst, unsigned N) const {
420 addMemOperands(Inst, N);
422 void addMem64Operands(MCInst &Inst, unsigned N) const {
423 addMemOperands(Inst, N);
425 void addMem80Operands(MCInst &Inst, unsigned N) const {
426 addMemOperands(Inst, N);
428 void addMem128Operands(MCInst &Inst, unsigned N) const {
429 addMemOperands(Inst, N);
431 void addMem256Operands(MCInst &Inst, unsigned N) const {
432 addMemOperands(Inst, N);
434 void addMemVX32Operands(MCInst &Inst, unsigned N) const {
435 addMemOperands(Inst, N);
437 void addMemVY32Operands(MCInst &Inst, unsigned N) const {
438 addMemOperands(Inst, N);
440 void addMemVX64Operands(MCInst &Inst, unsigned N) const {
441 addMemOperands(Inst, N);
443 void addMemVY64Operands(MCInst &Inst, unsigned N) const {
444 addMemOperands(Inst, N);
447 void addMemOperands(MCInst &Inst, unsigned N) const {
448 assert((N == 5) && "Invalid number of operands!");
449 Inst.addOperand(MCOperand::CreateReg(getMemBaseReg()));
450 Inst.addOperand(MCOperand::CreateImm(getMemScale()));
451 Inst.addOperand(MCOperand::CreateReg(getMemIndexReg()));
452 addExpr(Inst, getMemDisp());
453 Inst.addOperand(MCOperand::CreateReg(getMemSegReg()));
456 void addAbsMemOperands(MCInst &Inst, unsigned N) const {
457 assert((N == 1) && "Invalid number of operands!");
458 // Add as immediates when possible.
459 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getMemDisp()))
460 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
462 Inst.addOperand(MCOperand::CreateExpr(getMemDisp()));
465 static X86Operand *CreateToken(StringRef Str, SMLoc Loc) {
466 SMLoc EndLoc = SMLoc::getFromPointer(Loc.getPointer() + Str.size() - 1);
467 X86Operand *Res = new X86Operand(Token, Loc, EndLoc);
468 Res->Tok.Data = Str.data();
469 Res->Tok.Length = Str.size();
473 static X86Operand *CreateReg(unsigned RegNo, SMLoc StartLoc, SMLoc EndLoc,
474 SMLoc OffsetOfLoc = SMLoc()) {
475 X86Operand *Res = new X86Operand(Register, StartLoc, EndLoc);
476 Res->Reg.RegNo = RegNo;
477 Res->OffsetOfLoc = OffsetOfLoc;
481 static X86Operand *CreateImm(const MCExpr *Val, SMLoc StartLoc, SMLoc EndLoc,
482 bool NeedRewrite = true){
483 X86Operand *Res = new X86Operand(Immediate, StartLoc, EndLoc);
485 Res->Imm.NeedAsmRewrite = NeedRewrite;
489 /// Create an absolute memory operand.
490 static X86Operand *CreateMem(const MCExpr *Disp, SMLoc StartLoc, SMLoc EndLoc,
491 unsigned Size = 0, bool NeedSizeDir = false){
492 X86Operand *Res = new X86Operand(Memory, StartLoc, EndLoc);
494 Res->Mem.Disp = Disp;
495 Res->Mem.BaseReg = 0;
496 Res->Mem.IndexReg = 0;
498 Res->Mem.Size = Size;
499 Res->Mem.NeedSizeDir = NeedSizeDir;
503 /// Create a generalized memory operand.
504 static X86Operand *CreateMem(unsigned SegReg, const MCExpr *Disp,
505 unsigned BaseReg, unsigned IndexReg,
506 unsigned Scale, SMLoc StartLoc, SMLoc EndLoc,
507 unsigned Size = 0, bool NeedSizeDir = false) {
508 // We should never just have a displacement, that should be parsed as an
509 // absolute memory operand.
510 assert((SegReg || BaseReg || IndexReg) && "Invalid memory operand!");
512 // The scale should always be one of {1,2,4,8}.
513 assert(((Scale == 1 || Scale == 2 || Scale == 4 || Scale == 8)) &&
515 X86Operand *Res = new X86Operand(Memory, StartLoc, EndLoc);
516 Res->Mem.SegReg = SegReg;
517 Res->Mem.Disp = Disp;
518 Res->Mem.BaseReg = BaseReg;
519 Res->Mem.IndexReg = IndexReg;
520 Res->Mem.Scale = Scale;
521 Res->Mem.Size = Size;
522 Res->Mem.NeedSizeDir = NeedSizeDir;
527 } // end anonymous namespace.
529 bool X86AsmParser::isSrcOp(X86Operand &Op) {
530 unsigned basereg = is64BitMode() ? X86::RSI : X86::ESI;
532 return (Op.isMem() &&
533 (Op.Mem.SegReg == 0 || Op.Mem.SegReg == X86::DS) &&
534 isa<MCConstantExpr>(Op.Mem.Disp) &&
535 cast<MCConstantExpr>(Op.Mem.Disp)->getValue() == 0 &&
536 Op.Mem.BaseReg == basereg && Op.Mem.IndexReg == 0);
539 bool X86AsmParser::isDstOp(X86Operand &Op) {
540 unsigned basereg = is64BitMode() ? X86::RDI : X86::EDI;
543 (Op.Mem.SegReg == 0 || Op.Mem.SegReg == X86::ES) &&
544 isa<MCConstantExpr>(Op.Mem.Disp) &&
545 cast<MCConstantExpr>(Op.Mem.Disp)->getValue() == 0 &&
546 Op.Mem.BaseReg == basereg && Op.Mem.IndexReg == 0;
549 bool X86AsmParser::ParseRegister(unsigned &RegNo,
550 SMLoc &StartLoc, SMLoc &EndLoc) {
552 const AsmToken &PercentTok = Parser.getTok();
553 StartLoc = PercentTok.getLoc();
555 // If we encounter a %, ignore it. This code handles registers with and
556 // without the prefix, unprefixed registers can occur in cfi directives.
557 if (!isParsingIntelSyntax() && PercentTok.is(AsmToken::Percent))
558 Parser.Lex(); // Eat percent token.
560 const AsmToken &Tok = Parser.getTok();
561 if (Tok.isNot(AsmToken::Identifier)) {
562 if (isParsingIntelSyntax()) return true;
563 return Error(StartLoc, "invalid register name",
564 SMRange(StartLoc, Tok.getEndLoc()));
567 RegNo = MatchRegisterName(Tok.getString());
569 // If the match failed, try the register name as lowercase.
571 RegNo = MatchRegisterName(Tok.getString().lower());
573 if (!is64BitMode()) {
574 // FIXME: This should be done using Requires<In32BitMode> and
575 // Requires<In64BitMode> so "eiz" usage in 64-bit instructions can be also
577 // FIXME: Check AH, CH, DH, BH cannot be used in an instruction requiring a
579 if (RegNo == X86::RIZ ||
580 X86MCRegisterClasses[X86::GR64RegClassID].contains(RegNo) ||
581 X86II::isX86_64NonExtLowByteReg(RegNo) ||
582 X86II::isX86_64ExtendedReg(RegNo))
583 return Error(StartLoc, "register %"
584 + Tok.getString() + " is only available in 64-bit mode",
585 SMRange(StartLoc, Tok.getEndLoc()));
588 // Parse "%st" as "%st(0)" and "%st(1)", which is multiple tokens.
589 if (RegNo == 0 && (Tok.getString() == "st" || Tok.getString() == "ST")) {
591 EndLoc = Tok.getLoc();
592 Parser.Lex(); // Eat 'st'
594 // Check to see if we have '(4)' after %st.
595 if (getLexer().isNot(AsmToken::LParen))
600 const AsmToken &IntTok = Parser.getTok();
601 if (IntTok.isNot(AsmToken::Integer))
602 return Error(IntTok.getLoc(), "expected stack index");
603 switch (IntTok.getIntVal()) {
604 case 0: RegNo = X86::ST0; break;
605 case 1: RegNo = X86::ST1; break;
606 case 2: RegNo = X86::ST2; break;
607 case 3: RegNo = X86::ST3; break;
608 case 4: RegNo = X86::ST4; break;
609 case 5: RegNo = X86::ST5; break;
610 case 6: RegNo = X86::ST6; break;
611 case 7: RegNo = X86::ST7; break;
612 default: return Error(IntTok.getLoc(), "invalid stack index");
615 if (getParser().Lex().isNot(AsmToken::RParen))
616 return Error(Parser.getTok().getLoc(), "expected ')'");
618 EndLoc = Tok.getLoc();
619 Parser.Lex(); // Eat ')'
623 // If this is "db[0-7]", match it as an alias
625 if (RegNo == 0 && Tok.getString().size() == 3 &&
626 Tok.getString().startswith("db")) {
627 switch (Tok.getString()[2]) {
628 case '0': RegNo = X86::DR0; break;
629 case '1': RegNo = X86::DR1; break;
630 case '2': RegNo = X86::DR2; break;
631 case '3': RegNo = X86::DR3; break;
632 case '4': RegNo = X86::DR4; break;
633 case '5': RegNo = X86::DR5; break;
634 case '6': RegNo = X86::DR6; break;
635 case '7': RegNo = X86::DR7; break;
639 EndLoc = Tok.getLoc();
640 Parser.Lex(); // Eat it.
646 if (isParsingIntelSyntax()) return true;
647 return Error(StartLoc, "invalid register name",
648 SMRange(StartLoc, Tok.getEndLoc()));
651 EndLoc = Tok.getEndLoc();
652 Parser.Lex(); // Eat identifier token.
656 X86Operand *X86AsmParser::ParseOperand() {
657 if (isParsingIntelSyntax())
658 return ParseIntelOperand();
659 return ParseATTOperand();
662 /// getIntelMemOperandSize - Return intel memory operand size.
663 static unsigned getIntelMemOperandSize(StringRef OpStr) {
664 unsigned Size = StringSwitch<unsigned>(OpStr)
665 .Cases("BYTE", "byte", 8)
666 .Cases("WORD", "word", 16)
667 .Cases("DWORD", "dword", 32)
668 .Cases("QWORD", "qword", 64)
669 .Cases("XWORD", "xword", 80)
670 .Cases("XMMWORD", "xmmword", 128)
671 .Cases("YMMWORD", "ymmword", 256)
676 X86Operand *X86AsmParser::ParseIntelBracExpression(unsigned SegReg,
678 unsigned BaseReg = 0, IndexReg = 0, Scale = 1;
679 const AsmToken &Tok = Parser.getTok();
680 SMLoc Start = Tok.getLoc(), End;
682 const MCExpr *Disp = MCConstantExpr::Create(0, getContext());
683 // Parse [ BaseReg + Scale*IndexReg + Disp ] or [ symbol ]
686 if (getLexer().isNot(AsmToken::LBrac))
687 return ErrorOperand(Start, "Expected '[' token!");
690 if (getLexer().is(AsmToken::Identifier)) {
692 if (ParseRegister(BaseReg, Start, End)) {
693 // Handle '[' 'symbol' ']'
694 if (getParser().ParseExpression(Disp, End)) return 0;
695 if (getLexer().isNot(AsmToken::RBrac))
696 return ErrorOperand(Start, "Expected ']' token!");
698 return X86Operand::CreateMem(Disp, Start, End, Size);
700 } else if (getLexer().is(AsmToken::Integer)) {
701 int64_t Val = Tok.getIntVal();
703 SMLoc Loc = Tok.getLoc();
704 if (getLexer().is(AsmToken::RBrac)) {
705 // Handle '[' number ']'
707 const MCExpr *Disp = MCConstantExpr::Create(Val, getContext());
709 return X86Operand::CreateMem(SegReg, Disp, 0, 0, Scale,
711 return X86Operand::CreateMem(Disp, Start, End, Size);
712 } else if (getLexer().is(AsmToken::Star)) {
713 // Handle '[' Scale*IndexReg ']'
715 SMLoc IdxRegLoc = Tok.getLoc();
716 if (ParseRegister(IndexReg, IdxRegLoc, End))
717 return ErrorOperand(IdxRegLoc, "Expected register");
720 return ErrorOperand(Loc, "Unexpected token");
723 if (getLexer().is(AsmToken::Plus) || getLexer().is(AsmToken::Minus)) {
724 bool isPlus = getLexer().is(AsmToken::Plus);
726 SMLoc PlusLoc = Tok.getLoc();
727 if (getLexer().is(AsmToken::Integer)) {
728 int64_t Val = Tok.getIntVal();
730 if (getLexer().is(AsmToken::Star)) {
732 SMLoc IdxRegLoc = Tok.getLoc();
733 if (ParseRegister(IndexReg, IdxRegLoc, End))
734 return ErrorOperand(IdxRegLoc, "Expected register");
736 } else if (getLexer().is(AsmToken::RBrac)) {
737 const MCExpr *ValExpr = MCConstantExpr::Create(Val, getContext());
738 Disp = isPlus ? ValExpr : MCConstantExpr::Create(0-Val, getContext());
740 return ErrorOperand(PlusLoc, "unexpected token after +");
741 } else if (getLexer().is(AsmToken::Identifier)) {
742 // This could be an index register or a displacement expression.
745 ParseRegister(IndexReg, Start, End);
746 else if (getParser().ParseExpression(Disp, End)) return 0;
750 if (getLexer().isNot(AsmToken::RBrac))
751 if (getParser().ParseExpression(Disp, End)) return 0;
754 if (getLexer().isNot(AsmToken::RBrac))
755 return ErrorOperand(End, "expected ']' token!");
759 // Parse the dot operator (e.g., [ebx].foo.bar).
760 if (Tok.getString().startswith(".")) {
762 const MCExpr *NewDisp;
763 if (ParseIntelDotOperator(Disp, &NewDisp, Err))
764 return ErrorOperand(Tok.getLoc(), Err);
766 Parser.Lex(); // Eat the field.
773 if (!BaseReg && !IndexReg)
774 return X86Operand::CreateMem(Disp, Start, End, Size);
776 return X86Operand::CreateMem(SegReg, Disp, BaseReg, IndexReg, Scale,
780 /// ParseIntelMemOperand - Parse intel style memory operand.
781 X86Operand *X86AsmParser::ParseIntelMemOperand(unsigned SegReg, SMLoc Start) {
782 const AsmToken &Tok = Parser.getTok();
785 unsigned Size = getIntelMemOperandSize(Tok.getString());
788 assert ((Tok.getString() == "PTR" || Tok.getString() == "ptr") &&
789 "Unexpected token!");
793 if (getLexer().is(AsmToken::LBrac))
794 return ParseIntelBracExpression(SegReg, Size);
796 if (!ParseRegister(SegReg, Start, End)) {
797 // Handel SegReg : [ ... ]
798 if (getLexer().isNot(AsmToken::Colon))
799 return ErrorOperand(Start, "Expected ':' token!");
800 Parser.Lex(); // Eat :
801 if (getLexer().isNot(AsmToken::LBrac))
802 return ErrorOperand(Start, "Expected '[' token!");
803 return ParseIntelBracExpression(SegReg, Size);
806 const MCExpr *Disp = MCConstantExpr::Create(0, getParser().getContext());
807 if (getParser().ParseExpression(Disp, End)) return 0;
808 End = Parser.getTok().getLoc();
810 bool NeedSizeDir = false;
811 if (!Size && isParsingInlineAsm()) {
812 if (const MCSymbolRefExpr *SymRef = dyn_cast<MCSymbolRefExpr>(Disp)) {
813 const MCSymbol &Sym = SymRef->getSymbol();
814 // FIXME: The SemaLookup will fail if the name is anything other then an
816 // FIXME: Pass a valid SMLoc.
817 SemaCallback->LookupInlineAsmIdentifier(Sym.getName(), NULL, Size);
818 NeedSizeDir = Size > 0;
821 if (!isParsingInlineAsm())
822 return X86Operand::CreateMem(Disp, Start, End, Size);
824 // When parsing inline assembly we set the base register to a non-zero value
825 // as we don't know the actual value at this time. This is necessary to
826 // get the matching correct in some cases.
827 return X86Operand::CreateMem(/*SegReg*/0, Disp, /*BaseReg*/1, /*IndexReg*/0,
828 /*Scale*/1, Start, End, Size, NeedSizeDir);
831 /// Parse the '.' operator.
832 bool X86AsmParser::ParseIntelDotOperator(const MCExpr *Disp,
833 const MCExpr **NewDisp,
834 SmallString<64> &Err) {
835 AsmToken Tok = *&Parser.getTok();
836 uint64_t OrigDispVal, DotDispVal;
838 // FIXME: Handle non-constant expressions.
839 if (const MCConstantExpr *OrigDisp = dyn_cast<MCConstantExpr>(Disp)) {
840 OrigDispVal = OrigDisp->getValue();
842 Err = "Non-constant offsets are not supported!";
847 StringRef DotDispStr = Tok.getString().drop_front(1);
849 // .Imm gets lexed as a real.
850 if (Tok.is(AsmToken::Real)) {
852 DotDispStr.getAsInteger(10, DotDisp);
853 DotDispVal = DotDisp.getZExtValue();
854 } else if (Tok.is(AsmToken::Identifier)) {
855 // We should only see an identifier when parsing the original inline asm.
856 // The front-end should rewrite this in terms of immediates.
857 assert (isParsingInlineAsm() && "Unexpected field name!");
860 std::pair<StringRef, StringRef> BaseMember = DotDispStr.split('.');
861 if (SemaCallback->LookupInlineAsmField(BaseMember.first, BaseMember.second,
863 Err = "Unable to lookup field reference!";
866 DotDispVal = DotDisp;
868 Err = "Unexpected token type!";
872 if (isParsingInlineAsm() && Tok.is(AsmToken::Identifier)) {
873 SMLoc Loc = SMLoc::getFromPointer(DotDispStr.data());
874 unsigned Len = DotDispStr.size();
875 unsigned Val = OrigDispVal + DotDispVal;
876 InstInfo->AsmRewrites->push_back(AsmRewrite(AOK_DotOperator, Loc, Len,
880 *NewDisp = MCConstantExpr::Create(OrigDispVal + DotDispVal, getContext());
884 /// Parse the 'offset' operator. This operator is used to specify the
885 /// location rather then the content of a variable.
886 X86Operand *X86AsmParser::ParseIntelOffsetOfOperator(SMLoc Start) {
887 SMLoc OffsetOfLoc = Start;
888 Parser.Lex(); // Eat offset.
889 Start = Parser.getTok().getLoc();
890 assert (Parser.getTok().is(AsmToken::Identifier) && "Expected an identifier");
894 if (getParser().ParseExpression(Val, End))
895 return ErrorOperand(Start, "Unable to parse expression!");
897 End = Parser.getTok().getLoc();
899 // Don't emit the offset operator.
900 InstInfo->AsmRewrites->push_back(AsmRewrite(AOK_Skip, OffsetOfLoc, 7));
902 // The offset operator will have an 'r' constraint, thus we need to create
903 // register operand to ensure proper matching. Just pick a GPR based on
904 // the size of a pointer.
905 unsigned RegNo = is64BitMode() ? X86::RBX : X86::EBX;
906 return X86Operand::CreateReg(RegNo, Start, End, OffsetOfLoc);
909 /// Parse the 'TYPE' operator. The TYPE operator returns the size of a C or
910 /// C++ type or variable. If the variable is an array, TYPE returns the size of
911 /// a single element of the array.
912 X86Operand *X86AsmParser::ParseIntelTypeOperator(SMLoc Start) {
913 SMLoc TypeLoc = Start;
914 Parser.Lex(); // Eat offset.
915 Start = Parser.getTok().getLoc();
916 assert (Parser.getTok().is(AsmToken::Identifier) && "Expected an identifier");
920 if (getParser().ParseExpression(Val, End))
923 End = Parser.getTok().getLoc();
926 if (const MCSymbolRefExpr *SymRef = dyn_cast<MCSymbolRefExpr>(Val)) {
927 const MCSymbol &Sym = SymRef->getSymbol();
928 // FIXME: The SemaLookup will fail if the name is anything other then an
930 // FIXME: Pass a valid SMLoc.
931 if (!SemaCallback->LookupInlineAsmIdentifier(Sym.getName(), NULL, Size))
932 return ErrorOperand(Start, "Unable to lookup TYPE of expr!");
934 Size /= 8; // Size is in terms of bits, but we want bytes in the context.
937 // Rewrite the type operator and the C or C++ type or variable in terms of an
938 // immediate. E.g. TYPE foo -> $$4
939 unsigned Len = End.getPointer() - TypeLoc.getPointer();
940 InstInfo->AsmRewrites->push_back(AsmRewrite(AOK_Imm, TypeLoc, Len, Size));
942 const MCExpr *Imm = MCConstantExpr::Create(Size, getContext());
943 return X86Operand::CreateImm(Imm, Start, End, /*NeedAsmRewrite*/false);
946 X86Operand *X86AsmParser::ParseIntelOperand() {
947 SMLoc Start = Parser.getTok().getLoc(), End;
950 StringRef AsmTokStr = Parser.getTok().getString();
951 if ((AsmTokStr == "offset" || AsmTokStr == "OFFSET") &&
952 isParsingInlineAsm())
953 return ParseIntelOffsetOfOperator(Start);
956 if ((AsmTokStr == "type" || AsmTokStr == "TYPE") &&
957 isParsingInlineAsm())
958 return ParseIntelTypeOperator(Start);
960 // Unsupported directives.
961 if (isParsingIntelSyntax() &&
962 (AsmTokStr == "size" || AsmTokStr == "SIZE" ||
963 AsmTokStr == "length" || AsmTokStr == "LENGTH"))
964 return ErrorOperand(Start, "Unsupported directive!");
967 if (getLexer().is(AsmToken::Integer) || getLexer().is(AsmToken::Real) ||
968 getLexer().is(AsmToken::Minus)) {
970 if (!getParser().ParseExpression(Val, End)) {
971 End = Parser.getTok().getLoc();
972 return X86Operand::CreateImm(Val, Start, End);
978 if (!ParseRegister(RegNo, Start, End)) {
979 // If this is a segment register followed by a ':', then this is the start
980 // of a memory reference, otherwise this is a normal register reference.
981 if (getLexer().isNot(AsmToken::Colon))
982 return X86Operand::CreateReg(RegNo, Start, Parser.getTok().getLoc());
984 getParser().Lex(); // Eat the colon.
985 return ParseIntelMemOperand(RegNo, Start);
989 return ParseIntelMemOperand(0, Start);
992 X86Operand *X86AsmParser::ParseATTOperand() {
993 switch (getLexer().getKind()) {
995 // Parse a memory operand with no segment register.
996 return ParseMemOperand(0, Parser.getTok().getLoc());
997 case AsmToken::Percent: {
998 // Read the register.
1001 if (ParseRegister(RegNo, Start, End)) return 0;
1002 if (RegNo == X86::EIZ || RegNo == X86::RIZ) {
1003 Error(Start, "%eiz and %riz can only be used as index registers",
1004 SMRange(Start, End));
1008 // If this is a segment register followed by a ':', then this is the start
1009 // of a memory reference, otherwise this is a normal register reference.
1010 if (getLexer().isNot(AsmToken::Colon))
1011 return X86Operand::CreateReg(RegNo, Start, End);
1014 getParser().Lex(); // Eat the colon.
1015 return ParseMemOperand(RegNo, Start);
1017 case AsmToken::Dollar: {
1018 // $42 -> immediate.
1019 SMLoc Start = Parser.getTok().getLoc(), End;
1022 if (getParser().ParseExpression(Val, End))
1024 return X86Operand::CreateImm(Val, Start, End);
1029 /// ParseMemOperand: segment: disp(basereg, indexreg, scale). The '%ds:' prefix
1030 /// has already been parsed if present.
1031 X86Operand *X86AsmParser::ParseMemOperand(unsigned SegReg, SMLoc MemStart) {
1033 // We have to disambiguate a parenthesized expression "(4+5)" from the start
1034 // of a memory operand with a missing displacement "(%ebx)" or "(,%eax)". The
1035 // only way to do this without lookahead is to eat the '(' and see what is
1037 const MCExpr *Disp = MCConstantExpr::Create(0, getParser().getContext());
1038 if (getLexer().isNot(AsmToken::LParen)) {
1040 if (getParser().ParseExpression(Disp, ExprEnd)) return 0;
1042 // After parsing the base expression we could either have a parenthesized
1043 // memory address or not. If not, return now. If so, eat the (.
1044 if (getLexer().isNot(AsmToken::LParen)) {
1045 // Unless we have a segment register, treat this as an immediate.
1047 return X86Operand::CreateMem(Disp, MemStart, ExprEnd);
1048 return X86Operand::CreateMem(SegReg, Disp, 0, 0, 1, MemStart, ExprEnd);
1054 // Okay, we have a '('. We don't know if this is an expression or not, but
1055 // so we have to eat the ( to see beyond it.
1056 SMLoc LParenLoc = Parser.getTok().getLoc();
1057 Parser.Lex(); // Eat the '('.
1059 if (getLexer().is(AsmToken::Percent) || getLexer().is(AsmToken::Comma)) {
1060 // Nothing to do here, fall into the code below with the '(' part of the
1061 // memory operand consumed.
1065 // It must be an parenthesized expression, parse it now.
1066 if (getParser().ParseParenExpression(Disp, ExprEnd))
1069 // After parsing the base expression we could either have a parenthesized
1070 // memory address or not. If not, return now. If so, eat the (.
1071 if (getLexer().isNot(AsmToken::LParen)) {
1072 // Unless we have a segment register, treat this as an immediate.
1074 return X86Operand::CreateMem(Disp, LParenLoc, ExprEnd);
1075 return X86Operand::CreateMem(SegReg, Disp, 0, 0, 1, MemStart, ExprEnd);
1083 // If we reached here, then we just ate the ( of the memory operand. Process
1084 // the rest of the memory operand.
1085 unsigned BaseReg = 0, IndexReg = 0, Scale = 1;
1088 if (getLexer().is(AsmToken::Percent)) {
1089 SMLoc StartLoc, EndLoc;
1090 if (ParseRegister(BaseReg, StartLoc, EndLoc)) return 0;
1091 if (BaseReg == X86::EIZ || BaseReg == X86::RIZ) {
1092 Error(StartLoc, "eiz and riz can only be used as index registers",
1093 SMRange(StartLoc, EndLoc));
1098 if (getLexer().is(AsmToken::Comma)) {
1099 Parser.Lex(); // Eat the comma.
1100 IndexLoc = Parser.getTok().getLoc();
1102 // Following the comma we should have either an index register, or a scale
1103 // value. We don't support the later form, but we want to parse it
1106 // Not that even though it would be completely consistent to support syntax
1107 // like "1(%eax,,1)", the assembler doesn't. Use "eiz" or "riz" for this.
1108 if (getLexer().is(AsmToken::Percent)) {
1110 if (ParseRegister(IndexReg, L, L)) return 0;
1112 if (getLexer().isNot(AsmToken::RParen)) {
1113 // Parse the scale amount:
1114 // ::= ',' [scale-expression]
1115 if (getLexer().isNot(AsmToken::Comma)) {
1116 Error(Parser.getTok().getLoc(),
1117 "expected comma in scale expression");
1120 Parser.Lex(); // Eat the comma.
1122 if (getLexer().isNot(AsmToken::RParen)) {
1123 SMLoc Loc = Parser.getTok().getLoc();
1126 if (getParser().ParseAbsoluteExpression(ScaleVal)){
1127 Error(Loc, "expected scale expression");
1131 // Validate the scale amount.
1132 if (ScaleVal != 1 && ScaleVal != 2 && ScaleVal != 4 && ScaleVal != 8){
1133 Error(Loc, "scale factor in address must be 1, 2, 4 or 8");
1136 Scale = (unsigned)ScaleVal;
1139 } else if (getLexer().isNot(AsmToken::RParen)) {
1140 // A scale amount without an index is ignored.
1142 SMLoc Loc = Parser.getTok().getLoc();
1145 if (getParser().ParseAbsoluteExpression(Value))
1149 Warning(Loc, "scale factor without index register is ignored");
1154 // Ok, we've eaten the memory operand, verify we have a ')' and eat it too.
1155 if (getLexer().isNot(AsmToken::RParen)) {
1156 Error(Parser.getTok().getLoc(), "unexpected token in memory operand");
1159 SMLoc MemEnd = Parser.getTok().getLoc();
1160 Parser.Lex(); // Eat the ')'.
1162 // If we have both a base register and an index register make sure they are
1163 // both 64-bit or 32-bit registers.
1164 // To support VSIB, IndexReg can be 128-bit or 256-bit registers.
1165 if (BaseReg != 0 && IndexReg != 0) {
1166 if (X86MCRegisterClasses[X86::GR64RegClassID].contains(BaseReg) &&
1167 (X86MCRegisterClasses[X86::GR16RegClassID].contains(IndexReg) ||
1168 X86MCRegisterClasses[X86::GR32RegClassID].contains(IndexReg)) &&
1169 IndexReg != X86::RIZ) {
1170 Error(IndexLoc, "index register is 32-bit, but base register is 64-bit");
1173 if (X86MCRegisterClasses[X86::GR32RegClassID].contains(BaseReg) &&
1174 (X86MCRegisterClasses[X86::GR16RegClassID].contains(IndexReg) ||
1175 X86MCRegisterClasses[X86::GR64RegClassID].contains(IndexReg)) &&
1176 IndexReg != X86::EIZ){
1177 Error(IndexLoc, "index register is 64-bit, but base register is 32-bit");
1182 return X86Operand::CreateMem(SegReg, Disp, BaseReg, IndexReg, Scale,
1187 ParseInstruction(ParseInstructionInfo &Info, StringRef Name, SMLoc NameLoc,
1188 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1190 StringRef PatchedName = Name;
1192 // FIXME: Hack to recognize setneb as setne.
1193 if (PatchedName.startswith("set") && PatchedName.endswith("b") &&
1194 PatchedName != "setb" && PatchedName != "setnb")
1195 PatchedName = PatchedName.substr(0, Name.size()-1);
1197 // FIXME: Hack to recognize cmp<comparison code>{ss,sd,ps,pd}.
1198 const MCExpr *ExtraImmOp = 0;
1199 if ((PatchedName.startswith("cmp") || PatchedName.startswith("vcmp")) &&
1200 (PatchedName.endswith("ss") || PatchedName.endswith("sd") ||
1201 PatchedName.endswith("ps") || PatchedName.endswith("pd"))) {
1202 bool IsVCMP = PatchedName[0] == 'v';
1203 unsigned SSECCIdx = IsVCMP ? 4 : 3;
1204 unsigned SSEComparisonCode = StringSwitch<unsigned>(
1205 PatchedName.slice(SSECCIdx, PatchedName.size() - 2))
1209 .Case("unord", 0x03)
1214 /* AVX only from here */
1215 .Case("eq_uq", 0x08)
1218 .Case("false", 0x0B)
1219 .Case("neq_oq", 0x0C)
1223 .Case("eq_os", 0x10)
1224 .Case("lt_oq", 0x11)
1225 .Case("le_oq", 0x12)
1226 .Case("unord_s", 0x13)
1227 .Case("neq_us", 0x14)
1228 .Case("nlt_uq", 0x15)
1229 .Case("nle_uq", 0x16)
1230 .Case("ord_s", 0x17)
1231 .Case("eq_us", 0x18)
1232 .Case("nge_uq", 0x19)
1233 .Case("ngt_uq", 0x1A)
1234 .Case("false_os", 0x1B)
1235 .Case("neq_os", 0x1C)
1236 .Case("ge_oq", 0x1D)
1237 .Case("gt_oq", 0x1E)
1238 .Case("true_us", 0x1F)
1240 if (SSEComparisonCode != ~0U && (IsVCMP || SSEComparisonCode < 8)) {
1241 ExtraImmOp = MCConstantExpr::Create(SSEComparisonCode,
1242 getParser().getContext());
1243 if (PatchedName.endswith("ss")) {
1244 PatchedName = IsVCMP ? "vcmpss" : "cmpss";
1245 } else if (PatchedName.endswith("sd")) {
1246 PatchedName = IsVCMP ? "vcmpsd" : "cmpsd";
1247 } else if (PatchedName.endswith("ps")) {
1248 PatchedName = IsVCMP ? "vcmpps" : "cmpps";
1250 assert(PatchedName.endswith("pd") && "Unexpected mnemonic!");
1251 PatchedName = IsVCMP ? "vcmppd" : "cmppd";
1256 Operands.push_back(X86Operand::CreateToken(PatchedName, NameLoc));
1258 if (ExtraImmOp && !isParsingIntelSyntax())
1259 Operands.push_back(X86Operand::CreateImm(ExtraImmOp, NameLoc, NameLoc));
1261 // Determine whether this is an instruction prefix.
1263 Name == "lock" || Name == "rep" ||
1264 Name == "repe" || Name == "repz" ||
1265 Name == "repne" || Name == "repnz" ||
1266 Name == "rex64" || Name == "data16";
1269 // This does the actual operand parsing. Don't parse any more if we have a
1270 // prefix juxtaposed with an operation like "lock incl 4(%rax)", because we
1271 // just want to parse the "lock" as the first instruction and the "incl" as
1273 if (getLexer().isNot(AsmToken::EndOfStatement) && !isPrefix) {
1275 // Parse '*' modifier.
1276 if (getLexer().is(AsmToken::Star)) {
1277 SMLoc Loc = Parser.getTok().getLoc();
1278 Operands.push_back(X86Operand::CreateToken("*", Loc));
1279 Parser.Lex(); // Eat the star.
1282 // Read the first operand.
1283 if (X86Operand *Op = ParseOperand())
1284 Operands.push_back(Op);
1286 Parser.EatToEndOfStatement();
1290 while (getLexer().is(AsmToken::Comma)) {
1291 Parser.Lex(); // Eat the comma.
1293 // Parse and remember the operand.
1294 if (X86Operand *Op = ParseOperand())
1295 Operands.push_back(Op);
1297 Parser.EatToEndOfStatement();
1302 if (getLexer().isNot(AsmToken::EndOfStatement)) {
1303 SMLoc Loc = getLexer().getLoc();
1304 Parser.EatToEndOfStatement();
1305 return Error(Loc, "unexpected token in argument list");
1309 if (getLexer().is(AsmToken::EndOfStatement))
1310 Parser.Lex(); // Consume the EndOfStatement
1311 else if (isPrefix && getLexer().is(AsmToken::Slash))
1312 Parser.Lex(); // Consume the prefix separator Slash
1314 if (ExtraImmOp && isParsingIntelSyntax())
1315 Operands.push_back(X86Operand::CreateImm(ExtraImmOp, NameLoc, NameLoc));
1317 // This is a terrible hack to handle "out[bwl]? %al, (%dx)" ->
1318 // "outb %al, %dx". Out doesn't take a memory form, but this is a widely
1319 // documented form in various unofficial manuals, so a lot of code uses it.
1320 if ((Name == "outb" || Name == "outw" || Name == "outl" || Name == "out") &&
1321 Operands.size() == 3) {
1322 X86Operand &Op = *(X86Operand*)Operands.back();
1323 if (Op.isMem() && Op.Mem.SegReg == 0 &&
1324 isa<MCConstantExpr>(Op.Mem.Disp) &&
1325 cast<MCConstantExpr>(Op.Mem.Disp)->getValue() == 0 &&
1326 Op.Mem.BaseReg == MatchRegisterName("dx") && Op.Mem.IndexReg == 0) {
1327 SMLoc Loc = Op.getEndLoc();
1328 Operands.back() = X86Operand::CreateReg(Op.Mem.BaseReg, Loc, Loc);
1332 // Same hack for "in[bwl]? (%dx), %al" -> "inb %dx, %al".
1333 if ((Name == "inb" || Name == "inw" || Name == "inl" || Name == "in") &&
1334 Operands.size() == 3) {
1335 X86Operand &Op = *(X86Operand*)Operands.begin()[1];
1336 if (Op.isMem() && Op.Mem.SegReg == 0 &&
1337 isa<MCConstantExpr>(Op.Mem.Disp) &&
1338 cast<MCConstantExpr>(Op.Mem.Disp)->getValue() == 0 &&
1339 Op.Mem.BaseReg == MatchRegisterName("dx") && Op.Mem.IndexReg == 0) {
1340 SMLoc Loc = Op.getEndLoc();
1341 Operands.begin()[1] = X86Operand::CreateReg(Op.Mem.BaseReg, Loc, Loc);
1345 // Transform "ins[bwl] %dx, %es:(%edi)" into "ins[bwl]"
1346 if (Name.startswith("ins") && Operands.size() == 3 &&
1347 (Name == "insb" || Name == "insw" || Name == "insl")) {
1348 X86Operand &Op = *(X86Operand*)Operands.begin()[1];
1349 X86Operand &Op2 = *(X86Operand*)Operands.begin()[2];
1350 if (Op.isReg() && Op.getReg() == X86::DX && isDstOp(Op2)) {
1351 Operands.pop_back();
1352 Operands.pop_back();
1358 // Transform "outs[bwl] %ds:(%esi), %dx" into "out[bwl]"
1359 if (Name.startswith("outs") && Operands.size() == 3 &&
1360 (Name == "outsb" || Name == "outsw" || Name == "outsl")) {
1361 X86Operand &Op = *(X86Operand*)Operands.begin()[1];
1362 X86Operand &Op2 = *(X86Operand*)Operands.begin()[2];
1363 if (isSrcOp(Op) && Op2.isReg() && Op2.getReg() == X86::DX) {
1364 Operands.pop_back();
1365 Operands.pop_back();
1371 // Transform "movs[bwl] %ds:(%esi), %es:(%edi)" into "movs[bwl]"
1372 if (Name.startswith("movs") && Operands.size() == 3 &&
1373 (Name == "movsb" || Name == "movsw" || Name == "movsl" ||
1374 (is64BitMode() && Name == "movsq"))) {
1375 X86Operand &Op = *(X86Operand*)Operands.begin()[1];
1376 X86Operand &Op2 = *(X86Operand*)Operands.begin()[2];
1377 if (isSrcOp(Op) && isDstOp(Op2)) {
1378 Operands.pop_back();
1379 Operands.pop_back();
1384 // Transform "lods[bwl] %ds:(%esi),{%al,%ax,%eax,%rax}" into "lods[bwl]"
1385 if (Name.startswith("lods") && Operands.size() == 3 &&
1386 (Name == "lods" || Name == "lodsb" || Name == "lodsw" ||
1387 Name == "lodsl" || (is64BitMode() && Name == "lodsq"))) {
1388 X86Operand *Op1 = static_cast<X86Operand*>(Operands[1]);
1389 X86Operand *Op2 = static_cast<X86Operand*>(Operands[2]);
1390 if (isSrcOp(*Op1) && Op2->isReg()) {
1392 unsigned reg = Op2->getReg();
1393 bool isLods = Name == "lods";
1394 if (reg == X86::AL && (isLods || Name == "lodsb"))
1396 else if (reg == X86::AX && (isLods || Name == "lodsw"))
1398 else if (reg == X86::EAX && (isLods || Name == "lodsl"))
1400 else if (reg == X86::RAX && (isLods || Name == "lodsq"))
1405 Operands.pop_back();
1406 Operands.pop_back();
1410 static_cast<X86Operand*>(Operands[0])->setTokenValue(ins);
1414 // Transform "stos[bwl] {%al,%ax,%eax,%rax},%es:(%edi)" into "stos[bwl]"
1415 if (Name.startswith("stos") && Operands.size() == 3 &&
1416 (Name == "stos" || Name == "stosb" || Name == "stosw" ||
1417 Name == "stosl" || (is64BitMode() && Name == "stosq"))) {
1418 X86Operand *Op1 = static_cast<X86Operand*>(Operands[1]);
1419 X86Operand *Op2 = static_cast<X86Operand*>(Operands[2]);
1420 if (isDstOp(*Op2) && Op1->isReg()) {
1422 unsigned reg = Op1->getReg();
1423 bool isStos = Name == "stos";
1424 if (reg == X86::AL && (isStos || Name == "stosb"))
1426 else if (reg == X86::AX && (isStos || Name == "stosw"))
1428 else if (reg == X86::EAX && (isStos || Name == "stosl"))
1430 else if (reg == X86::RAX && (isStos || Name == "stosq"))
1435 Operands.pop_back();
1436 Operands.pop_back();
1440 static_cast<X86Operand*>(Operands[0])->setTokenValue(ins);
1445 // FIXME: Hack to handle recognize s{hr,ar,hl} $1, <op>. Canonicalize to
1447 if ((Name.startswith("shr") || Name.startswith("sar") ||
1448 Name.startswith("shl") || Name.startswith("sal") ||
1449 Name.startswith("rcl") || Name.startswith("rcr") ||
1450 Name.startswith("rol") || Name.startswith("ror")) &&
1451 Operands.size() == 3) {
1452 if (isParsingIntelSyntax()) {
1454 X86Operand *Op1 = static_cast<X86Operand*>(Operands[2]);
1455 if (Op1->isImm() && isa<MCConstantExpr>(Op1->getImm()) &&
1456 cast<MCConstantExpr>(Op1->getImm())->getValue() == 1) {
1458 Operands.pop_back();
1461 X86Operand *Op1 = static_cast<X86Operand*>(Operands[1]);
1462 if (Op1->isImm() && isa<MCConstantExpr>(Op1->getImm()) &&
1463 cast<MCConstantExpr>(Op1->getImm())->getValue() == 1) {
1465 Operands.erase(Operands.begin() + 1);
1470 // Transforms "int $3" into "int3" as a size optimization. We can't write an
1471 // instalias with an immediate operand yet.
1472 if (Name == "int" && Operands.size() == 2) {
1473 X86Operand *Op1 = static_cast<X86Operand*>(Operands[1]);
1474 if (Op1->isImm() && isa<MCConstantExpr>(Op1->getImm()) &&
1475 cast<MCConstantExpr>(Op1->getImm())->getValue() == 3) {
1477 Operands.erase(Operands.begin() + 1);
1478 static_cast<X86Operand*>(Operands[0])->setTokenValue("int3");
1486 processInstruction(MCInst &Inst,
1487 const SmallVectorImpl<MCParsedAsmOperand*> &Ops) {
1488 switch (Inst.getOpcode()) {
1489 default: return false;
1490 case X86::AND16i16: {
1491 if (!Inst.getOperand(0).isImm() ||
1492 !isImmSExti16i8Value(Inst.getOperand(0).getImm()))
1496 TmpInst.setOpcode(X86::AND16ri8);
1497 TmpInst.addOperand(MCOperand::CreateReg(X86::AX));
1498 TmpInst.addOperand(MCOperand::CreateReg(X86::AX));
1499 TmpInst.addOperand(Inst.getOperand(0));
1503 case X86::AND32i32: {
1504 if (!Inst.getOperand(0).isImm() ||
1505 !isImmSExti32i8Value(Inst.getOperand(0).getImm()))
1509 TmpInst.setOpcode(X86::AND32ri8);
1510 TmpInst.addOperand(MCOperand::CreateReg(X86::EAX));
1511 TmpInst.addOperand(MCOperand::CreateReg(X86::EAX));
1512 TmpInst.addOperand(Inst.getOperand(0));
1516 case X86::AND64i32: {
1517 if (!Inst.getOperand(0).isImm() ||
1518 !isImmSExti64i8Value(Inst.getOperand(0).getImm()))
1522 TmpInst.setOpcode(X86::AND64ri8);
1523 TmpInst.addOperand(MCOperand::CreateReg(X86::RAX));
1524 TmpInst.addOperand(MCOperand::CreateReg(X86::RAX));
1525 TmpInst.addOperand(Inst.getOperand(0));
1529 case X86::XOR16i16: {
1530 if (!Inst.getOperand(0).isImm() ||
1531 !isImmSExti16i8Value(Inst.getOperand(0).getImm()))
1535 TmpInst.setOpcode(X86::XOR16ri8);
1536 TmpInst.addOperand(MCOperand::CreateReg(X86::AX));
1537 TmpInst.addOperand(MCOperand::CreateReg(X86::AX));
1538 TmpInst.addOperand(Inst.getOperand(0));
1542 case X86::XOR32i32: {
1543 if (!Inst.getOperand(0).isImm() ||
1544 !isImmSExti32i8Value(Inst.getOperand(0).getImm()))
1548 TmpInst.setOpcode(X86::XOR32ri8);
1549 TmpInst.addOperand(MCOperand::CreateReg(X86::EAX));
1550 TmpInst.addOperand(MCOperand::CreateReg(X86::EAX));
1551 TmpInst.addOperand(Inst.getOperand(0));
1555 case X86::XOR64i32: {
1556 if (!Inst.getOperand(0).isImm() ||
1557 !isImmSExti64i8Value(Inst.getOperand(0).getImm()))
1561 TmpInst.setOpcode(X86::XOR64ri8);
1562 TmpInst.addOperand(MCOperand::CreateReg(X86::RAX));
1563 TmpInst.addOperand(MCOperand::CreateReg(X86::RAX));
1564 TmpInst.addOperand(Inst.getOperand(0));
1568 case X86::OR16i16: {
1569 if (!Inst.getOperand(0).isImm() ||
1570 !isImmSExti16i8Value(Inst.getOperand(0).getImm()))
1574 TmpInst.setOpcode(X86::OR16ri8);
1575 TmpInst.addOperand(MCOperand::CreateReg(X86::AX));
1576 TmpInst.addOperand(MCOperand::CreateReg(X86::AX));
1577 TmpInst.addOperand(Inst.getOperand(0));
1581 case X86::OR32i32: {
1582 if (!Inst.getOperand(0).isImm() ||
1583 !isImmSExti32i8Value(Inst.getOperand(0).getImm()))
1587 TmpInst.setOpcode(X86::OR32ri8);
1588 TmpInst.addOperand(MCOperand::CreateReg(X86::EAX));
1589 TmpInst.addOperand(MCOperand::CreateReg(X86::EAX));
1590 TmpInst.addOperand(Inst.getOperand(0));
1594 case X86::OR64i32: {
1595 if (!Inst.getOperand(0).isImm() ||
1596 !isImmSExti64i8Value(Inst.getOperand(0).getImm()))
1600 TmpInst.setOpcode(X86::OR64ri8);
1601 TmpInst.addOperand(MCOperand::CreateReg(X86::RAX));
1602 TmpInst.addOperand(MCOperand::CreateReg(X86::RAX));
1603 TmpInst.addOperand(Inst.getOperand(0));
1607 case X86::CMP16i16: {
1608 if (!Inst.getOperand(0).isImm() ||
1609 !isImmSExti16i8Value(Inst.getOperand(0).getImm()))
1613 TmpInst.setOpcode(X86::CMP16ri8);
1614 TmpInst.addOperand(MCOperand::CreateReg(X86::AX));
1615 TmpInst.addOperand(Inst.getOperand(0));
1619 case X86::CMP32i32: {
1620 if (!Inst.getOperand(0).isImm() ||
1621 !isImmSExti32i8Value(Inst.getOperand(0).getImm()))
1625 TmpInst.setOpcode(X86::CMP32ri8);
1626 TmpInst.addOperand(MCOperand::CreateReg(X86::EAX));
1627 TmpInst.addOperand(Inst.getOperand(0));
1631 case X86::CMP64i32: {
1632 if (!Inst.getOperand(0).isImm() ||
1633 !isImmSExti64i8Value(Inst.getOperand(0).getImm()))
1637 TmpInst.setOpcode(X86::CMP64ri8);
1638 TmpInst.addOperand(MCOperand::CreateReg(X86::RAX));
1639 TmpInst.addOperand(Inst.getOperand(0));
1643 case X86::ADD16i16: {
1644 if (!Inst.getOperand(0).isImm() ||
1645 !isImmSExti16i8Value(Inst.getOperand(0).getImm()))
1649 TmpInst.setOpcode(X86::ADD16ri8);
1650 TmpInst.addOperand(MCOperand::CreateReg(X86::AX));
1651 TmpInst.addOperand(MCOperand::CreateReg(X86::AX));
1652 TmpInst.addOperand(Inst.getOperand(0));
1656 case X86::ADD32i32: {
1657 if (!Inst.getOperand(0).isImm() ||
1658 !isImmSExti32i8Value(Inst.getOperand(0).getImm()))
1662 TmpInst.setOpcode(X86::ADD32ri8);
1663 TmpInst.addOperand(MCOperand::CreateReg(X86::EAX));
1664 TmpInst.addOperand(MCOperand::CreateReg(X86::EAX));
1665 TmpInst.addOperand(Inst.getOperand(0));
1669 case X86::ADD64i32: {
1670 if (!Inst.getOperand(0).isImm() ||
1671 !isImmSExti64i8Value(Inst.getOperand(0).getImm()))
1675 TmpInst.setOpcode(X86::ADD64ri8);
1676 TmpInst.addOperand(MCOperand::CreateReg(X86::RAX));
1677 TmpInst.addOperand(MCOperand::CreateReg(X86::RAX));
1678 TmpInst.addOperand(Inst.getOperand(0));
1682 case X86::SUB16i16: {
1683 if (!Inst.getOperand(0).isImm() ||
1684 !isImmSExti16i8Value(Inst.getOperand(0).getImm()))
1688 TmpInst.setOpcode(X86::SUB16ri8);
1689 TmpInst.addOperand(MCOperand::CreateReg(X86::AX));
1690 TmpInst.addOperand(MCOperand::CreateReg(X86::AX));
1691 TmpInst.addOperand(Inst.getOperand(0));
1695 case X86::SUB32i32: {
1696 if (!Inst.getOperand(0).isImm() ||
1697 !isImmSExti32i8Value(Inst.getOperand(0).getImm()))
1701 TmpInst.setOpcode(X86::SUB32ri8);
1702 TmpInst.addOperand(MCOperand::CreateReg(X86::EAX));
1703 TmpInst.addOperand(MCOperand::CreateReg(X86::EAX));
1704 TmpInst.addOperand(Inst.getOperand(0));
1708 case X86::SUB64i32: {
1709 if (!Inst.getOperand(0).isImm() ||
1710 !isImmSExti64i8Value(Inst.getOperand(0).getImm()))
1714 TmpInst.setOpcode(X86::SUB64ri8);
1715 TmpInst.addOperand(MCOperand::CreateReg(X86::RAX));
1716 TmpInst.addOperand(MCOperand::CreateReg(X86::RAX));
1717 TmpInst.addOperand(Inst.getOperand(0));
1725 MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
1726 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
1727 MCStreamer &Out, unsigned &ErrorInfo,
1728 bool MatchingInlineAsm) {
1729 assert(!Operands.empty() && "Unexpect empty operand list!");
1730 X86Operand *Op = static_cast<X86Operand*>(Operands[0]);
1731 assert(Op->isToken() && "Leading operand should always be a mnemonic!");
1732 ArrayRef<SMRange> EmptyRanges = ArrayRef<SMRange>();
1734 // First, handle aliases that expand to multiple instructions.
1735 // FIXME: This should be replaced with a real .td file alias mechanism.
1736 // Also, MatchInstructionImpl should actually *do* the EmitInstruction
1738 if (Op->getToken() == "fstsw" || Op->getToken() == "fstcw" ||
1739 Op->getToken() == "fstsww" || Op->getToken() == "fstcww" ||
1740 Op->getToken() == "finit" || Op->getToken() == "fsave" ||
1741 Op->getToken() == "fstenv" || Op->getToken() == "fclex") {
1743 Inst.setOpcode(X86::WAIT);
1745 if (!MatchingInlineAsm)
1746 Out.EmitInstruction(Inst);
1749 StringSwitch<const char*>(Op->getToken())
1750 .Case("finit", "fninit")
1751 .Case("fsave", "fnsave")
1752 .Case("fstcw", "fnstcw")
1753 .Case("fstcww", "fnstcw")
1754 .Case("fstenv", "fnstenv")
1755 .Case("fstsw", "fnstsw")
1756 .Case("fstsww", "fnstsw")
1757 .Case("fclex", "fnclex")
1759 assert(Repl && "Unknown wait-prefixed instruction");
1761 Operands[0] = X86Operand::CreateToken(Repl, IDLoc);
1764 bool WasOriginallyInvalidOperand = false;
1767 // First, try a direct match.
1768 switch (MatchInstructionImpl(Operands, Inst,
1769 ErrorInfo, MatchingInlineAsm,
1770 isParsingIntelSyntax())) {
1773 // Some instructions need post-processing to, for example, tweak which
1774 // encoding is selected. Loop on it while changes happen so the
1775 // individual transformations can chain off each other.
1776 if (!MatchingInlineAsm)
1777 while (processInstruction(Inst, Operands))
1781 if (!MatchingInlineAsm)
1782 Out.EmitInstruction(Inst);
1783 Opcode = Inst.getOpcode();
1785 case Match_MissingFeature:
1786 Error(IDLoc, "instruction requires a CPU feature not currently enabled",
1787 EmptyRanges, MatchingInlineAsm);
1789 case Match_InvalidOperand:
1790 WasOriginallyInvalidOperand = true;
1792 case Match_MnemonicFail:
1796 // FIXME: Ideally, we would only attempt suffix matches for things which are
1797 // valid prefixes, and we could just infer the right unambiguous
1798 // type. However, that requires substantially more matcher support than the
1801 // Change the operand to point to a temporary token.
1802 StringRef Base = Op->getToken();
1803 SmallString<16> Tmp;
1806 Op->setTokenValue(Tmp.str());
1808 // If this instruction starts with an 'f', then it is a floating point stack
1809 // instruction. These come in up to three forms for 32-bit, 64-bit, and
1810 // 80-bit floating point, which use the suffixes s,l,t respectively.
1812 // Otherwise, we assume that this may be an integer instruction, which comes
1813 // in 8/16/32/64-bit forms using the b,w,l,q suffixes respectively.
1814 const char *Suffixes = Base[0] != 'f' ? "bwlq" : "slt\0";
1816 // Check for the various suffix matches.
1817 Tmp[Base.size()] = Suffixes[0];
1818 unsigned ErrorInfoIgnore;
1819 unsigned Match1, Match2, Match3, Match4;
1821 Match1 = MatchInstructionImpl(Operands, Inst, ErrorInfoIgnore,
1822 isParsingIntelSyntax());
1823 Tmp[Base.size()] = Suffixes[1];
1824 Match2 = MatchInstructionImpl(Operands, Inst, ErrorInfoIgnore,
1825 isParsingIntelSyntax());
1826 Tmp[Base.size()] = Suffixes[2];
1827 Match3 = MatchInstructionImpl(Operands, Inst, ErrorInfoIgnore,
1828 isParsingIntelSyntax());
1829 Tmp[Base.size()] = Suffixes[3];
1830 Match4 = MatchInstructionImpl(Operands, Inst, ErrorInfoIgnore,
1831 isParsingIntelSyntax());
1833 // Restore the old token.
1834 Op->setTokenValue(Base);
1836 // If exactly one matched, then we treat that as a successful match (and the
1837 // instruction will already have been filled in correctly, since the failing
1838 // matches won't have modified it).
1839 unsigned NumSuccessfulMatches =
1840 (Match1 == Match_Success) + (Match2 == Match_Success) +
1841 (Match3 == Match_Success) + (Match4 == Match_Success);
1842 if (NumSuccessfulMatches == 1) {
1844 if (!MatchingInlineAsm)
1845 Out.EmitInstruction(Inst);
1846 Opcode = Inst.getOpcode();
1850 // Otherwise, the match failed, try to produce a decent error message.
1852 // If we had multiple suffix matches, then identify this as an ambiguous
1854 if (NumSuccessfulMatches > 1) {
1856 unsigned NumMatches = 0;
1857 if (Match1 == Match_Success) MatchChars[NumMatches++] = Suffixes[0];
1858 if (Match2 == Match_Success) MatchChars[NumMatches++] = Suffixes[1];
1859 if (Match3 == Match_Success) MatchChars[NumMatches++] = Suffixes[2];
1860 if (Match4 == Match_Success) MatchChars[NumMatches++] = Suffixes[3];
1862 SmallString<126> Msg;
1863 raw_svector_ostream OS(Msg);
1864 OS << "ambiguous instructions require an explicit suffix (could be ";
1865 for (unsigned i = 0; i != NumMatches; ++i) {
1868 if (i + 1 == NumMatches)
1870 OS << "'" << Base << MatchChars[i] << "'";
1873 Error(IDLoc, OS.str(), EmptyRanges, MatchingInlineAsm);
1877 // Okay, we know that none of the variants matched successfully.
1879 // If all of the instructions reported an invalid mnemonic, then the original
1880 // mnemonic was invalid.
1881 if ((Match1 == Match_MnemonicFail) && (Match2 == Match_MnemonicFail) &&
1882 (Match3 == Match_MnemonicFail) && (Match4 == Match_MnemonicFail)) {
1883 if (!WasOriginallyInvalidOperand) {
1884 ArrayRef<SMRange> Ranges = MatchingInlineAsm ? EmptyRanges :
1886 return Error(IDLoc, "invalid instruction mnemonic '" + Base + "'",
1887 Ranges, MatchingInlineAsm);
1890 // Recover location info for the operand if we know which was the problem.
1891 if (ErrorInfo != ~0U) {
1892 if (ErrorInfo >= Operands.size())
1893 return Error(IDLoc, "too few operands for instruction",
1894 EmptyRanges, MatchingInlineAsm);
1896 X86Operand *Operand = (X86Operand*)Operands[ErrorInfo];
1897 if (Operand->getStartLoc().isValid()) {
1898 SMRange OperandRange = Operand->getLocRange();
1899 return Error(Operand->getStartLoc(), "invalid operand for instruction",
1900 OperandRange, MatchingInlineAsm);
1904 return Error(IDLoc, "invalid operand for instruction", EmptyRanges,
1908 // If one instruction matched with a missing feature, report this as a
1910 if ((Match1 == Match_MissingFeature) + (Match2 == Match_MissingFeature) +
1911 (Match3 == Match_MissingFeature) + (Match4 == Match_MissingFeature) == 1){
1912 Error(IDLoc, "instruction requires a CPU feature not currently enabled",
1913 EmptyRanges, MatchingInlineAsm);
1917 // If one instruction matched with an invalid operand, report this as an
1919 if ((Match1 == Match_InvalidOperand) + (Match2 == Match_InvalidOperand) +
1920 (Match3 == Match_InvalidOperand) + (Match4 == Match_InvalidOperand) == 1){
1921 Error(IDLoc, "invalid operand for instruction", EmptyRanges,
1926 // If all of these were an outright failure, report it in a useless way.
1927 Error(IDLoc, "unknown use of instruction mnemonic without a size suffix",
1928 EmptyRanges, MatchingInlineAsm);
1933 bool X86AsmParser::ParseDirective(AsmToken DirectiveID) {
1934 StringRef IDVal = DirectiveID.getIdentifier();
1935 if (IDVal == ".word")
1936 return ParseDirectiveWord(2, DirectiveID.getLoc());
1937 else if (IDVal.startswith(".code"))
1938 return ParseDirectiveCode(IDVal, DirectiveID.getLoc());
1939 else if (IDVal.startswith(".att_syntax")) {
1940 getParser().setAssemblerDialect(0);
1942 } else if (IDVal.startswith(".intel_syntax")) {
1943 getParser().setAssemblerDialect(1);
1944 if (getLexer().isNot(AsmToken::EndOfStatement)) {
1945 if(Parser.getTok().getString() == "noprefix") {
1946 // FIXME : Handle noprefix
1956 /// ParseDirectiveWord
1957 /// ::= .word [ expression (, expression)* ]
1958 bool X86AsmParser::ParseDirectiveWord(unsigned Size, SMLoc L) {
1959 if (getLexer().isNot(AsmToken::EndOfStatement)) {
1961 const MCExpr *Value;
1962 if (getParser().ParseExpression(Value))
1965 getParser().getStreamer().EmitValue(Value, Size, 0 /*addrspace*/);
1967 if (getLexer().is(AsmToken::EndOfStatement))
1970 // FIXME: Improve diagnostic.
1971 if (getLexer().isNot(AsmToken::Comma))
1972 return Error(L, "unexpected token in directive");
1981 /// ParseDirectiveCode
1982 /// ::= .code32 | .code64
1983 bool X86AsmParser::ParseDirectiveCode(StringRef IDVal, SMLoc L) {
1984 if (IDVal == ".code32") {
1986 if (is64BitMode()) {
1988 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
1990 } else if (IDVal == ".code64") {
1992 if (!is64BitMode()) {
1994 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code64);
1997 return Error(L, "unexpected directive " + IDVal);
2004 extern "C" void LLVMInitializeX86AsmLexer();
2006 // Force static initialization.
2007 extern "C" void LLVMInitializeX86AsmParser() {
2008 RegisterMCAsmParser<X86AsmParser> X(TheX86_32Target);
2009 RegisterMCAsmParser<X86AsmParser> Y(TheX86_64Target);
2010 LLVMInitializeX86AsmLexer();
2013 #define GET_REGISTER_MATCHER
2014 #define GET_MATCHER_IMPLEMENTATION
2015 #include "X86GenAsmMatcher.inc"