1 //===-- X86Operand.h - Parsed X86 machine instruction --------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #ifndef LLVM_LIB_TARGET_X86_ASMPARSER_X86OPERAND_H
11 #define LLVM_LIB_TARGET_X86_ASMPARSER_X86OPERAND_H
13 #include "X86AsmParserCommon.h"
14 #include "llvm/MC/MCExpr.h"
15 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
16 #include "llvm/ADT/STLExtras.h"
20 /// X86Operand - Instances of this class represent a parsed X86 machine
22 struct X86Operand : public MCParsedAsmOperand {
30 SMLoc StartLoc, EndLoc;
65 X86Operand(KindTy K, SMLoc Start, SMLoc End)
66 : Kind(K), StartLoc(Start), EndLoc(End) {}
68 StringRef getSymName() override { return SymName; }
69 void *getOpDecl() override { return OpDecl; }
71 /// getStartLoc - Get the location of the first token of this operand.
72 SMLoc getStartLoc() const override { return StartLoc; }
73 /// getEndLoc - Get the location of the last token of this operand.
74 SMLoc getEndLoc() const override { return EndLoc; }
75 /// getLocRange - Get the range between the first and last token of this
77 SMRange getLocRange() const { return SMRange(StartLoc, EndLoc); }
78 /// getOffsetOfLoc - Get the location of the offset operator.
79 SMLoc getOffsetOfLoc() const override { return OffsetOfLoc; }
81 void print(raw_ostream &OS) const override {}
83 StringRef getToken() const {
84 assert(Kind == Token && "Invalid access!");
85 return StringRef(Tok.Data, Tok.Length);
87 void setTokenValue(StringRef Value) {
88 assert(Kind == Token && "Invalid access!");
89 Tok.Data = Value.data();
90 Tok.Length = Value.size();
93 unsigned getReg() const override {
94 assert(Kind == Register && "Invalid access!");
98 const MCExpr *getImm() const {
99 assert(Kind == Immediate && "Invalid access!");
103 const MCExpr *getMemDisp() const {
104 assert(Kind == Memory && "Invalid access!");
107 unsigned getMemSegReg() const {
108 assert(Kind == Memory && "Invalid access!");
111 unsigned getMemBaseReg() const {
112 assert(Kind == Memory && "Invalid access!");
115 unsigned getMemIndexReg() const {
116 assert(Kind == Memory && "Invalid access!");
119 unsigned getMemScale() const {
120 assert(Kind == Memory && "Invalid access!");
124 bool isToken() const override {return Kind == Token; }
126 bool isImm() const override { return Kind == Immediate; }
128 bool isImmSExti16i8() const {
132 // If this isn't a constant expr, just assume it fits and let relaxation
134 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
138 // Otherwise, check the value is in a range that makes sense for this
140 return isImmSExti16i8Value(CE->getValue());
142 bool isImmSExti32i8() const {
146 // If this isn't a constant expr, just assume it fits and let relaxation
148 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
152 // Otherwise, check the value is in a range that makes sense for this
154 return isImmSExti32i8Value(CE->getValue());
156 bool isImmZExtu32u8() const {
160 // If this isn't a constant expr, just assume it fits and let relaxation
162 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
166 // Otherwise, check the value is in a range that makes sense for this
168 return isImmZExtu32u8Value(CE->getValue());
170 bool isImmSExti64i8() const {
174 // If this isn't a constant expr, just assume it fits and let relaxation
176 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
180 // Otherwise, check the value is in a range that makes sense for this
182 return isImmSExti64i8Value(CE->getValue());
184 bool isImmSExti64i32() const {
188 // If this isn't a constant expr, just assume it fits and let relaxation
190 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
194 // Otherwise, check the value is in a range that makes sense for this
196 return isImmSExti64i32Value(CE->getValue());
199 bool isOffsetOf() const override {
200 return OffsetOfLoc.getPointer();
203 bool needAddressOf() const override {
207 bool isMem() const override { return Kind == Memory; }
208 bool isMemUnsized() const {
209 return Kind == Memory && Mem.Size == 0;
211 bool isMem8() const {
212 return Kind == Memory && (!Mem.Size || Mem.Size == 8);
214 bool isMem16() const {
215 return Kind == Memory && (!Mem.Size || Mem.Size == 16);
217 bool isMem32() const {
218 return Kind == Memory && (!Mem.Size || Mem.Size == 32);
220 bool isMem64() const {
221 return Kind == Memory && (!Mem.Size || Mem.Size == 64);
223 bool isMem80() const {
224 return Kind == Memory && (!Mem.Size || Mem.Size == 80);
226 bool isMem128() const {
227 return Kind == Memory && (!Mem.Size || Mem.Size == 128);
229 bool isMem256() const {
230 return Kind == Memory && (!Mem.Size || Mem.Size == 256);
232 bool isMem512() const {
233 return Kind == Memory && (!Mem.Size || Mem.Size == 512);
236 bool isMemVX32() const {
237 return Kind == Memory && (!Mem.Size || Mem.Size == 32) &&
238 getMemIndexReg() >= X86::XMM0 && getMemIndexReg() <= X86::XMM15;
240 bool isMemVY32() const {
241 return Kind == Memory && (!Mem.Size || Mem.Size == 32) &&
242 getMemIndexReg() >= X86::YMM0 && getMemIndexReg() <= X86::YMM15;
244 bool isMemVX64() const {
245 return Kind == Memory && (!Mem.Size || Mem.Size == 64) &&
246 getMemIndexReg() >= X86::XMM0 && getMemIndexReg() <= X86::XMM15;
248 bool isMemVY64() const {
249 return Kind == Memory && (!Mem.Size || Mem.Size == 64) &&
250 getMemIndexReg() >= X86::YMM0 && getMemIndexReg() <= X86::YMM15;
252 bool isMemVZ32() const {
253 return Kind == Memory && (!Mem.Size || Mem.Size == 32) &&
254 getMemIndexReg() >= X86::ZMM0 && getMemIndexReg() <= X86::ZMM31;
256 bool isMemVZ64() const {
257 return Kind == Memory && (!Mem.Size || Mem.Size == 64) &&
258 getMemIndexReg() >= X86::ZMM0 && getMemIndexReg() <= X86::ZMM31;
261 bool isAbsMem() const {
262 return Kind == Memory && !getMemSegReg() && !getMemBaseReg() &&
263 !getMemIndexReg() && getMemScale() == 1;
266 bool isSrcIdx() const {
267 return !getMemIndexReg() && getMemScale() == 1 &&
268 (getMemBaseReg() == X86::RSI || getMemBaseReg() == X86::ESI ||
269 getMemBaseReg() == X86::SI) && isa<MCConstantExpr>(getMemDisp()) &&
270 cast<MCConstantExpr>(getMemDisp())->getValue() == 0;
272 bool isSrcIdx8() const {
273 return isMem8() && isSrcIdx();
275 bool isSrcIdx16() const {
276 return isMem16() && isSrcIdx();
278 bool isSrcIdx32() const {
279 return isMem32() && isSrcIdx();
281 bool isSrcIdx64() const {
282 return isMem64() && isSrcIdx();
285 bool isDstIdx() const {
286 return !getMemIndexReg() && getMemScale() == 1 &&
287 (getMemSegReg() == 0 || getMemSegReg() == X86::ES) &&
288 (getMemBaseReg() == X86::RDI || getMemBaseReg() == X86::EDI ||
289 getMemBaseReg() == X86::DI) && isa<MCConstantExpr>(getMemDisp()) &&
290 cast<MCConstantExpr>(getMemDisp())->getValue() == 0;
292 bool isDstIdx8() const {
293 return isMem8() && isDstIdx();
295 bool isDstIdx16() const {
296 return isMem16() && isDstIdx();
298 bool isDstIdx32() const {
299 return isMem32() && isDstIdx();
301 bool isDstIdx64() const {
302 return isMem64() && isDstIdx();
305 bool isMemOffs8() const {
306 return Kind == Memory && !getMemBaseReg() &&
307 !getMemIndexReg() && getMemScale() == 1 && (!Mem.Size || Mem.Size == 8);
309 bool isMemOffs16() const {
310 return Kind == Memory && !getMemBaseReg() &&
311 !getMemIndexReg() && getMemScale() == 1 && (!Mem.Size || Mem.Size == 16);
313 bool isMemOffs32() const {
314 return Kind == Memory && !getMemBaseReg() &&
315 !getMemIndexReg() && getMemScale() == 1 && (!Mem.Size || Mem.Size == 32);
317 bool isMemOffs64() const {
318 return Kind == Memory && !getMemBaseReg() &&
319 !getMemIndexReg() && getMemScale() == 1 && (!Mem.Size || Mem.Size == 64);
322 bool isReg() const override { return Kind == Register; }
324 bool isGR32orGR64() const {
325 return Kind == Register &&
326 (X86MCRegisterClasses[X86::GR32RegClassID].contains(getReg()) ||
327 X86MCRegisterClasses[X86::GR64RegClassID].contains(getReg()));
330 void addExpr(MCInst &Inst, const MCExpr *Expr) const {
331 // Add as immediates when possible.
332 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
333 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
335 Inst.addOperand(MCOperand::CreateExpr(Expr));
338 void addRegOperands(MCInst &Inst, unsigned N) const {
339 assert(N == 1 && "Invalid number of operands!");
340 Inst.addOperand(MCOperand::CreateReg(getReg()));
343 static unsigned getGR32FromGR64(unsigned RegNo) {
345 default: llvm_unreachable("Unexpected register");
346 case X86::RAX: return X86::EAX;
347 case X86::RCX: return X86::ECX;
348 case X86::RDX: return X86::EDX;
349 case X86::RBX: return X86::EBX;
350 case X86::RBP: return X86::EBP;
351 case X86::RSP: return X86::ESP;
352 case X86::RSI: return X86::ESI;
353 case X86::RDI: return X86::EDI;
354 case X86::R8: return X86::R8D;
355 case X86::R9: return X86::R9D;
356 case X86::R10: return X86::R10D;
357 case X86::R11: return X86::R11D;
358 case X86::R12: return X86::R12D;
359 case X86::R13: return X86::R13D;
360 case X86::R14: return X86::R14D;
361 case X86::R15: return X86::R15D;
362 case X86::RIP: return X86::EIP;
366 void addGR32orGR64Operands(MCInst &Inst, unsigned N) const {
367 assert(N == 1 && "Invalid number of operands!");
368 unsigned RegNo = getReg();
369 if (X86MCRegisterClasses[X86::GR64RegClassID].contains(RegNo))
370 RegNo = getGR32FromGR64(RegNo);
371 Inst.addOperand(MCOperand::CreateReg(RegNo));
374 void addImmOperands(MCInst &Inst, unsigned N) const {
375 assert(N == 1 && "Invalid number of operands!");
376 addExpr(Inst, getImm());
379 void addMemOperands(MCInst &Inst, unsigned N) const {
380 assert((N == 5) && "Invalid number of operands!");
381 Inst.addOperand(MCOperand::CreateReg(getMemBaseReg()));
382 Inst.addOperand(MCOperand::CreateImm(getMemScale()));
383 Inst.addOperand(MCOperand::CreateReg(getMemIndexReg()));
384 addExpr(Inst, getMemDisp());
385 Inst.addOperand(MCOperand::CreateReg(getMemSegReg()));
388 void addAbsMemOperands(MCInst &Inst, unsigned N) const {
389 assert((N == 1) && "Invalid number of operands!");
390 // Add as immediates when possible.
391 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getMemDisp()))
392 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
394 Inst.addOperand(MCOperand::CreateExpr(getMemDisp()));
397 void addSrcIdxOperands(MCInst &Inst, unsigned N) const {
398 assert((N == 2) && "Invalid number of operands!");
399 Inst.addOperand(MCOperand::CreateReg(getMemBaseReg()));
400 Inst.addOperand(MCOperand::CreateReg(getMemSegReg()));
402 void addDstIdxOperands(MCInst &Inst, unsigned N) const {
403 assert((N == 1) && "Invalid number of operands!");
404 Inst.addOperand(MCOperand::CreateReg(getMemBaseReg()));
407 void addMemOffsOperands(MCInst &Inst, unsigned N) const {
408 assert((N == 2) && "Invalid number of operands!");
409 // Add as immediates when possible.
410 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getMemDisp()))
411 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
413 Inst.addOperand(MCOperand::CreateExpr(getMemDisp()));
414 Inst.addOperand(MCOperand::CreateReg(getMemSegReg()));
417 static std::unique_ptr<X86Operand> CreateToken(StringRef Str, SMLoc Loc) {
418 SMLoc EndLoc = SMLoc::getFromPointer(Loc.getPointer() + Str.size());
419 auto Res = llvm::make_unique<X86Operand>(Token, Loc, EndLoc);
420 Res->Tok.Data = Str.data();
421 Res->Tok.Length = Str.size();
425 static std::unique_ptr<X86Operand>
426 CreateReg(unsigned RegNo, SMLoc StartLoc, SMLoc EndLoc,
427 bool AddressOf = false, SMLoc OffsetOfLoc = SMLoc(),
428 StringRef SymName = StringRef(), void *OpDecl = nullptr) {
429 auto Res = llvm::make_unique<X86Operand>(Register, StartLoc, EndLoc);
430 Res->Reg.RegNo = RegNo;
431 Res->AddressOf = AddressOf;
432 Res->OffsetOfLoc = OffsetOfLoc;
433 Res->SymName = SymName;
434 Res->OpDecl = OpDecl;
438 static std::unique_ptr<X86Operand> CreateImm(const MCExpr *Val,
439 SMLoc StartLoc, SMLoc EndLoc) {
440 auto Res = llvm::make_unique<X86Operand>(Immediate, StartLoc, EndLoc);
445 /// Create an absolute memory operand.
446 static std::unique_ptr<X86Operand>
447 CreateMem(const MCExpr *Disp, SMLoc StartLoc, SMLoc EndLoc, unsigned Size = 0,
448 StringRef SymName = StringRef(), void *OpDecl = nullptr) {
449 auto Res = llvm::make_unique<X86Operand>(Memory, StartLoc, EndLoc);
451 Res->Mem.Disp = Disp;
452 Res->Mem.BaseReg = 0;
453 Res->Mem.IndexReg = 0;
455 Res->Mem.Size = Size;
456 Res->SymName = SymName;
457 Res->OpDecl = OpDecl;
458 Res->AddressOf = false;
462 /// Create a generalized memory operand.
463 static std::unique_ptr<X86Operand>
464 CreateMem(unsigned SegReg, const MCExpr *Disp, unsigned BaseReg,
465 unsigned IndexReg, unsigned Scale, SMLoc StartLoc, SMLoc EndLoc,
466 unsigned Size = 0, StringRef SymName = StringRef(),
467 void *OpDecl = nullptr) {
468 // We should never just have a displacement, that should be parsed as an
469 // absolute memory operand.
470 assert((SegReg || BaseReg || IndexReg) && "Invalid memory operand!");
472 // The scale should always be one of {1,2,4,8}.
473 assert(((Scale == 1 || Scale == 2 || Scale == 4 || Scale == 8)) &&
475 auto Res = llvm::make_unique<X86Operand>(Memory, StartLoc, EndLoc);
476 Res->Mem.SegReg = SegReg;
477 Res->Mem.Disp = Disp;
478 Res->Mem.BaseReg = BaseReg;
479 Res->Mem.IndexReg = IndexReg;
480 Res->Mem.Scale = Scale;
481 Res->Mem.Size = Size;
482 Res->SymName = SymName;
483 Res->OpDecl = OpDecl;
484 Res->AddressOf = false;
489 } // End of namespace llvm