1 //===-- X86Operand.h - Parsed X86 machine instruction --------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #ifndef LLVM_LIB_TARGET_X86_ASMPARSER_X86OPERAND_H
11 #define LLVM_LIB_TARGET_X86_ASMPARSER_X86OPERAND_H
13 #include "X86AsmParserCommon.h"
14 #include "llvm/MC/MCExpr.h"
15 #include "llvm/MC/MCInst.h"
16 #include "llvm/MC/MCRegisterInfo.h"
17 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
18 #include "llvm/ADT/STLExtras.h"
19 #include "MCTargetDesc/X86MCTargetDesc.h"
23 /// X86Operand - Instances of this class represent a parsed X86 machine
25 struct X86Operand : public MCParsedAsmOperand {
33 SMLoc StartLoc, EndLoc;
69 X86Operand(KindTy K, SMLoc Start, SMLoc End)
70 : Kind(K), StartLoc(Start), EndLoc(End) {}
72 StringRef getSymName() override { return SymName; }
73 void *getOpDecl() override { return OpDecl; }
75 /// getStartLoc - Get the location of the first token of this operand.
76 SMLoc getStartLoc() const override { return StartLoc; }
77 /// getEndLoc - Get the location of the last token of this operand.
78 SMLoc getEndLoc() const override { return EndLoc; }
79 /// getLocRange - Get the range between the first and last token of this
81 SMRange getLocRange() const { return SMRange(StartLoc, EndLoc); }
82 /// getOffsetOfLoc - Get the location of the offset operator.
83 SMLoc getOffsetOfLoc() const override { return OffsetOfLoc; }
85 void print(raw_ostream &OS) const override {}
87 StringRef getToken() const {
88 assert(Kind == Token && "Invalid access!");
89 return StringRef(Tok.Data, Tok.Length);
91 void setTokenValue(StringRef Value) {
92 assert(Kind == Token && "Invalid access!");
93 Tok.Data = Value.data();
94 Tok.Length = Value.size();
97 unsigned getReg() const override {
98 assert(Kind == Register && "Invalid access!");
102 const MCExpr *getImm() const {
103 assert(Kind == Immediate && "Invalid access!");
107 const MCExpr *getMemDisp() const {
108 assert(Kind == Memory && "Invalid access!");
111 unsigned getMemSegReg() const {
112 assert(Kind == Memory && "Invalid access!");
115 unsigned getMemBaseReg() const {
116 assert(Kind == Memory && "Invalid access!");
119 unsigned getMemIndexReg() const {
120 assert(Kind == Memory && "Invalid access!");
123 unsigned getMemScale() const {
124 assert(Kind == Memory && "Invalid access!");
127 unsigned getMemModeSize() const {
128 assert(Kind == Memory && "Invalid access!");
132 bool isToken() const override {return Kind == Token; }
134 bool isImm() const override { return Kind == Immediate; }
136 bool isImmSExti16i8() const {
140 // If this isn't a constant expr, just assume it fits and let relaxation
142 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
146 // Otherwise, check the value is in a range that makes sense for this
148 return isImmSExti16i8Value(CE->getValue());
150 bool isImmSExti32i8() const {
154 // If this isn't a constant expr, just assume it fits and let relaxation
156 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
160 // Otherwise, check the value is in a range that makes sense for this
162 return isImmSExti32i8Value(CE->getValue());
164 bool isImmSExti64i8() const {
168 // If this isn't a constant expr, just assume it fits and let relaxation
170 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
174 // Otherwise, check the value is in a range that makes sense for this
176 return isImmSExti64i8Value(CE->getValue());
178 bool isImmSExti64i32() const {
182 // If this isn't a constant expr, just assume it fits and let relaxation
184 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
188 // Otherwise, check the value is in a range that makes sense for this
190 return isImmSExti64i32Value(CE->getValue());
193 bool isImmUnsignedi8() const {
194 if (!isImm()) return false;
195 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
196 if (!CE) return false;
197 return isImmUnsignedi8Value(CE->getValue());
200 bool isOffsetOf() const override {
201 return OffsetOfLoc.getPointer();
204 bool needAddressOf() const override {
208 bool isMem() const override { return Kind == Memory; }
209 bool isMemUnsized() const {
210 return Kind == Memory && Mem.Size == 0;
212 bool isMem8() const {
213 return Kind == Memory && (!Mem.Size || Mem.Size == 8);
215 bool isMem16() const {
216 return Kind == Memory && (!Mem.Size || Mem.Size == 16);
218 bool isMem32() const {
219 return Kind == Memory && (!Mem.Size || Mem.Size == 32);
221 bool isMem64() const {
222 return Kind == Memory && (!Mem.Size || Mem.Size == 64);
224 bool isMem80() const {
225 return Kind == Memory && (!Mem.Size || Mem.Size == 80);
227 bool isMem128() const {
228 return Kind == Memory && (!Mem.Size || Mem.Size == 128);
230 bool isMem256() const {
231 return Kind == Memory && (!Mem.Size || Mem.Size == 256);
233 bool isMem512() const {
234 return Kind == Memory && (!Mem.Size || Mem.Size == 512);
237 bool isMemVX32() const {
238 return Kind == Memory && (!Mem.Size || Mem.Size == 32) &&
239 getMemIndexReg() >= X86::XMM0 && getMemIndexReg() <= X86::XMM15;
241 bool isMemVY32() const {
242 return Kind == Memory && (!Mem.Size || Mem.Size == 32) &&
243 getMemIndexReg() >= X86::YMM0 && getMemIndexReg() <= X86::YMM15;
245 bool isMemVX64() const {
246 return Kind == Memory && (!Mem.Size || Mem.Size == 64) &&
247 getMemIndexReg() >= X86::XMM0 && getMemIndexReg() <= X86::XMM15;
249 bool isMemVY64() const {
250 return Kind == Memory && (!Mem.Size || Mem.Size == 64) &&
251 getMemIndexReg() >= X86::YMM0 && getMemIndexReg() <= X86::YMM15;
253 bool isMemVZ32() const {
254 return Kind == Memory && (!Mem.Size || Mem.Size == 32) &&
255 getMemIndexReg() >= X86::ZMM0 && getMemIndexReg() <= X86::ZMM31;
257 bool isMemVZ64() const {
258 return Kind == Memory && (!Mem.Size || Mem.Size == 64) &&
259 getMemIndexReg() >= X86::ZMM0 && getMemIndexReg() <= X86::ZMM31;
262 bool isAbsMem() const {
263 return Kind == Memory && !getMemSegReg() && !getMemBaseReg() &&
264 !getMemIndexReg() && getMemScale() == 1;
266 bool isAVX512RC() const{
270 bool isAbsMem16() const {
271 return isAbsMem() && Mem.ModeSize == 16;
274 bool isSrcIdx() const {
275 return !getMemIndexReg() && getMemScale() == 1 &&
276 (getMemBaseReg() == X86::RSI || getMemBaseReg() == X86::ESI ||
277 getMemBaseReg() == X86::SI) && isa<MCConstantExpr>(getMemDisp()) &&
278 cast<MCConstantExpr>(getMemDisp())->getValue() == 0;
280 bool isSrcIdx8() const {
281 return isMem8() && isSrcIdx();
283 bool isSrcIdx16() const {
284 return isMem16() && isSrcIdx();
286 bool isSrcIdx32() const {
287 return isMem32() && isSrcIdx();
289 bool isSrcIdx64() const {
290 return isMem64() && isSrcIdx();
293 bool isDstIdx() const {
294 return !getMemIndexReg() && getMemScale() == 1 &&
295 (getMemSegReg() == 0 || getMemSegReg() == X86::ES) &&
296 (getMemBaseReg() == X86::RDI || getMemBaseReg() == X86::EDI ||
297 getMemBaseReg() == X86::DI) && isa<MCConstantExpr>(getMemDisp()) &&
298 cast<MCConstantExpr>(getMemDisp())->getValue() == 0;
300 bool isDstIdx8() const {
301 return isMem8() && isDstIdx();
303 bool isDstIdx16() const {
304 return isMem16() && isDstIdx();
306 bool isDstIdx32() const {
307 return isMem32() && isDstIdx();
309 bool isDstIdx64() const {
310 return isMem64() && isDstIdx();
313 bool isMemOffs() const {
314 return Kind == Memory && !getMemBaseReg() && !getMemIndexReg() &&
318 bool isMemOffs16_8() const {
319 return isMemOffs() && Mem.ModeSize == 16 && (!Mem.Size || Mem.Size == 8);
321 bool isMemOffs16_16() const {
322 return isMemOffs() && Mem.ModeSize == 16 && (!Mem.Size || Mem.Size == 16);
324 bool isMemOffs16_32() const {
325 return isMemOffs() && Mem.ModeSize == 16 && (!Mem.Size || Mem.Size == 32);
327 bool isMemOffs32_8() const {
328 return isMemOffs() && Mem.ModeSize == 32 && (!Mem.Size || Mem.Size == 8);
330 bool isMemOffs32_16() const {
331 return isMemOffs() && Mem.ModeSize == 32 && (!Mem.Size || Mem.Size == 16);
333 bool isMemOffs32_32() const {
334 return isMemOffs() && Mem.ModeSize == 32 && (!Mem.Size || Mem.Size == 32);
336 bool isMemOffs32_64() const {
337 return isMemOffs() && Mem.ModeSize == 32 && (!Mem.Size || Mem.Size == 64);
339 bool isMemOffs64_8() const {
340 return isMemOffs() && Mem.ModeSize == 64 && (!Mem.Size || Mem.Size == 8);
342 bool isMemOffs64_16() const {
343 return isMemOffs() && Mem.ModeSize == 64 && (!Mem.Size || Mem.Size == 16);
345 bool isMemOffs64_32() const {
346 return isMemOffs() && Mem.ModeSize == 64 && (!Mem.Size || Mem.Size == 32);
348 bool isMemOffs64_64() const {
349 return isMemOffs() && Mem.ModeSize == 64 && (!Mem.Size || Mem.Size == 64);
352 bool isReg() const override { return Kind == Register; }
354 bool isGR32orGR64() const {
355 return Kind == Register &&
356 (X86MCRegisterClasses[X86::GR32RegClassID].contains(getReg()) ||
357 X86MCRegisterClasses[X86::GR64RegClassID].contains(getReg()));
360 void addExpr(MCInst &Inst, const MCExpr *Expr) const {
361 // Add as immediates when possible.
362 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
363 Inst.addOperand(MCOperand::createImm(CE->getValue()));
365 Inst.addOperand(MCOperand::createExpr(Expr));
368 void addRegOperands(MCInst &Inst, unsigned N) const {
369 assert(N == 1 && "Invalid number of operands!");
370 Inst.addOperand(MCOperand::createReg(getReg()));
373 static unsigned getGR32FromGR64(unsigned RegNo) {
375 default: llvm_unreachable("Unexpected register");
376 case X86::RAX: return X86::EAX;
377 case X86::RCX: return X86::ECX;
378 case X86::RDX: return X86::EDX;
379 case X86::RBX: return X86::EBX;
380 case X86::RBP: return X86::EBP;
381 case X86::RSP: return X86::ESP;
382 case X86::RSI: return X86::ESI;
383 case X86::RDI: return X86::EDI;
384 case X86::R8: return X86::R8D;
385 case X86::R9: return X86::R9D;
386 case X86::R10: return X86::R10D;
387 case X86::R11: return X86::R11D;
388 case X86::R12: return X86::R12D;
389 case X86::R13: return X86::R13D;
390 case X86::R14: return X86::R14D;
391 case X86::R15: return X86::R15D;
392 case X86::RIP: return X86::EIP;
396 void addGR32orGR64Operands(MCInst &Inst, unsigned N) const {
397 assert(N == 1 && "Invalid number of operands!");
398 unsigned RegNo = getReg();
399 if (X86MCRegisterClasses[X86::GR64RegClassID].contains(RegNo))
400 RegNo = getGR32FromGR64(RegNo);
401 Inst.addOperand(MCOperand::createReg(RegNo));
403 void addAVX512RCOperands(MCInst &Inst, unsigned N) const {
404 assert(N == 1 && "Invalid number of operands!");
405 addExpr(Inst, getImm());
407 void addImmOperands(MCInst &Inst, unsigned N) const {
408 assert(N == 1 && "Invalid number of operands!");
409 addExpr(Inst, getImm());
412 void addMemOperands(MCInst &Inst, unsigned N) const {
413 assert((N == 5) && "Invalid number of operands!");
414 Inst.addOperand(MCOperand::createReg(getMemBaseReg()));
415 Inst.addOperand(MCOperand::createImm(getMemScale()));
416 Inst.addOperand(MCOperand::createReg(getMemIndexReg()));
417 addExpr(Inst, getMemDisp());
418 Inst.addOperand(MCOperand::createReg(getMemSegReg()));
421 void addAbsMemOperands(MCInst &Inst, unsigned N) const {
422 assert((N == 1) && "Invalid number of operands!");
423 // Add as immediates when possible.
424 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getMemDisp()))
425 Inst.addOperand(MCOperand::createImm(CE->getValue()));
427 Inst.addOperand(MCOperand::createExpr(getMemDisp()));
430 void addSrcIdxOperands(MCInst &Inst, unsigned N) const {
431 assert((N == 2) && "Invalid number of operands!");
432 Inst.addOperand(MCOperand::createReg(getMemBaseReg()));
433 Inst.addOperand(MCOperand::createReg(getMemSegReg()));
435 void addDstIdxOperands(MCInst &Inst, unsigned N) const {
436 assert((N == 1) && "Invalid number of operands!");
437 Inst.addOperand(MCOperand::createReg(getMemBaseReg()));
440 void addMemOffsOperands(MCInst &Inst, unsigned N) const {
441 assert((N == 2) && "Invalid number of operands!");
442 // Add as immediates when possible.
443 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getMemDisp()))
444 Inst.addOperand(MCOperand::createImm(CE->getValue()));
446 Inst.addOperand(MCOperand::createExpr(getMemDisp()));
447 Inst.addOperand(MCOperand::createReg(getMemSegReg()));
450 static std::unique_ptr<X86Operand> CreateToken(StringRef Str, SMLoc Loc) {
451 SMLoc EndLoc = SMLoc::getFromPointer(Loc.getPointer() + Str.size());
452 auto Res = llvm::make_unique<X86Operand>(Token, Loc, EndLoc);
453 Res->Tok.Data = Str.data();
454 Res->Tok.Length = Str.size();
458 static std::unique_ptr<X86Operand>
459 CreateReg(unsigned RegNo, SMLoc StartLoc, SMLoc EndLoc,
460 bool AddressOf = false, SMLoc OffsetOfLoc = SMLoc(),
461 StringRef SymName = StringRef(), void *OpDecl = nullptr) {
462 auto Res = llvm::make_unique<X86Operand>(Register, StartLoc, EndLoc);
463 Res->Reg.RegNo = RegNo;
464 Res->AddressOf = AddressOf;
465 Res->OffsetOfLoc = OffsetOfLoc;
466 Res->SymName = SymName;
467 Res->OpDecl = OpDecl;
471 static std::unique_ptr<X86Operand> CreateImm(const MCExpr *Val,
472 SMLoc StartLoc, SMLoc EndLoc) {
473 auto Res = llvm::make_unique<X86Operand>(Immediate, StartLoc, EndLoc);
478 /// Create an absolute memory operand.
479 static std::unique_ptr<X86Operand>
480 CreateMem(unsigned ModeSize, const MCExpr *Disp, SMLoc StartLoc, SMLoc EndLoc,
481 unsigned Size = 0, StringRef SymName = StringRef(),
482 void *OpDecl = nullptr) {
483 auto Res = llvm::make_unique<X86Operand>(Memory, StartLoc, EndLoc);
485 Res->Mem.Disp = Disp;
486 Res->Mem.BaseReg = 0;
487 Res->Mem.IndexReg = 0;
489 Res->Mem.Size = Size;
490 Res->Mem.ModeSize = ModeSize;
491 Res->SymName = SymName;
492 Res->OpDecl = OpDecl;
493 Res->AddressOf = false;
497 /// Create a generalized memory operand.
498 static std::unique_ptr<X86Operand>
499 CreateMem(unsigned ModeSize, unsigned SegReg, const MCExpr *Disp,
500 unsigned BaseReg, unsigned IndexReg, unsigned Scale, SMLoc StartLoc,
501 SMLoc EndLoc, unsigned Size = 0, StringRef SymName = StringRef(),
502 void *OpDecl = nullptr) {
503 // We should never just have a displacement, that should be parsed as an
504 // absolute memory operand.
505 assert((SegReg || BaseReg || IndexReg) && "Invalid memory operand!");
507 // The scale should always be one of {1,2,4,8}.
508 assert(((Scale == 1 || Scale == 2 || Scale == 4 || Scale == 8)) &&
510 auto Res = llvm::make_unique<X86Operand>(Memory, StartLoc, EndLoc);
511 Res->Mem.SegReg = SegReg;
512 Res->Mem.Disp = Disp;
513 Res->Mem.BaseReg = BaseReg;
514 Res->Mem.IndexReg = IndexReg;
515 Res->Mem.Scale = Scale;
516 Res->Mem.Size = Size;
517 Res->Mem.ModeSize = ModeSize;
518 Res->SymName = SymName;
519 Res->OpDecl = OpDecl;
520 Res->AddressOf = false;
525 } // End of namespace llvm