1 //===-- X86IntelInstPrinter.cpp - AT&T assembly instruction printing ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file includes code for rendering MCInst instances as AT&T-style
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "asm-printer"
16 #include "X86IntelInstPrinter.h"
17 #include "llvm/MC/MCInst.h"
18 #include "llvm/MC/MCAsmInfo.h"
19 #include "llvm/MC/MCExpr.h"
20 #include "llvm/Support/ErrorHandling.h"
21 #include "llvm/Support/FormattedStream.h"
22 #include "X86GenInstrNames.inc"
25 // Include the auto-generated portion of the assembly writer.
26 #define MachineInstr MCInst
27 #define NO_ASM_WRITER_BOILERPLATE
28 #define X86IntelAsmPrinter X86IntelInstPrinter
29 #include "X86GenAsmWriter1.inc"
32 void X86IntelInstPrinter::printInst(const MCInst *MI) { printInstruction(MI); }
34 void X86IntelInstPrinter::printSSECC(const MCInst *MI, unsigned Op) {
35 switch (MI->getOperand(Op).getImm()) {
36 default: llvm_unreachable("Invalid ssecc argument!");
37 case 0: O << "eq"; break;
38 case 1: O << "lt"; break;
39 case 2: O << "le"; break;
40 case 3: O << "unord"; break;
41 case 4: O << "neq"; break;
42 case 5: O << "nlt"; break;
43 case 6: O << "nle"; break;
44 case 7: O << "ord"; break;
48 /// print_pcrel_imm - This is used to print an immediate value that ends up
49 /// being encoded as a pc-relative value. These print slightly differently, for
50 /// example, a $ is not emitted.
51 void X86IntelInstPrinter::print_pcrel_imm(const MCInst *MI, unsigned OpNo) {
52 const MCOperand &Op = MI->getOperand(OpNo);
56 assert(Op.isExpr() && "unknown pcrel immediate operand");
57 Op.getExpr()->print(O, &MAI);
61 static void PrintRegName(raw_ostream &O, StringRef RegName) {
62 for (unsigned i = 0, e = RegName.size(); i != e; ++i)
63 O << (char)toupper(RegName[i]);
66 void X86IntelInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
67 const char *Modifier) {
68 assert(Modifier == 0 && "Modifiers should not be used");
70 const MCOperand &Op = MI->getOperand(OpNo);
72 PrintRegName(O, getRegisterName(Op.getReg()));
73 } else if (Op.isImm()) {
76 assert(Op.isExpr() && "unknown operand kind in printOperand");
77 Op.getExpr()->print(O, &MAI);
81 void X86IntelInstPrinter::printLeaMemReference(const MCInst *MI, unsigned Op) {
82 const MCOperand &BaseReg = MI->getOperand(Op);
83 unsigned ScaleVal = MI->getOperand(Op+1).getImm();
84 const MCOperand &IndexReg = MI->getOperand(Op+2);
85 const MCOperand &DispSpec = MI->getOperand(Op+3);
89 bool NeedPlus = false;
90 if (BaseReg.getReg()) {
95 if (IndexReg.getReg()) {
96 if (NeedPlus) O << " + ";
99 printOperand(MI, Op+2);
104 if (!DispSpec.isImm()) {
105 if (NeedPlus) O << " + ";
106 assert(DispSpec.isExpr() && "non-immediate displacement for LEA?");
107 DispSpec.getExpr()->print(O, &MAI);
109 int64_t DispVal = DispSpec.getImm();
110 if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg())) {
126 void X86IntelInstPrinter::printMemReference(const MCInst *MI, unsigned Op) {
127 // If this has a segment register, print it.
128 if (MI->getOperand(Op+4).getReg()) {
129 printOperand(MI, Op+4);
132 printLeaMemReference(MI, Op);